coreboot-gerrit June 2020

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Change in coreboot[master]: soc/intel/skx: Lets iasl automatically resolve _PRT package size
by Arthur Heymans (Code Review) 02 Jun '20

02 Jun '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41529 ) Change subject: soc/intel/skx: Lets iasl automatically resolve _PRT package size ...................................................................... soc/intel/skx: Lets iasl automatically resolve _PRT package size BUILD_TIMELESS=1 with ocp/tiogapass results in identical binaries. Change-Id: Iff97f3cc0ce800036be32b2758c60e4b7ac39fe9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl 1 file changed, 98 insertions(+), 98 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/41529/1 diff --git a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl index 2f5328f..9926367 100644 --- a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl +++ b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl @@ -7,225 +7,225 @@ */ #define GEN_PCIE_LEGACY_IRQ() \ - Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, \ - Package (0x04) { 0x0001FFFF, 0x00, LNKA, 0x00 }, \ - Package (0x04) { 0x0002FFFF, 0x00, LNKA, 0x00 }, \ - Package (0x04) { 0x0003FFFF, 0x00, LNKA, 0x00 } + Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, \ + Package () { 0x0001FFFF, 0x00, LNKA, 0x00 }, \ + Package () { 0x0002FFFF, 0x00, LNKA, 0x00 }, \ + Package () { 0x0003FFFF, 0x00, LNKA, 0x00 } #define GEN_UNCORE_LEGACY_IRQ(dev) \ - Package (0x04) { ##dev, 0x00, LNKA, 0x00 }, \ - Package (0x04) { ##dev, 0x01, LNKB, 0x00 }, \ - Package (0x04) { ##dev, 0x02, LNKC, 0x00 }, \ - Package (0x04) { ##dev, 0x03, LNKD, 0x00 } + Package () { ##dev, 0x00, LNKA, 0x00 }, \ + Package () { ##dev, 0x01, LNKB, 0x00 }, \ + Package () { ##dev, 0x02, LNKC, 0x00 }, \ + Package () { ##dev, 0x03, LNKD, 0x00 } #define GEN_PCIE_IOAPIC_IRQ(irq) \ - Package (0x04) { 0x0000FFFF, 0x00, 0x00, ##irq }, \ - Package (0x04) { 0x0001FFFF, 0x00, 0x00, ##irq }, \ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, ##irq }, \ - Package (0x04) { 0x0003FFFF, 0x00, 0x00, ##irq } + Package () { 0x0000FFFF, 0x00, 0x00, ##irq }, \ + Package () { 0x0001FFFF, 0x00, 0x00, ##irq }, \ + Package () { 0x0002FFFF, 0x00, 0x00, ##irq }, \ + Package () { 0x0003FFFF, 0x00, 0x00, ##irq } #define GEN_UNCORE_IOAPIC_IRQ(dev,irq1,irq2,irq3,irq4) \ - Package (0x04) { ##dev, 0x00, 0x00, ##irq1 }, \ - Package (0x04) { ##dev, 0x01, 0x00, ##irq2 }, \ - Package (0x04) { ##dev, 0x02, 0x00, ##irq3 }, \ - Package (0x04) { ##dev, 0x03, 0x00, ##irq4 } + Package () { ##dev, 0x00, 0x00, ##irq1 }, \ + Package () { ##dev, 0x01, 0x00, ##irq2 }, \ + Package () { ##dev, 0x02, 0x00, ##irq3 }, \ + Package () { ##dev, 0x03, 0x00, ##irq4 } // Socket 0, IIOStack 0 device legacy interrupt routing Name (PR00, Package (0x28) { // [DMI0]: Legacy PCI Express Port 0 - Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, // [CB0A]: CBDMA // [CB0E]: CBDMA - Package (0x04) { 0x0004FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0004FFFF, 0x00, LNKA, 0x00 }, // [CB0B]: CBDMA // [CB0F]: CBDMA - Package (0x04) { 0x0004FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0004FFFF, 0x01, LNKB, 0x00 }, // [CB0C]: CBDMA // [CB0G]: CBDMA - Package (0x04) { 0x0004FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0004FFFF, 0x02, LNKC, 0x00 }, // [CB0D]: CBDMA // [CB0H]: CBDMA - Package (0x04) { 0x0004FFFF, 0x03, LNKD, 0x00 }, + Package () { 0x0004FFFF, 0x03, LNKD, 0x00 }, // Uncore 0 UBOX Device - Package (0x04) { 0x0008FFFF, 0x00, LNKA, 0x00 }, - Package (0x04) { 0x0008FFFF, 0x01, LNKB, 0x00 }, - Package (0x04) { 0x0008FFFF, 0x02, LNKC, 0x00 }, - Package (0x04) { 0x0008FFFF, 0x03, LNKD, 0x00 }, + Package () { 0x0008FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0008FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0008FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0008FFFF, 0x03, LNKD, 0x00 }, // [DISP]: Display Controller - Package (0x04) { 0x000FFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x000FFFFF, 0x00, LNKA, 0x00 }, // [IHC1]: HECI #1 // [IHC3]: HECI #3 - Package (0x04) { 0x0010FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0010FFFF, 0x00, LNKA, 0x00 }, // [IHC2]: HECI #2 - Package (0x04) { 0x0010FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0010FFFF, 0x01, LNKB, 0x00 }, // [IIDR]: IDE-Redirection (IDE-R) - Package (0x04) { 0x0010FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0010FFFF, 0x02, LNKC, 0x00 }, // [IMKT]: Keyboard and Text (KT) Redirection - Package (0x04) { 0x0010FFFF, 0x03, LNKD, 0x00 }, + Package () { 0x0010FFFF, 0x03, LNKD, 0x00 }, // [SAT2]: sSATA Host controller 2 on PCH - Package (0x04) { 0x0011FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0011FFFF, 0x00, LNKA, 0x00 }, // // [XHCI]: xHCI controller 1 on PCH - Package (0x04) { 0x0014FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0014FFFF, 0x00, LNKA, 0x00 }, // [OTG0]: USB Device Controller (OTG) on PCH - Package (0x04) { 0x0014FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0014FFFF, 0x01, LNKB, 0x00 }, // [TERM]: Thermal Subsystem on PCH - Package (0x04) { 0x0014FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0014FFFF, 0x02, LNKC, 0x00 }, // [CAMR]: Camera IO Host Controller on PCH - Package (0x04) { 0x0014FFFF, 0x03, LNKD, 0x00 }, + Package () { 0x0014FFFF, 0x03, LNKD, 0x00 }, // [HEC1]: HECI #1 on PCH // [HEC3]: HECI #3 on PCH - Package (0x04) { 0x0016FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0016FFFF, 0x00, LNKA, 0x00 }, // [HEC2]: HECI #2 on PCH - Package (0x04) { 0x0016FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0016FFFF, 0x01, LNKB, 0x00 }, // [IDER]: ME IDE redirect on PCH - Package (0x04) { 0x0016FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0016FFFF, 0x02, LNKC, 0x00 }, // [MEKT]: MEKT on PCH - Package (0x04) { 0x0016FFFF, 0x03, LNKD, 0x00 }, + Package () { 0x0016FFFF, 0x03, LNKD, 0x00 }, // [SAT1]: SATA controller 1 on PCH - Package (0x04) { 0x0017FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0017FFFF, 0x00, LNKA, 0x00 }, // [NAN1]: NAND Cycle Router on PCH - Package (0x04) { 0x0018FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0018FFFF, 0x00, LNKA, 0x00 }, // [RP17]: PCIE PCH Root Port #17 - Package (0x04) { 0x001BFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x001BFFFF, 0x00, LNKA, 0x00 }, // [RP18]: PCIE PCH Root Port #18 - Package (0x04) { 0x001BFFFF, 0x01, LNKB, 0x00 }, + Package () { 0x001BFFFF, 0x01, LNKB, 0x00 }, // [RP19]: PCIE PCH Root Port #19 - Package (0x04) { 0x001BFFFF, 0x02, LNKC, 0x00 }, + Package () { 0x001BFFFF, 0x02, LNKC, 0x00 }, // [RP20]: PCIE PCH Root Port #20 - Package (0x04) { 0x001BFFFF, 0x03, LNKD, 0x00 }, + Package () { 0x001BFFFF, 0x03, LNKD, 0x00 }, // [RP01]: PCIE PCH Root Port #1 // [RP05]: PCIE PCH Root Port #5 - Package (0x04) { 0x001CFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x001CFFFF, 0x00, LNKA, 0x00 }, // [RP02]: PCIE PCH Root Port #2 // [RP06]: PCIE PCH Root Port #6 - Package (0x04) { 0x001CFFFF, 0x01, LNKB, 0x00 }, + Package () { 0x001CFFFF, 0x01, LNKB, 0x00 }, // [RP03]: PCIE PCH Root Port #3 // [RP07]: PCIE PCH Root Port #7 - Package (0x04) { 0x001CFFFF, 0x02, LNKC, 0x00 }, + Package () { 0x001CFFFF, 0x02, LNKC, 0x00 }, // [RP04]: PCIE PCH Root Port #4 // [RP08]: PCIE PCH Root Port #8 - Package (0x04) { 0x001CFFFF, 0x03, LNKD, 0x00 }, + Package () { 0x001CFFFF, 0x03, LNKD, 0x00 }, // [RP09]: PCIE PCH Root Port #9 // [RP13]: PCIE PCH Root Port #13 - Package (0x04) { 0x001DFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x001DFFFF, 0x00, LNKA, 0x00 }, // [RP10]: PCIE PCH Root Port #10 // [RP14]: PCIE PCH Root Port #14 - Package (0x04) { 0x001DFFFF, 0x01, LNKB, 0x00 }, + Package () { 0x001DFFFF, 0x01, LNKB, 0x00 }, // [RP11]: PCIE PCH Root Port #11 // [RP15]: PCIE PCH Root Port #15 - Package (0x04) { 0x001DFFFF, 0x02, LNKC, 0x00 }, + Package () { 0x001DFFFF, 0x02, LNKC, 0x00 }, // [RP12]: PCIE PCH Root Port #12 // [RP16]: PCIE PCH Root Port #16 - Package (0x04) { 0x001DFFFF, 0x03, LNKD, 0x00 }, + Package () { 0x001DFFFF, 0x03, LNKD, 0x00 }, // [UAR0]: UART #0 on PCH - Package (0x04) { 0x001EFFFF, 0x02, LNKC, 0x00 }, + Package () { 0x001EFFFF, 0x02, LNKC, 0x00 }, // [UAR1]: UART #1 on PCH - Package (0x04) { 0x001EFFFF, 0x03, LNKD, 0x00 }, + Package () { 0x001EFFFF, 0x03, LNKD, 0x00 }, // [CAVS]: HD Audio Subsystem Controller on PCH // [SMBS]: SMBus controller on PCH // [GBE1]: GbE Controller on PCH // [NTPK]: Northpeak Controller on PCH - Package (0x04) { 0x001FFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x001FFFFF, 0x00, LNKA, 0x00 }, }) // Socket 0, IIOStack 0 device IOAPIC interrupt routing Name (AR00, Package (0x28) { // [DMI0]: Legacy PCI Express Port 0 - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1F }, + Package () { 0x0000FFFF, 0x00, 0x00, 0x1F }, // [CB0A]: CB3DMA // [CB0E]: CB3DMA - Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, + Package () { 0x0004FFFF, 0x00, 0x00, 0x1A }, // [CB0B]: CB3DMA // [CB0F]: CB3DMA - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B }, + Package () { 0x0004FFFF, 0x01, 0x00, 0x1B }, // [CB0C]: CB3DMA // [CB0G]: CB3DMA - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A }, + Package () { 0x0004FFFF, 0x02, 0x00, 0x1A }, // [CB0D]: CB3DMA // [CB0H]: CB3DMA - Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B }, + Package () { 0x0004FFFF, 0x03, 0x00, 0x1B }, // [UBX0]: Uncore 0 UBOX Device - Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x18 }, - Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x1C }, - Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x1D }, - Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x1E }, + Package () { 0x0008FFFF, 0x00, 0x00, 0x18 }, + Package () { 0x0008FFFF, 0x01, 0x00, 0x1C }, + Package () { 0x0008FFFF, 0x02, 0x00, 0x1D }, + Package () { 0x0008FFFF, 0x03, 0x00, 0x1E }, // [DISP]: Display Controller - Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x10 }, + Package () { 0x000FFFFF, 0x00, 0x00, 0x10 }, // [IHC1]: HECI #1 // [IHC3]: HECI #3 - Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0010FFFF, 0x00, 0x00, 0x10 }, // [IHC2]: HECI #2 - Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x11 }, + Package () { 0x0010FFFF, 0x01, 0x00, 0x11 }, // [IIDR]: IDE-Redirection (IDE-R) - Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x12 }, + Package () { 0x0010FFFF, 0x02, 0x00, 0x12 }, // [IMKT]: Keyboard and Text (KT) Redirection - Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x13 }, + Package () { 0x0010FFFF, 0x03, 0x00, 0x13 }, // [SAT2]: sSATA Host controller 2 on PCH - Package (0x04) { 0x0011FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0011FFFF, 0x00, 0x00, 0x10 }, // [XHCI]: xHCI controller 1 on PCH - Package (0x04) { 0x0014FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0014FFFF, 0x00, 0x00, 0x10 }, // [OTG0]: USB Device Controller (OTG) on PCH - Package (0x04) { 0x0014FFFF, 0x01, 0x00, 0x11 }, + Package () { 0x0014FFFF, 0x01, 0x00, 0x11 }, // [TERM]: Thermal Subsystem on PCH - Package (0x04) { 0x0014FFFF, 0x02, 0x00, 0x12 }, + Package () { 0x0014FFFF, 0x02, 0x00, 0x12 }, // [CAMR]: Camera IO Host Controller on PCH - Package (0x04) { 0x0014FFFF, 0x03, 0x00, 0x13 }, + Package () { 0x0014FFFF, 0x03, 0x00, 0x13 }, // [HEC1]: HECI #1 on PCH // [HEC3]: HECI #3 on PCH - Package (0x04) { 0x0016FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0016FFFF, 0x00, 0x00, 0x10 }, // [HEC2]: HECI #2 on PCH - Package (0x04) { 0x0016FFFF, 0x01, 0x00, 0x11 }, + Package () { 0x0016FFFF, 0x01, 0x00, 0x11 }, // [IDER]: ME IDE redirect on PCH - Package (0x04) { 0x0016FFFF, 0x02, 0x00, 0x12 }, + Package () { 0x0016FFFF, 0x02, 0x00, 0x12 }, // [MEKT]: MEKT on PCH - Package (0x04) { 0x0016FFFF, 0x03, 0x00, 0x13 }, + Package () { 0x0016FFFF, 0x03, 0x00, 0x13 }, // [SAT1]: SATA controller 1 on PCH - Package (0x04) { 0x0017FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0017FFFF, 0x00, 0x00, 0x10 }, // [NAN1]: NAND Cycle Router on PCH - Package (0x04) { 0x0018FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0018FFFF, 0x00, 0x00, 0x10 }, // [RP17]: PCIE PCH Root Port #17 - Package (0x04) { 0x001BFFFF, 0x00, 0x00, 0x10 }, + Package () { 0x001BFFFF, 0x00, 0x00, 0x10 }, // [RP18]: PCIE PCH Root Port #18 - Package (0x04) { 0x001BFFFF, 0x01, 0x00, 0x11 }, + Package () { 0x001BFFFF, 0x01, 0x00, 0x11 }, // [RP19]: PCIE PCH Root Port #19 - Package (0x04) { 0x001BFFFF, 0x02, 0x00, 0x12 }, + Package () { 0x001BFFFF, 0x02, 0x00, 0x12 }, // [RP20]: PCIE PCH Root Port #20 - Package (0x04) { 0x001BFFFF, 0x03, 0x00, 0x13 }, + Package () { 0x001BFFFF, 0x03, 0x00, 0x13 }, // [RP01]: PCIE PCH Root Port #1 // [RP05]: PCIE PCH Root Port #5 - Package (0x04) { 0x001CFFFF, 0x00, 0x00, 0x10 }, + Package () { 0x001CFFFF, 0x00, 0x00, 0x10 }, // [RP02]: PCIE PCH Root Port #2 // [RP06]: PCIE PCH Root Port #6 - Package (0x04) { 0x001CFFFF, 0x01, 0x00, 0x11 }, + Package () { 0x001CFFFF, 0x01, 0x00, 0x11 }, // [RP03]: PCIE PCH Root Port #3 // [RP07]: PCIE PCH Root Port #7 - Package (0x04) { 0x001CFFFF, 0x02, 0x00, 0x12 }, + Package () { 0x001CFFFF, 0x02, 0x00, 0x12 }, // [RP04]: PCIE PCH Root Port #4 // [RP08]: PCIE PCH Root Port #8 - Package (0x04) { 0x001CFFFF, 0x03, 0x00, 0x13 }, + Package () { 0x001CFFFF, 0x03, 0x00, 0x13 }, // [RP09]: PCIE PCH Root Port #9 // [RP13]: PCIE PCH Root Port #13 - Package (0x04) { 0x001DFFFF, 0x00, 0x00, 0x10 }, + Package () { 0x001DFFFF, 0x00, 0x00, 0x10 }, // [RP10]: PCIE PCH Root Port #10 // [RP14]: PCIE PCH Root Port #14 - Package (0x04) { 0x001DFFFF, 0x01, 0x00, 0x11 }, + Package () { 0x001DFFFF, 0x01, 0x00, 0x11 }, // [RP11]: PCIE PCH Root Port #11 // [RP15]: PCIE PCH Root Port #15 - Package (0x04) { 0x001DFFFF, 0x02, 0x00, 0x12 }, + Package () { 0x001DFFFF, 0x02, 0x00, 0x12 }, // [RP12]: PCIE PCH Root Port #12 // [RP16]: PCIE PCH Root Port #16 - Package (0x04) { 0x001DFFFF, 0x03, 0x00, 0x13 }, + Package () { 0x001DFFFF, 0x03, 0x00, 0x13 }, // [UAR0]: UART #0 on PCH - Package (0x04) { 0x001EFFFF, 0x02, 0x00, 0x16 }, + Package () { 0x001EFFFF, 0x02, 0x00, 0x16 }, // [UAR1]: UART #1 on PCH - Package (0x04) { 0x001EFFFF, 0x03, 0x00, 0x17 }, + Package () { 0x001EFFFF, 0x03, 0x00, 0x17 }, // [CAVS]: HD Audio Subsystem Controller on PCH // [SMBS]: SMBus controller on PCH // [GBE1]: GbE Controller on PCH // [NTPK]: Northpeak Controller on PCH - Package (0x04) { 0x001FFFFF, 0x00, 0x00, 0x10 }, + Package () { 0x001FFFFF, 0x00, 0x00, 0x10 }, }) // Socket 0, IIOStack 1 device legacy interrupt routing @@ -406,7 +406,7 @@ Name (PR40, Package (0x09) { // DMI - Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, // CBDMA GEN_UNCORE_LEGACY_IRQ(0x0004FFFF), @@ -419,7 +419,7 @@ Name (AR40, Package (0x09) { // DMI - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x4F }, + Package () { 0x0000FFFF, 0x00, 0x00, 0x4F }, // CBDMA GEN_UNCORE_IOAPIC_IRQ(0x0004FFFF, 0x4A, 0x4B, 0x4A, 0x4B), -- To view, visit https://review.coreboot.org/c/coreboot/+/41529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff97f3cc0ce800036be32b2758c60e4b7ac39fe9 Gerrit-Change-Number: 41529 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

7 9

Change in coreboot[master]: lockdown: Fix missing spaces in boot log
by Daniel Gröber (dxld) (Code Review) 02 Jun '20

02 Jun '20

Hello Daniel Gröber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41748 to review the following change. Change subject: lockdown: Fix missing spaces in boot log ...................................................................... lockdown: Fix missing spaces in boot log Change-Id: I414703c53d356c6a69be515596c178997eed82e3 Signed-off-by: Daniel Gröber <dxld(a)darkboxed.org> --- M src/security/lockdown/lockdown.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/41748/1 diff --git a/src/security/lockdown/lockdown.c b/src/security/lockdown/lockdown.c index 81478cc..c2e2ac3 100644 --- a/src/security/lockdown/lockdown.c +++ b/src/security/lockdown/lockdown.c @@ -28,7 +28,7 @@ printk(BIOS_DEBUG, "'WP_RO only'"); lock_type = CTRLR_WP; } - printk(BIOS_DEBUG, "using CTRL...\n"); + printk(BIOS_DEBUG, " using CTRL...\n"); } else { if (CONFIG(BOOTMEDIA_LOCK_WHOLE_RO)) { printk(BIOS_DEBUG, "'readonly'"); @@ -37,7 +37,7 @@ printk(BIOS_DEBUG, "'WP_RO only'"); lock_type = MEDIA_WP; } - printk(BIOS_DEBUG, "using flash chip...\n"); + printk(BIOS_DEBUG, " using flash chip...\n"); } if (CONFIG(BOOTMEDIA_LOCK_WPRO_VBOOT_RO)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/41748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I414703c53d356c6a69be515596c178997eed82e3 Gerrit-Change-Number: 41748 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Gröber (dxld) Gerrit-Reviewer: Daniel Gröber <dxld(a)darkboxed.org> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: mainboard(s): drop redundant entries from Makefiles
by Wim Vervoorn (Code Review) 02 Jun '20

02 Jun '20

Wim Vervoorn has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41107 ) Change subject: mainboard(s): drop redundant entries from Makefiles ...................................................................... Patch Set 10: (2 comments) https://review.coreboot.org/c/coreboot/+/41107/10/src/mainboard/facebook/fb… File src/mainboard/facebook/fbg1701/Makefile.inc: https://review.coreboot.org/c/coreboot/+/41107/10/src/mainboard/facebook/fb… PS10, Line 14: ramstage-y += hda_verb.c This removes the hds_verb.c from the build. It isn't included in another way. AZALIA_PLUGIN_SUPPORT is not set and the Braswell support doesn't pull it in either. https://review.coreboot.org/c/coreboot/+/41107/10/src/mainboard/portwell/m1… File src/mainboard/portwell/m107/Makefile.inc: https://review.coreboot.org/c/coreboot/+/41107/10/src/mainboard/portwell/m1… PS10, Line 6: ramstage-y += hda_verb.c This removes the hds_verb.c from the build. It isn't included in another way. AZALIA_PLUGIN_SUPPORT is not set and the Braswell support doesn't pull it in either. As a side item, wouldn't it be good to somehow document which files will be included implicitely from the mainboard directory? This makes creating a new mainboard directory a bit easier and prevents the inclusion of files that are not required. -- To view, visit https://review.coreboot.org/c/coreboot/+/41107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1961646c5ed4ae6a1308ce0e8e15792970da4e0d Gerrit-Change-Number: 41107 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Jun 2020 08:46:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/sconfig: Move default includes out of emit_chips()
by Nico Huber (Code Review) 02 Jun '20

02 Jun '20

Hello Furquan Shaikh, Patrick Georgi, Angel Pons, Arthur Heymans, Kyösti Mälkki, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41744 to review the following change. Change subject: util/sconfig: Move default includes out of emit_chips() ...................................................................... util/sconfig: Move default includes out of emit_chips() This should make it easier to add more includes. Change-Id: Ib4a25352901408c2b36de4972391df742a0d8037 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/sconfig/main.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/41744/1 diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 3e3bd17..0d8f7f8 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -889,9 +889,6 @@ { struct chip *tmp = chip; - fprintf(fil, "#include <device/device.h>\n"); - fprintf(fil, "#include <device/pci.h>\n"); - while (chip) { if (chip->chiph_exists) fprintf(fil, "#include \"%s/chip.h\"\n", chip->name); @@ -1347,6 +1344,9 @@ fprintf(autohead, "#define __STATIC_DEVICE_TREE_H\n\n"); fprintf(autohead, "#include <device/device.h>\n\n"); + fprintf(autogen, "#include <device/device.h>\n"); + fprintf(autogen, "#include <device/pci.h>\n\n"); + emit_chips(autogen); walk_device_tree(autogen, autohead, &base_root_dev, inherit_subsystem_ids); -- To view, visit https://review.coreboot.org/c/coreboot/+/41744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4a25352901408c2b36de4972391df742a0d8037 Gerrit-Change-Number: 41744 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Update SMBIOS type 0 firmware version by VPD variable
by Jingle Hsu (Code Review) 02 Jun '20

02 Jun '20

Jingle Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41720 ) Change subject: mb/ocp/deltalake: Update SMBIOS type 0 firmware version by VPD variable ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/41720/9/src/mainboard/ocp/deltalak… File src/mainboard/ocp/deltalake/ramstage.c: https://review.coreboot.org/c/coreboot/+/41720/9/src/mainboard/ocp/deltalak… PS9, Line 8: <console/console.h> > duplicated Done -- To view, visit https://review.coreboot.org/c/coreboot/+/41720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98a8fe1135728f31ec154d6340d19be8d8f980ba Gerrit-Change-Number: 41720 Gerrit-PatchSet: 11 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 02 Jun 2020 08:43:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/deltalake: Update SMBIOS type 0 firmware version by VPD variable
by Jingle Hsu (Code Review) 02 Jun '20

02 Jun '20

Hello build bot (Jenkins), Jonathan Zhang, Johnny Lin, Morgan Jang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41720 to look at the new patch set (#11). Change subject: mb/ocp/deltalake: Update SMBIOS type 0 firmware version by VPD variable ...................................................................... mb/ocp/deltalake: Update SMBIOS type 0 firmware version by VPD variable Get firmware version from VPD version variable, and update firmware version to SMBIOS type 0. Tested on Tioga Pass / Delta Lake. Signed-off-by: Jingle Hsu <jingle_hsu(a)wiwynn.com> Change-Id: I98a8fe1135728f31ec154d6340d19be8d8f980ba --- M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/ocp/deltalake/board.fmd M src/mainboard/ocp/deltalake/ramstage.c 3 files changed, 22 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/41720/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/41720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98a8fe1135728f31ec154d6340d19be8d8f980ba Gerrit-Change-Number: 41720 Gerrit-PatchSet: 11 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [NOTFORMERGE] mb/facebook/fbg1701: Remove C_ENV_BOOTBLOCK_SIZE
by Kyösti Mälkki (Code Review) 02 Jun '20

02 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41694 ) Change subject: [NOTFORMERGE] mb/facebook/fbg1701: Remove C_ENV_BOOTBLOCK_SIZE ...................................................................... [NOTFORMERGE] mb/facebook/fbg1701: Remove C_ENV_BOOTBLOCK_SIZE Change-Id: I4254d681525327c7eec18832586818e9c4e8eb22 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M configs/config.facebook_fbg1701.mboot_vboot M src/mainboard/facebook/fbg1701/Kconfig M src/mainboard/facebook/fbg1701/board_verified_boot.c 3 files changed, 6 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/41694/1 diff --git a/configs/config.facebook_fbg1701.mboot_vboot b/configs/config.facebook_fbg1701.mboot_vboot index b372bbe..34d349a 100644 --- a/configs/config.facebook_fbg1701.mboot_vboot +++ b/configs/config.facebook_fbg1701.mboot_vboot @@ -1,5 +1,4 @@ CONFIG_VENDOR_FACEBOOK=y -CONFIG_C_ENV_BOOTBLOCK_SIZE=0x6000 CONFIG_ONBOARD_SAMSUNG_MEM=y CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFF8B000 CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index ca19e05..d04fb75 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -64,10 +64,6 @@ bool "TPM Setup in RAMSTAGE" default n -config C_ENV_BOOTBLOCK_SIZE - hex "C Bootblock Size" - default 0x4000 - config VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST bool default y diff --git a/src/mainboard/facebook/fbg1701/board_verified_boot.c b/src/mainboard/facebook/fbg1701/board_verified_boot.c index 57bd199..685818b 100644 --- a/src/mainboard/facebook/fbg1701/board_verified_boot.c +++ b/src/mainboard/facebook/fbg1701/board_verified_boot.c @@ -8,10 +8,13 @@ const verify_item_t bootblock_verify_list[] = { { VERIFY_FILE, ROMSTAGE, { { NULL, CBFS_TYPE_STAGE } }, HASH_IDX_ROM_STAGE, MBOOT_PCR_INDEX_0 }, +#if 0 +/* TODO: Is it possible to remove C_ENV_BOOTBLOCK_SIZE here? */ { VERIFY_BLOCK, "BootBlock", { { (void *)0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, CONFIG_C_ENV_BOOTBLOCK_SIZE, } }, HASH_IDX_BOOTBLOCK, MBOOT_PCR_INDEX_0 }, +#endif #if CONFIG(VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST) { VERIFY_BLOCK, "PublicKey", { { (void *)CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_LOCATION, @@ -34,10 +37,13 @@ MBOOT_PCR_INDEX_1 }, { VERIFY_FILE, "spd.bin", { { NULL, CBFS_TYPE_SPD } }, HASH_IDX_SPD0, MBOOT_PCR_INDEX_1 }, +#if 0 +/* TODO: Is it possible to remove C_ENV_BOOTBLOCK_SIZE here? */ { VERIFY_BLOCK, "BootBlock", { { (void *)0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, CONFIG_C_ENV_BOOTBLOCK_SIZE, } }, HASH_IDX_BOOTBLOCK, MBOOT_PCR_INDEX_0 }, +#endif #if CONFIG(VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST) { VERIFY_BLOCK, "PublicKey", { { (void *)CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_LOCATION, -- To view, visit https://review.coreboot.org/c/coreboot/+/41694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4254d681525327c7eec18832586818e9c4e8eb22 Gerrit-Change-Number: 41694 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: commonlib: Add CBFS_TYPE_BOOTBLOCK
by Wim Vervoorn (Code Review) 02 Jun '20

02 Jun '20

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41824 ) Change subject: commonlib: Add CBFS_TYPE_BOOTBLOCK ...................................................................... commonlib: Add CBFS_TYPE_BOOTBLOCK Add CBFS_TYPE_BOOTBLOCK to allow accessing the bootblock as a CBFS file. BUG=N/A TEST=build Change-Id: Ibb03ac3a6cd8711e0402e47335bb8e110c6ef61a Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/41824/1 diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h index d2fc626..af4baf5 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h @@ -21,6 +21,7 @@ #define CBFS_TYPE_DELETED 0x00000000 #define CBFS_TYPE_DELETED2 0xffffffff +#define CBFS_TYPE_BOOTBLOCK 0x01 #define CBFS_TYPE_STAGE 0x10 #define CBFS_TYPE_SELF 0x20 #define CBFS_TYPE_FIT 0x21 -- To view, visit https://review.coreboot.org/c/coreboot/+/41824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb03ac3a6cd8711e0402e47335bb8e110c6ef61a Gerrit-Change-Number: 41824 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/sconfig: Refactor and fix add_register()
by Nico Huber (Code Review) 02 Jun '20

02 Jun '20

Hello Furquan Shaikh, Patrick Georgi, Angel Pons, Arthur Heymans, Kyösti Mälkki, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41743 to review the following change. Change subject: util/sconfig: Refactor and fix add_register() ...................................................................... util/sconfig: Refactor and fix add_register() add_register() contained a duplicate check but only compared the new key to the first (smallest in order) list member. Fix that and factor the list handling out so it can be used by other functions. Change-Id: I5a8346f36fa024351e1282c9681868ecf451b283 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/sconfig/main.c 1 file changed, 19 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/41743/1 diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 6676bae..3e3bd17 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -528,33 +528,34 @@ new_resource(bus->dev, type, index, base); } -void add_register(struct chip_instance *chip_instance, char *name, char *val) +static void add_reg(struct reg **const head, char *const name, char *const val) { - struct reg *r = S_ALLOC(sizeof(struct reg)); + struct reg *const r = S_ALLOC(sizeof(struct reg)); + struct reg *prev = NULL; + struct reg *cur; r->key = name; r->value = val; - if (chip_instance->reg) { - struct reg *head = chip_instance->reg; - // sorting to be equal to sconfig's behaviour - int sort = strcmp(r->key, head->key); + + for (cur = *head; cur != NULL; prev = cur, cur = cur->next) { + const int sort = strcmp(r->key, cur->key); if (sort == 0) { printf("ERROR: duplicate 'register' key.\n"); exit(1); } - if (sort < 0) { - r->next = head; - chip_instance->reg = r; - } else { - while ((head->next) - && (strcmp(head->next->key, r->key) < 0)) - head = head->next; - r->next = head->next; - head->next = r; - } - } else { - chip_instance->reg = r; + if (sort < 0) + break; } + r->next = cur; + if (prev) + prev->next = r; + else + *head = r; +} + +void add_register(struct chip_instance *chip_instance, char *name, char *val) +{ + add_reg(&chip_instance->reg, name, val); } void add_slot_desc(struct bus *bus, char *type, char *length, char *designation, -- To view, visit https://review.coreboot.org/c/coreboot/+/41743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a8346f36fa024351e1282c9681868ecf451b283 Gerrit-Change-Number: 41743 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/denverton_ns: Fix 16-bit read/write PCI_COMMAND register
by HAOUAS Elyes (Code Review) 02 Jun '20

02 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40842 ) Change subject: soc/intel/denverton_ns: Fix 16-bit read/write PCI_COMMAND register ...................................................................... soc/intel/denverton_ns: Fix 16-bit read/write PCI_COMMAND register Change-Id: I23ca0c50b0b3c71710173b84d98c2e170ed3e45b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/smihandler.c 2 files changed, 8 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/40842/1 diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index b1f045a..7abf68c 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -515,24 +515,22 @@ void southcluster_enable_dev(struct device *dev) { - u32 reg32; + u16 reg16; if (!dev->enabled) { printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); + reg16 = pci_read_config16(dev, PCI_COMMAND); reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Hide this device if possible */ pch_hide_devfn(dev->path.pci.devfn); } else { /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } } diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 276ab09..a3a53d2 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -50,7 +50,7 @@ for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u32 reg32; + u16 reg16; pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); @@ -60,9 +60,9 @@ continue; /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16); /* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); -- To view, visit https://review.coreboot.org/c/coreboot/+/40842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23ca0c50b0b3c71710173b84d98c2e170ed3e45b Gerrit-Change-Number: 40842 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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