coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

1 participants
2826 discussions

Change in coreboot[master]: [WIP] mb/asrock/h110m: Select MAINBOARD_HAS_LPC_TPM
by Kyösti Mälkki (Code Review) 02 Jun '20

02 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41714 ) Change subject: [WIP] mb/asrock/h110m: Select MAINBOARD_HAS_LPC_TPM ...................................................................... [WIP] mb/asrock/h110m: Select MAINBOARD_HAS_LPC_TPM Change-Id: I6d6a24cb66a104c549790f039049a17ecbef208f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/asrock/h110m/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/41714/1 diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index eebce57..425aff4 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -16,6 +16,7 @@ select SUPERIO_NUVOTON_NCT6791D_COM_A select REALTEK_8168_RESET select RT8168_SET_LED_MODE + select MAINBOARD_HAS_LPC_TPM config IRQ_SLOT_COUNT int -- To view, visit https://review.coreboot.org/c/coreboot/+/41714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d6a24cb66a104c549790f039049a17ecbef208f Gerrit-Change-Number: 41714 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: soc/intel/jasperlake: Apply FiVR related settings
by build bot (Jenkins) (Code Review) 02 Jun '20

02 Jun '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41062 ) Change subject: soc/intel/jasperlake: Apply FiVR related settings ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/41062/11/src/soc/intel/jasperlake/… File src/soc/intel/jasperlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/41062/11/src/soc/intel/jasperlake/… PS11, Line 182: /* Retention Mode Voltage to Low Current Mode Voltage trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/41062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief81fe481c94abef9754881cf1f454699fafa52e Gerrit-Change-Number: 41062 Gerrit-PatchSet: 11 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Jun 2020 11:57:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/jasperlake: Apply FiVR related settings
by Meera Ravindranath (Code Review) 02 Jun '20

02 Jun '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Maulik V Vaghela, Aamir Bohra, Ronak Kanabar, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41062 to look at the new patch set (#11). Change subject: soc/intel/jasperlake: Apply FiVR related settings ...................................................................... soc/intel/jasperlake: Apply FiVR related settings Set optimized values for FiVR to shut the VCCIN_AUX_SHUTDOWN power rails during SOix. BUG=None BRANCH=None TEST=Build and boot dedede and check VCCIN_AUX_SHUTDOWN rails are shut. Change-Id: Ief81fe481c94abef9754881cf1f454699fafa52e Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/41062/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/41062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief81fe481c94abef9754881cf1f454699fafa52e Gerrit-Change-Number: 41062 Gerrit-PatchSet: 11 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/jasperlake: Apply FiVR related settings
by build bot (Jenkins) (Code Review) 02 Jun '20

02 Jun '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41062 ) Change subject: soc/intel/jasperlake: Apply FiVR related settings ...................................................................... Patch Set 10: (3 comments) https://review.coreboot.org/c/coreboot/+/41062/10/src/soc/intel/jasperlake/… File src/soc/intel/jasperlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/41062/10/src/soc/intel/jasperlake/… PS10, Line 182: /* Retention Mode Voltage to Low Current Mode Voltage transition time in 1us resolution - 44 us */ line over 96 characters https://review.coreboot.org/c/coreboot/+/41062/10/src/soc/intel/jasperlake/… PS10, Line 184: /* Retention Mode Voltage to High Current Mode Voltage transition time in 1us resolution - 54 us */ line over 96 characters https://review.coreboot.org/c/coreboot/+/41062/10/src/soc/intel/jasperlake/… PS10, Line 186: /* Low Current Mode Voltage to High Current Mode Voltage transition time in 1us resolution - 13 us */ line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/41062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief81fe481c94abef9754881cf1f454699fafa52e Gerrit-Change-Number: 41062 Gerrit-PatchSet: 10 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Jun 2020 11:52:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/jasperlake: Apply FiVR related settings
by Meera Ravindranath (Code Review) 02 Jun '20

02 Jun '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Maulik V Vaghela, Aamir Bohra, Ronak Kanabar, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41062 to look at the new patch set (#10). Change subject: soc/intel/jasperlake: Apply FiVR related settings ...................................................................... soc/intel/jasperlake: Apply FiVR related settings Set optimized values for FiVR to shut the VCCIN_AUX_SHUTDOWN power rails during SOix. BUG=None BRANCH=None TEST=Build and boot dedede and check VCCIN_AUX_SHUTDOWN rails are shut. Change-Id: Ief81fe481c94abef9754881cf1f454699fafa52e Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/41062/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/41062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief81fe481c94abef9754881cf1f454699fafa52e Gerrit-Change-Number: 41062 Gerrit-PatchSet: 10 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/purism/librem_skl: drop EC chip driver
by Matt DeVillier (Code Review) 02 Jun '20

02 Jun '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41788 ) Change subject: mb/purism/librem_skl: drop EC chip driver ...................................................................... mb/purism/librem_skl: drop EC chip driver CB:35086 exposed that the devicetree listed an EC chip for which there is no actual driver; the EC is entirely ACPI code (.asl) included by the board's ec.asl. Remove the unnecessary EC chip driver. Test: build/boot Librem 13v4, verify battery info etc still correct. Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Change-Id: I5cb0b51881ab8f14e9ec693485f673f4284b5f14 --- M src/mainboard/purism/librem_skl/devicetree.cb 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/41788/1 diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index a439e02..d44d2ad 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -208,9 +208,6 @@ device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1f.0 on - chip ec/purism/librem - device pnp 0c09.0 on end - end chip drivers/pc80/tpm device pnp 0c31.0 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/41788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cb0b51881ab8f14e9ec693485f673f4284b5f14 Gerrit-Change-Number: 41788 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: src: Remove redundant includes
by HAOUAS Elyes (Code Review) 02 Jun '20

02 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41817 ) Change subject: src: Remove redundant includes ...................................................................... src: Remove redundant includes <types.h> is supposed to provide <commonlib/bsd/cb_err.h>, <stdbool.h>,<stdint.h> and <stddef.h>. So remove those includes each time when <types.h> is included. Change-Id: I886f02255099f3005852a2e6095b21ca86a940ed Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/armv7/exception.c M src/arch/arm64/armv8/exception.c M src/device/pci_device.c M src/drivers/i2c/tpm/tpm.c M src/drivers/intel/fsp2_0/include/fsp/info_header.h M src/drivers/tpm/tpm.c M src/drivers/uart/pl011.h M src/ec/google/wilco/commands.h M src/ec/google/wilco/mailbox.c M src/include/device/dram/ddr3.h M src/include/device/dram/ddr4.h M src/include/lib.h M src/mainboard/supermicro/x10slm-f/mainboard.c M src/northbridge/intel/x4x/dq_dqs.c M src/security/tpm/tss.h M src/security/tpm/tss/tcg-2.0/tss_structures.h M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/common/block/include/amdblocks/lpc.h M src/soc/amd/common/block/lpc/espi_util.c M src/soc/cavium/cn81xx/include/soc/soc.h M src/soc/cavium/cn81xx/include/soc/timer.h M src/soc/cavium/cn81xx/include/soc/uart.h M src/soc/intel/apollolake/graphics.c M src/soc/intel/common/block/include/intelblocks/cse.h M src/soc/mediatek/mt8173/flash_controller.c M src/soc/mediatek/mt8173/include/soc/dramc_register.h M src/soc/mediatek/mt8173/include/soc/emi.h M src/soc/mediatek/mt8183/include/soc/emi.h M src/soc/mediatek/mt8183/include/soc/spm.h M src/soc/nvidia/tegra/dc.h M src/soc/nvidia/tegra124/spi.c M src/soc/nvidia/tegra210/include/soc/dma.h M src/soc/nvidia/tegra210/spi.c 33 files changed, 2 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/41817/1 diff --git a/src/arch/arm/armv7/exception.c b/src/arch/arm/armv7/exception.c index 39ef16d..799ae02 100644 --- a/src/arch/arm/armv7/exception.c +++ b/src/arch/arm/armv7/exception.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -#include <stdint.h> #include <types.h> #include <arch/cache.h> #include <arch/exception.h> diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c index db399fe..88e68e7 100644 --- a/src/arch/arm64/armv8/exception.c +++ b/src/arch/arm64/armv8/exception.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -#include <stdint.h> #include <types.h> #include <arch/barrier.h> #include <arch/exception.h> diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 5f50a31..d9f65e6 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -11,7 +11,6 @@ #include <console/console.h> #include <cpu/cpu.h> #include <stdlib.h> -#include <stdint.h> #include <string.h> #include <delay.h> #include <device/cardbus.h> diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c index 41d4577..78ac224 100644 --- a/src/drivers/i2c/tpm/tpm.c +++ b/src/drivers/i2c/tpm/tpm.c @@ -17,7 +17,6 @@ #include <commonlib/endian.h> -#include <stdint.h> #include <string.h> #include <types.h> #include <delay.h> diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index f6f66ce..7755d2a 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -3,7 +3,6 @@ #ifndef _FSP2_0_INFO_HEADER_H_ #define _FSP2_0_INFO_HEADER_H_ -#include <stdint.h> #include <types.h> #define FSP_HDR_OFFSET 0x94 diff --git a/src/drivers/tpm/tpm.c b/src/drivers/tpm/tpm.c index ad4a54c..d3485bb 100644 --- a/src/drivers/tpm/tpm.c +++ b/src/drivers/tpm/tpm.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <types.h> -#include <stddef.h> #include <bootstate.h> #include <security/tpm/tspi.h> diff --git a/src/drivers/uart/pl011.h b/src/drivers/uart/pl011.h index 7b573a4..d4d54c4 100644 --- a/src/drivers/uart/pl011.h +++ b/src/drivers/uart/pl011.h @@ -7,7 +7,6 @@ #ifndef __DRIVERS_UART_PL011_H #define __DRIVERS_UART_PL011_H -#include <stdint.h> #include <types.h> /* PL011 r1p5 registers */ diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h index 912e88a..a216345 100644 --- a/src/ec/google/wilco/commands.h +++ b/src/ec/google/wilco/commands.h @@ -3,7 +3,6 @@ #ifndef EC_GOOGLE_WILCO_COMMANDS_H #define EC_GOOGLE_WILCO_COMMANDS_H -#include <stdint.h> #include <types.h> enum { diff --git a/src/ec/google/wilco/mailbox.c b/src/ec/google/wilco/mailbox.c index c592d81..f7aac86 100644 --- a/src/ec/google/wilco/mailbox.c +++ b/src/ec/google/wilco/mailbox.c @@ -4,7 +4,6 @@ #include <console/console.h> #include <delay.h> #include <ec/google/common/mec.h> -#include <stdint.h> #include <string.h> #include <timer.h> #include <types.h> diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 08b7b7c..a209e48 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -15,7 +15,6 @@ * \brief Utilities for decoding DDR3 SPDs */ -#include <stdint.h> #include <spd.h> #include <device/dram/common.h> #include <types.h> diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h index 51fd7bf..f258fa9 100644 --- a/src/include/device/dram/ddr4.h +++ b/src/include/device/dram/ddr4.h @@ -14,7 +14,6 @@ * \brief Utilities for decoding DDR4 SPDs */ -#include <stdint.h> #include <spd.h> #include <device/dram/common.h> #include <types.h> diff --git a/src/include/lib.h b/src/include/lib.h index d7b6b14..0d6fdb1 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -4,7 +4,7 @@ #ifndef __LIB_H__ #define __LIB_H__ -#include <stdint.h> + #include <types.h> /* Defined in src/lib/lzma.c. Returns decompressed size or 0 on error. */ diff --git a/src/mainboard/supermicro/x10slm-f/mainboard.c b/src/mainboard/supermicro/x10slm-f/mainboard.c index 7d840f5..2f20606 100644 --- a/src/mainboard/supermicro/x10slm-f/mainboard.c +++ b/src/mainboard/supermicro/x10slm-f/mainboard.c @@ -3,7 +3,6 @@ #include <console/console.h> #include <device/device.h> #include <option.h> -#include <stdint.h> #include <types.h> /* diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index 7df2591..dda4174 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -3,7 +3,6 @@ #include <device/mmio.h> #include <console/console.h> #include <delay.h> -#include <stdint.h> #include <string.h> #include <types.h> #include "x4x.h" diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h index 57f3b24..f39b0f5 100644 --- a/src/security/tpm/tss.h +++ b/src/security/tpm/tss.h @@ -13,7 +13,6 @@ #ifndef TSS_H_ #define TSS_H_ -#include <stdint.h> #include <types.h> #include <security/tpm/tss/common/tss_common.h> diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index 3f0c654..c267ec9 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -11,7 +11,6 @@ * This file includes a subset of definitions of TPM protocol version 2.x * constants and structures needed for functions used in coreboot. */ -#include <stdint.h> #include <types.h> #include "../common/tss_common.h" diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 0d41782..84a9360 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -4,7 +4,6 @@ #define __AMDBLOCKS_ACPIMMIO_H__ #include <device/mmio.h> -#include <stdint.h> #include <types.h> #include <amdblocks/acpimmio_map.h> diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 11acc78..7412e7b 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -4,7 +4,6 @@ #define __AMDBLOCKS_LPC_H__ #include <types.h> -#include <stdint.h> /* PCI registers for D14F3 */ #define LPC_PCI_CONTROL 0x40 diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 5ca0d28..3750a8b 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -7,8 +7,6 @@ #include <console/console.h> #include <espi.h> #include <soc/pci_devs.h> -#include <stddef.h> -#include <stdint.h> #include <timer.h> #include <types.h> diff --git a/src/soc/cavium/cn81xx/include/soc/soc.h b/src/soc/cavium/cn81xx/include/soc/soc.h index 3939517..78343fd 100644 --- a/src/soc/cavium/cn81xx/include/soc/soc.h +++ b/src/soc/cavium/cn81xx/include/soc/soc.h @@ -3,7 +3,6 @@ #ifndef __SOC_CAVIUM_CN81XX_INCLUDE_SOC_SOC_H #define __SOC_CAVIUM_CN81XX_INCLUDE_SOC_SOC_H -#include <stdint.h> #include <types.h> /* MIO BOOT Registers */ diff --git a/src/soc/cavium/cn81xx/include/soc/timer.h b/src/soc/cavium/cn81xx/include/soc/timer.h index 99dbb6a..d722569 100644 --- a/src/soc/cavium/cn81xx/include/soc/timer.h +++ b/src/soc/cavium/cn81xx/include/soc/timer.h @@ -3,7 +3,6 @@ #ifndef __SOC_CAVIUM_CN81XX_TIMER_H__ #define __SOC_CAVIUM_CN81XX_TIMER_H__ -#include <stdint.h> #include <types.h> /* Watchdog functions */ diff --git a/src/soc/cavium/cn81xx/include/soc/uart.h b/src/soc/cavium/cn81xx/include/soc/uart.h index db1a51e..afafd0e 100644 --- a/src/soc/cavium/cn81xx/include/soc/uart.h +++ b/src/soc/cavium/cn81xx/include/soc/uart.h @@ -3,7 +3,6 @@ #ifndef __SOC_CAVIUM_COMMON_INCLUDE_SOC_UART_H #define __SOC_CAVIUM_COMMON_INCLUDE_SOC_UART_H -#include <stdint.h> #include <types.h> int uart_is_enabled(const size_t bus); diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index a5e361e..2fc0376 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <stdint.h> #include <acpi/acpi.h> #include <bootmode.h> #include <console/console.h> diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 9f85730..a1dc3d9 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -3,7 +3,6 @@ #ifndef SOC_INTEL_COMMON_CSE_H #define SOC_INTEL_COMMON_CSE_H -#include <stdint.h> #include <types.h> /* MKHI Command groups */ diff --git a/src/soc/mediatek/mt8173/flash_controller.c b/src/soc/mediatek/mt8173/flash_controller.c index c1f2dae..64eff2e 100644 --- a/src/soc/mediatek/mt8173/flash_controller.c +++ b/src/soc/mediatek/mt8173/flash_controller.c @@ -7,7 +7,6 @@ #include <console/console.h> #include <spi_flash.h> #include <spi-generic.h> -#include <stdint.h> #include <string.h> #include <symbols.h> #include <timer.h> diff --git a/src/soc/mediatek/mt8173/include/soc/dramc_register.h b/src/soc/mediatek/mt8173/include/soc/dramc_register.h index 5841b24..cabc1dc 100644 --- a/src/soc/mediatek/mt8173/include/soc/dramc_register.h +++ b/src/soc/mediatek/mt8173/include/soc/dramc_register.h @@ -3,7 +3,6 @@ #ifndef _DRAMC_REGISTER_H_ #define _DRAMC_REGISTER_H_ -#include <stddef.h> #include <types.h> #define DRIVING_DS2_0 7 /* DS[2:0] 7->6 */ diff --git a/src/soc/mediatek/mt8173/include/soc/emi.h b/src/soc/mediatek/mt8173/include/soc/emi.h index 8f12ee3..1cc2577 100644 --- a/src/soc/mediatek/mt8173/include/soc/emi.h +++ b/src/soc/mediatek/mt8173/include/soc/emi.h @@ -4,7 +4,6 @@ #define SOC_MEDIATEK_MT8173_EMI_H #include <soc/dramc_common.h> -#include <stdint.h> #include <types.h> /* DDR type */ diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index e775973..b2d78b9 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -3,7 +3,6 @@ #ifndef SOC_MEDIATEK_MT8183_EMI_H #define SOC_MEDIATEK_MT8183_EMI_H -#include <stdint.h> #include <types.h> #include <soc/dramc_common_mt8183.h> diff --git a/src/soc/mediatek/mt8183/include/soc/spm.h b/src/soc/mediatek/mt8183/include/soc/spm.h index e09d451..fa6d6d0 100644 --- a/src/soc/mediatek/mt8183/include/soc/spm.h +++ b/src/soc/mediatek/mt8183/include/soc/spm.h @@ -4,7 +4,6 @@ #define SOC_MEDIATEK_MT8183_SPM_H #include <soc/addressmap.h> -#include <stdint.h> #include <types.h> /* SPM READ/WRITE CFG */ diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index f0f5b11..27bbee8 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -2,8 +2,8 @@ #ifndef __SOC_NVIDIA_TEGRA_DC_H #define __SOC_NVIDIA_TEGRA_DC_H + #include <device/device.h> -#include <stddef.h> #include <types.h> /* Register definitions for the Tegra display controller */ diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 6a25721..adf0248 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -7,7 +7,6 @@ #include <boot_device.h> #include <console/console.h> #include <delay.h> -#include <stdint.h> #include <soc/addressmap.h> #include <soc/dma.h> #include <soc/spi.h> diff --git a/src/soc/nvidia/tegra210/include/soc/dma.h b/src/soc/nvidia/tegra210/include/soc/dma.h index 3add2ba..b06cec6 100644 --- a/src/soc/nvidia/tegra210/include/soc/dma.h +++ b/src/soc/nvidia/tegra210/include/soc/dma.h @@ -3,7 +3,6 @@ #ifndef __NVIDIA_TEGRA210_DMA_H__ #define __NVIDIA_TEGRA210_DMA_H__ -#include <stdint.h> #include <soc/addressmap.h> #include <types.h> diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index eae8f39..8fde9c2 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -7,7 +7,6 @@ #include <boot_device.h> #include <console/console.h> #include <delay.h> -#include <stdint.h> #include <spi-generic.h> #include <spi_flash.h> #include <soc/addressmap.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/41817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I886f02255099f3005852a2e6095b21ca86a940ed Gerrit-Change-Number: 41817 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: mb/lenovo/x230: Add support for ThinkLight
by Stefan Ott (Code Review) 02 Jun '20

02 Jun '20

Stefan Ott has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40669 ) Change subject: mb/lenovo/x230: Add support for ThinkLight ...................................................................... mb/lenovo/x230: Add support for ThinkLight With this patch, the ThinkLight on the ThinkPad X230 can be controlled through the OS. This was initially done for the X201 in f63fbdb6: mb/lenovo/x201: Add support for ThinkLight. After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight Unfortunately I do not own an X230 to test this. Change-Id: Idd93b26f52eccb8fc79888f1e45117f26d694291 Signed-off-by: Stefan Ott <stefan(a)ott.net> --- M src/mainboard/lenovo/x230/dsdt.asl 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/40669/1 diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl index a03b252..c04195a 100644 --- a/src/mainboard/lenovo/x230/dsdt.asl +++ b/src/mainboard/lenovo/x230/dsdt.asl @@ -37,4 +37,5 @@ } #include <southbridge/intel/common/acpi/sleepstates.asl> + #include <ec/lenovo/h8/acpi/lightlight.asl> } -- To view, visit https://review.coreboot.org/c/coreboot/+/40669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd93b26f52eccb8fc79888f1e45117f26d694291 Gerrit-Change-Number: 40669 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Ott <coreboot(a)desire.ch> Gerrit-MessageType: newchange

6 11

Change in coreboot[master]: sb/intel/i82371eb: Fix 16-bit read/write PCI_COMMAND register
by HAOUAS Elyes (Code Review) 02 Jun '20

02 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40809 ) Change subject: sb/intel/i82371eb: Fix 16-bit read/write PCI_COMMAND register ...................................................................... sb/intel/i82371eb: Fix 16-bit read/write PCI_COMMAND register Change-Id: Icecda127a7229c1410c73a6fdd0898430f7eceb2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82371eb/isa.c 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/40809/1 diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index bb87611..f7c38fe 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -40,9 +40,7 @@ /* * Enable special cycles, needed for soft poweroff. */ - reg32 = pci_read_config16(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SPECIAL; - pci_write_config16(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SPECIAL); /* * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO) -- To view, visit https://review.coreboot.org/c/coreboot/+/40809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icecda127a7229c1410c73a6fdd0898430f7eceb2 Gerrit-Change-Number: 40809 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: usb/xhci: Fix timeout logic
by Caveh Jalali (Code Review) 02 Jun '20

02 Jun '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41854 ) Change subject: usb/xhci: Fix timeout logic ...................................................................... Patch Set 2: > Patch Set 2: > > Was there a bug for this? not really, this is something i noticed by inspection while investigating b/157721366. -- To view, visit https://review.coreboot.org/c/coreboot/+/41854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81a888aa0a1544e55e6a680be8f3b7f6e0d87812 Gerrit-Change-Number: 41854 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Jun 2020 11:24:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2020