coreboot-gerrit June 2020

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Change in coreboot[master]: sb/intel/lynxpoint: Restore lost PCI_COMMAND_MASTER bits
by Angel Pons (Code Review) 01 Jun '20

01 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41945 ) Change subject: sb/intel/lynxpoint: Restore lost PCI_COMMAND_MASTER bits ...................................................................... sb/intel/lynxpoint: Restore lost PCI_COMMAND_MASTER bits Commit 73ae076 "fixed" accesses to the PCI command register that were not 16 bits, but also lost some bits to be written in the process. Change-Id: I4eb62a0433a4563827a69c9e39c17ddd2eb8cd23 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/early_usb.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/serialio.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/41945/1 diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c index 86abbe0..313d0c2 100644 --- a/src/southbridge/intel/lynxpoint/early_usb.c +++ b/src/southbridge/intel/lynxpoint/early_usb.c @@ -24,7 +24,7 @@ static void enable_usb_bar_on_device(pci_devfn_t dev, u32 bar) { pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar); - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } void enable_usb_bar(void) diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 79d47da..ebe0aa9 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -730,7 +730,7 @@ mei_base_address = (u32 *)(uintptr_t)res->base; /* Ensure Memory and Bus Master bits are set */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* Clean up status for next message */ read_host_csr(&host); diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index accc51b..a75cea0 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -137,7 +137,7 @@ printk(BIOS_DEBUG, "Initializing Serial IO device\n"); /* Ensure memory and bus master are enabled */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* Find BAR0 and BAR1 */ bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); -- To view, visit https://review.coreboot.org/c/coreboot/+/41945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4eb62a0433a4563827a69c9e39c17ddd2eb8cd23 Gerrit-Change-Number: 41945 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: src: Fix up ##-commented SPDX comments
by Angel Pons (Code Review) 01 Jun '20

01 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41833 ) Change subject: src: Fix up ##-commented SPDX comments ...................................................................... src: Fix up ##-commented SPDX comments Delete trailing empty comment lines. Change-Id: If1c5f568af3290c329d22dfc054d10d01c079065 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/cmos.layout M src/vendorcode/cavium/Kconfig M src/vendorcode/cavium/Makefile.inc M src/vendorcode/eltan/security/Kconfig M src/vendorcode/eltan/security/Makefile.inc M src/vendorcode/eltan/security/mboot/Kconfig M src/vendorcode/eltan/security/mboot/Makefile.inc M src/vendorcode/eltan/security/verified_boot/Kconfig M src/vendorcode/eltan/security/verified_boot/Makefile.inc M src/vendorcode/google/Kconfig M src/vendorcode/google/Makefile.inc M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/Makefile.inc M src/vendorcode/intel/Kconfig M src/vendorcode/intel/Makefile.inc M src/vendorcode/siemens/Kconfig M src/vendorcode/siemens/Makefile.inc M src/vendorcode/siemens/hwilib/Makefile.inc 18 files changed, 0 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/41833/1 diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout index 5b9157c..b104a96 100644 --- a/src/mainboard/asrock/b85m_pro4/cmos.layout +++ b/src/mainboard/asrock/b85m_pro4/cmos.layout @@ -1,5 +1,3 @@ -## -## ## Copyright (C) 2007-2008 coresystems GmbH ## Copyright (C) 2014 Vladimir Serbinenko ## diff --git a/src/vendorcode/cavium/Kconfig b/src/vendorcode/cavium/Kconfig index ca32157..15b9ef5 100644 --- a/src/vendorcode/cavium/Kconfig +++ b/src/vendorcode/cavium/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only config CAVIUM_BDK diff --git a/src/vendorcode/cavium/Makefile.inc b/src/vendorcode/cavium/Makefile.inc index cfe4c25..bf2fe04 100644 --- a/src/vendorcode/cavium/Makefile.inc +++ b/src/vendorcode/cavium/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_CAVIUM_BDK),y) diff --git a/src/vendorcode/eltan/security/Kconfig b/src/vendorcode/eltan/security/Kconfig index 45a6fba..0d8d04c 100644 --- a/src/vendorcode/eltan/security/Kconfig +++ b/src/vendorcode/eltan/security/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only config USE_VENDORCODE_ELTAN diff --git a/src/vendorcode/eltan/security/Makefile.inc b/src/vendorcode/eltan/security/Makefile.inc index d9c40ef..7db68c8 100644 --- a/src/vendorcode/eltan/security/Makefile.inc +++ b/src/vendorcode/eltan/security/Makefile.inc @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only subdirs-y += verified_boot diff --git a/src/vendorcode/eltan/security/mboot/Kconfig b/src/vendorcode/eltan/security/mboot/Kconfig index 9563ae0..91898fc 100644 --- a/src/vendorcode/eltan/security/mboot/Kconfig +++ b/src/vendorcode/eltan/security/mboot/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only menu "Measured Boot (mboot)" diff --git a/src/vendorcode/eltan/security/mboot/Makefile.inc b/src/vendorcode/eltan/security/mboot/Makefile.inc index b8c6020..22729af 100644 --- a/src/vendorcode/eltan/security/mboot/Makefile.inc +++ b/src/vendorcode/eltan/security/mboot/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBOOT)),) diff --git a/src/vendorcode/eltan/security/verified_boot/Kconfig b/src/vendorcode/eltan/security/verified_boot/Kconfig index 2c29107..11574dd 100644 --- a/src/vendorcode/eltan/security/verified_boot/Kconfig +++ b/src/vendorcode/eltan/security/verified_boot/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only menu "Verified Boot (verified_boot)" diff --git a/src/vendorcode/eltan/security/verified_boot/Makefile.inc b/src/vendorcode/eltan/security/verified_boot/Makefile.inc index 3ed4da3..9158760 100644 --- a/src/vendorcode/eltan/security/verified_boot/Makefile.inc +++ b/src/vendorcode/eltan/security/verified_boot/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBOOT)),) diff --git a/src/vendorcode/google/Kconfig b/src/vendorcode/google/Kconfig index be1f32c..60c0c22 100644 --- a/src/vendorcode/google/Kconfig +++ b/src/vendorcode/google/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only source "src/vendorcode/google/chromeos/Kconfig" diff --git a/src/vendorcode/google/Makefile.inc b/src/vendorcode/google/Makefile.inc index 1e0164b..c67ea20 100644 --- a/src/vendorcode/google/Makefile.inc +++ b/src/vendorcode/google/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only subdirs-$(CONFIG_CHROMEOS) += chromeos diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 8621e66..f48069f 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only config MAINBOARD_HAS_CHROMEOS diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index fc00374..a25700f 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_ELOG) += elog.c diff --git a/src/vendorcode/intel/Kconfig b/src/vendorcode/intel/Kconfig index a0f9b7a..8612eba 100644 --- a/src/vendorcode/intel/Kconfig +++ b/src/vendorcode/intel/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only config UEFI_2_4_BINDING diff --git a/src/vendorcode/intel/Makefile.inc b/src/vendorcode/intel/Makefile.inc index 41c1882..d08ae2a 100644 --- a/src/vendorcode/intel/Makefile.inc +++ b/src/vendorcode/intel/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_UEFI_2_4_BINDING),y) diff --git a/src/vendorcode/siemens/Kconfig b/src/vendorcode/siemens/Kconfig index f1df819..d7c16ff 100644 --- a/src/vendorcode/siemens/Kconfig +++ b/src/vendorcode/siemens/Kconfig @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only config USE_SIEMENS_HWILIB diff --git a/src/vendorcode/siemens/Makefile.inc b/src/vendorcode/siemens/Makefile.inc index 40623dc..88fd1c3 100644 --- a/src/vendorcode/siemens/Makefile.inc +++ b/src/vendorcode/siemens/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only subdirs-$(CONFIG_USE_SIEMENS_HWILIB) += hwilib diff --git a/src/vendorcode/siemens/hwilib/Makefile.inc b/src/vendorcode/siemens/hwilib/Makefile.inc index b4152c1..2456db2 100644 --- a/src/vendorcode/siemens/hwilib/Makefile.inc +++ b/src/vendorcode/siemens/hwilib/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only CFLAGS_x86_32 += -Isrc/vendorcode/siemens/hwilib -- To view, visit https://review.coreboot.org/c/coreboot/+/41833 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1c5f568af3290c329d22dfc054d10d01c079065 Gerrit-Change-Number: 41833 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: drivers/intel/mipi_camera: camera SSDT generation
by Tim Wawrzynczak (Code Review) 01 Jun '20

01 Jun '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41607 ) Change subject: drivers/intel/mipi_camera: camera SSDT generation ...................................................................... Patch Set 10: (5 comments) https://review.coreboot.org/c/coreboot/+/41607/6/src/drivers/intel/mipi_cam… File src/drivers/intel/mipi_camera/camera.c: https://review.coreboot.org/c/coreboot/+/41607/6/src/drivers/intel/mipi_cam… PS6, Line 159: config->ssdb.platform = 9; : if (!config->ssdb.flash_support) : config->ssdb.flash_support = 2; : if (!config->ssdb.privacy_led) : config->ssdb.privacy_led = 1; : if (!config->ssdb.mipi_define) : config->ssdb.mipi_define = 1; : if (!config->ssdb.mclk_speed) : config->ssdb.mclk_speed = 19200000; > Some of these values can be found in Intel's "SkyCam" camera driver SDK (example files Skycam/public […] Thanks Matt, Sugnan could you add those in? https://review.coreboot.org/c/coreboot/+/41607/6/src/drivers/intel/mipi_cam… PS6, Line 188: /* Method (_DSM, 4, NotSerialized) */ : acpigen_write_method("_DSM", 0x4); : : /* ToBuffer (Arg0, Local0) */ : acpigen_write_to_buffer(ARG0_OP, LOCAL0_OP); : : /* If (LEqual (Local0, ToUUID(uuid))) */ : acpigen_write_if(); : acpigen_emit_byte(LEQUAL_OP); : acpigen_emit_byte(LOCAL0_OP); : acpigen_write_uuid("822ace8f-2814-4174-a56b-5f029fe079ee"); : acpigen_write_return_string(config->sensor_name ? config->sensor_name : "UNKNOWN"); : acpigen_pop_len(); /* If */ : : /* If (LEqual (Local0, ToUUID(uuid))) */ : acpigen_write_if(); : acpigen_emit_byte(LEQUAL_OP); : acpigen_emit_byte(LOCAL0_OP); : acpigen_write_uuid("26257549-9271-4ca4-bb43-c4899d5a4881"); : /* ToInteger (Arg2, Local1) */ : acpigen_write_to_integer(ARG2_OP, LOCAL1_OP); : : /* If (LEqual (Local1, 1)) */ : acpigen_write_if_lequal_op_int(LOCAL1_OP, 1); : acpigen_write_return_integer((config->ssdb.vcm_type ? 1 : 0) + : (config->ssdb.rom_type ? 1 : 0) + 1); : acpigen_pop_len(); /* If Arg2=1 */ : : /* If (LEqual (Local1, 2)) */ : acpigen_write_if_lequal_op_int(LOCAL1_OP, 2); : acpigen_write_return_integer(((uint32_t)i2c_bus) << 24 | : ((uint32_t)i2c_addr) << 8 | 0x0); /* type 0 for sensor */ : acpigen_pop_len(); /* If Arg2=2 */ : : if (config->ssdb.vcm_type) { : /* If (LEqual (Local1, 3)) */ : acpigen_write_if_lequal_op_int(LOCAL1_OP, 3); : acpigen_write_return_integer(((uint32_t)i2c_bus) << 24 | /* type 1 for vcm */ : ((uint32_t)config->vcm_address) << 8 | 0x01); : acpigen_pop_len(); /* If Arg2=3 */ : } : if (config->ssdb.rom_type) { : /* If (LEqual (Local1, 3 or 4)) */ : acpigen_write_if_lequal_op_int(LOCAL1_OP, 3 + (config->ssdb.vcm_type ? 1 : 0)); : acpigen_write_return_integer(((uint32_t)i2c_bus) << 24 | /* type 2 for rom */ : ((uint32_t)config->rom_address) << 8 | 0x02); : acpigen_pop_len(); /* If Arg2=3 or 4 */ : } : : acpigen_pop_len(); /* If uuid */ : : /* Return (Buffer (One) { 0x0 }) */ : acpigen_write_return_singleton_buffer(0x0); : : acpigen_pop_len(); /* Method _DSM */ > I think _DSM is mostly used in Intel's design for Windows drivers. […] You should be able to use acpigen_write_dsm. It takes lists of corresponding UUIDs and callback functions to add what code to run for each `if (arg2 == uuid[0]), etc.` https://review.coreboot.org/c/coreboot/+/41607/6/src/drivers/intel/mipi_cam… PS6, Line 445: if (config->dep) { : acpigen_write_name("_DEP"); : acpigen_write_package(1); : acpigen_emit_namestring(config->dep); : acpigen_pop_len(); : } > To include a dependency similar to one in the following link. […] Is the kernel driver using _DEP for something unusual? _DEP is used to "designate device objects that OSPM should assign a higher priority in start ordering due to future operation region accesses." https://review.coreboot.org/c/coreboot/+/41607/6/src/drivers/intel/mipi_cam… File src/drivers/intel/mipi_camera/chip.h: https://review.coreboot.org/c/coreboot/+/41607/6/src/drivers/intel/mipi_cam… PS6, Line 79: uint8_t reserved[13]; > It pads SSDB out so the binary blob in ACPI is the same size as seen on other firmwares. […] Ack https://review.coreboot.org/c/coreboot/+/41607/6/src/drivers/intel/mipi_cam… PS6, Line 107: const char *pr0; : const char *pr3; /* _PR3 shouldn't be needed > Idea was to push @Matt patch mostly as it is and the incremental changes related to power resource i […] A later patch is OK with me. -- To view, visit https://review.coreboot.org/c/coreboot/+/41607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15979f345fb823df2560db269e902a1ea650b69e Gerrit-Change-Number: 41607 Gerrit-PatchSet: 10 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Comment-Date: Mon, 01 Jun 2020 17:46:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt Delco <delco(a)chromium.org> Comment-In-Reply-To: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: AGESA f14/f15tn/f16kb: Clean up buildOpts.c files
by Angel Pons (Code Review) 01 Jun '20

01 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41667 ) Change subject: AGESA f14/f15tn/f16kb: Clean up buildOpts.c files ...................................................................... AGESA f14/f15tn/f16kb: Clean up buildOpts.c files Until now, the buildOpts.c files were primarily made out of copy-pasted AGESA options, commented-out definitions and several useless comments; that is, the materialization of technical debt in GCC-parsable form... Until now. It is assumed that the boards in the tree still boot. So, by comparing their settings, we can extract saner defaults to place into AGESA. Many of the settings were common across all boards of the same family, so we promote those values to default settings. In some cases flipping a flag was required, so the macros to alter that option had to be adapted as well. Since those AGESA versions are expected to never receive updates, it should not be a problem to change their files to suit our needs. As a result, all but two buildOpts.c files now have less than 100 lines. AGESA f14 boards need less than 50 lines, and f15tn/f16kb just require about 60 or 70 lines in those files. Hopefully, this will make porting more mainboards using AGESA f14/f15tn/f16kb a substantially easier task. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Ife1ca5177d85441b9a7b24d64d7fcbabde6e0409 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/amd/inagua/buildOpts.c M src/mainboard/amd/olivehill/buildOpts.c M src/mainboard/amd/parmer/buildOpts.c M src/mainboard/amd/persimmon/buildOpts.c M src/mainboard/amd/south_station/buildOpts.c M src/mainboard/amd/thatcher/buildOpts.c M src/mainboard/amd/union_station/buildOpts.c M src/mainboard/asrock/e350m1/buildOpts.c M src/mainboard/asrock/imb-a180/buildOpts.c M src/mainboard/asus/am1i-a/buildOpts.c M src/mainboard/asus/f2a85-m/buildOpts.c M src/mainboard/bap/ode_e20XX/buildOpts.c M src/mainboard/biostar/a68n_5200/buildOpts.c M src/mainboard/biostar/am1ml/buildOpts.c M src/mainboard/elmex/pcm205400/buildOpts.c M src/mainboard/gizmosphere/gizmo/buildOpts.c M src/mainboard/gizmosphere/gizmo2/buildOpts.c M src/mainboard/hp/abm/buildOpts.c M src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c M src/mainboard/jetway/nf81-t56n-lf/buildOpts.c M src/mainboard/lenovo/g505s/buildOpts.c M src/mainboard/lippert/frontrunner-af/buildOpts.c M src/mainboard/lippert/toucan-af/buildOpts.c M src/mainboard/msi/ms7721/buildOpts.c M src/mainboard/pcengines/apu1/buildOpts.c M src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f15tn/Config/OptionFchInstall.h M src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h M src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h M src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h M src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h 33 files changed, 786 insertions(+), 5,000 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/41667/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/41667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife1ca5177d85441b9a7b24d64d7fcbabde6e0409 Gerrit-Change-Number: 41667 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: usb/xhci: Fix timeout logic
by Tim Wawrzynczak (Code Review) 01 Jun '20

01 Jun '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41854 ) Change subject: usb/xhci: Fix timeout logic ...................................................................... Patch Set 2: Was there a bug for this? -- To view, visit https://review.coreboot.org/c/coreboot/+/41854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81a888aa0a1544e55e6a680be8f3b7f6e0d87812 Gerrit-Change-Number: 41854 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 01 Jun 2020 17:33:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/asrock/e350m1/buildOpts.c: Fix AGESA_VERSION_STRING
by Angel Pons (Code Review) 01 Jun '20

01 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41621 ) Change subject: mb/asrock/e350m1/buildOpts.c: Fix AGESA_VERSION_STRING ...................................................................... mb/asrock/e350m1/buildOpts.c: Fix AGESA_VERSION_STRING This is the only board using AGESA f14 with a different version string. Change it so that it matches the other AGESA f14 boards in the tree. Change-Id: I384bd96db51457e68a320b99ecdbb2ada0dfbdd5 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/e350m1/buildOpts.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/41621/1 diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index 1e644c5..29a20e7 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -238,7 +238,7 @@ // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} +#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 -- To view, visit https://review.coreboot.org/c/coreboot/+/41621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I384bd96db51457e68a320b99ecdbb2ada0dfbdd5 Gerrit-Change-Number: 41621 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: Add FSP 2.2 specific support
by Nathaniel L Desimone (Code Review) 01 Jun '20

01 Jun '20

Nathaniel L Desimone has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41728 ) Change subject: drivers/intel/fsp2_0: Add FSP 2.2 specific support ...................................................................... Patch Set 2: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/41728/1/src/drivers/intel/fsp2_0/s… File src/drivers/intel/fsp2_0/silicon_init.c: https://review.coreboot.org/c/coreboot/+/41728/1/src/drivers/intel/fsp2_0/s… PS1, Line 100: multi_phase_params = xmalloc(sizeof(struct fsp_multi_phase_params)); : multi_phase_get_number = : xmalloc(sizeof(struct fsp_multi_phase_get_number_of_phase_params)); > Do we really need to allocate heap for these? Seems like they could be local variables on the stack. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/41728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Gerrit-Change-Number: 41728 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 01 Jun 2020 16:55:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Add FSP 2.2 specific support
by Subrata Banik (Code Review) 01 Jun '20

01 Jun '20

Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Maulik V Vaghela, Duncan Laurie, Sridhar Siricilla, Aamir Bohra, Andrey Petrov, Aaron Durbin, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41728 to look at the new patch set (#2). Change subject: drivers/intel/fsp2_0: Add FSP 2.2 specific support ...................................................................... drivers/intel/fsp2_0: Add FSP 2.2 specific support • Based on FSP EAS v2.1 – Backward compatibility is retained. • Added multi-phase silicon initialization to increase the modularity of the FspSiliconInit() API. • Added FspMultiPhaseSiInit() API • FSP_INFO_HEADER changes o Added FspMultiPhaseSiInitEntryOffset • Added FSPS_ARCH_UPD o Added EnableMultiPhaseSiliconInit, bootloaders designed for FSP 2.0/2.1 can disable the FspMultiPhaseSiInit() API and continue to use FspSiliconInit() without change. FSP 2.2 Specification: https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-… Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/include/fsp/info_header.h M src/drivers/intel/fsp2_0/include/fsp/upd.h M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/fsp2_0/util.c 7 files changed, 130 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/41728/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/41728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Gerrit-Change-Number: 41728 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/hatch: Enable the CSE Lite SKU for Puff variants
by Sridhar Siricilla (Code Review) 01 Jun '20

01 Jun '20

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41199 ) Change subject: mb/google/hatch: Enable the CSE Lite SKU for Puff variants ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/41199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0de6bca162b01870ca554ae97bc4a41cf66fef18 Gerrit-Change-Number: 41199 Gerrit-PatchSet: 7 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 01 Jun 2020 15:51:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch: Modify the puff fmd files to support CSE Lite SKU
by Sridhar Siricilla (Code Review) 01 Jun '20

01 Jun '20

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41198 ) Change subject: mb/google/hatch: Modify the puff fmd files to support CSE Lite SKU ...................................................................... Patch Set 10: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/41198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d39a1bdeabf48fc740da67539f48a9ff72c442c Gerrit-Change-Number: 41198 Gerrit-PatchSet: 10 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sam McNally <sammc(a)google.com> Gerrit-Comment-Date: Mon, 01 Jun 2020 15:50:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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