coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: payloads/tianocore: Enable PS2 keyboard module
by Matt DeVillier (Code Review) 25 Feb '20

25 Feb '20

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38960 ) Change subject: payloads/tianocore: Enable PS2 keyboard module ...................................................................... Patch Set 3: (2 comments) > Patch Set 3: > > (2 comments) > > Should this be a Kconfig option so only boards with PS/2 controllers enable this? On the other hand, that might be too complex, and the default payload configuration in coreboot should be generic. we don't selectively enable it in other payloads (eg, SeaBIOS), so I don't see why we'd do that here https://review.coreboot.org/c/coreboot/+/38960/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38960/3//COMMIT_MSG@9 PS3, Line 9: Upstream UEFIPayload now includes support for PS2 keyboards, but > Could you please reference the upstream commit adding the support? 33a3293: UefiPayloadPkg/BootManager: Add PS2 keyboard support https://review.coreboot.org/c/coreboot/+/38960/3//COMMIT_MSG@11 PS3, Line 11: > Please mention how much this increases the payload size. the payload size is fixed at 4MB uncompressed -- To view, visit https://review.coreboot.org/c/coreboot/+/38960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6d468809142a0049ce1648217d62b070229ad6b Gerrit-Change-Number: 38960 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 25 Feb 2020 16:59:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/dell: Add Dell Optiplex 790
by HAOUAS Elyes (Code Review) 25 Feb '20

25 Feb '20

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21774 ) Change subject: mb/dell: Add Dell Optiplex 790 ...................................................................... Patch Set 65: (1 comment) https://review.coreboot.org/c/coreboot/+/21774/60/src/mainboard/dell/optipl… File src/mainboard/dell/optiplex_790/romstage.c: https://review.coreboot.org/c/coreboot/+/21774/60/src/mainboard/dell/optipl… PS60, Line 17: : #include <stdint.h> : #include <string.h> : #include <timestamp.h> : #include <arch/byteorder.h> : #include <arch/io.h> : #include <device/mmio.h> : #include <device/pci_ops.h> : #include <device/pnp_ops.h> : #include <cpu/x86/lapic.h> : #include <console/console.h> : #include <northbridge/intel/sandybridge/sandybridge.h> : #include <northbridge/intel/sandybridge/raminit_native.h> : #include <southbridge/intel/bd82x6x/pch.h> : #include <southbridge/intel/common/gpio.h> > Done, I think? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/21774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3d3a13163d5da1368259a7498019d42fb3ed57f Gerrit-Change-Number: 21774 Gerrit-PatchSet: 65 Gerrit-Owner: Christoph Pomaska <github(a)slrie.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christoph Pomaska <github(a)slrie.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Tue, 25 Feb 2020 15:50:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/dell: Add Dell Optiplex 790
by Christoph Pomaska (Code Review) 25 Feb '20

25 Feb '20

Christoph Pomaska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21774 ) Change subject: mb/dell: Add Dell Optiplex 790 ...................................................................... Patch Set 65: (4 comments) https://review.coreboot.org/c/coreboot/+/21774/62//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/21774/62//COMMIT_MSG@48 PS62, Line 48: DisplayPort? > FIXME Done https://review.coreboot.org/c/coreboot/+/21774/62//COMMIT_MSG@49 PS62, Line 49: VGA BIOS? > FIXME Done https://review.coreboot.org/c/coreboot/+/21774/50/src/mainboard/dell/optipl… File src/mainboard/dell/optiplex_790/gma-mainboard.ads: https://review.coreboot.org/c/coreboot/+/21774/50/src/mainboard/dell/optipl… PS50, Line 23: : -- For a three-pipe setup, bandwidth is shared between the 2nd and : -- the 3rd pipe. Thus, probe ports that likely have a high-resolution : -- display attached first. > DONE Done https://review.coreboot.org/c/coreboot/+/21774/50/src/mainboard/dell/optipl… File src/mainboard/dell/optiplex_790/mainboard.c: https://review.coreboot.org/c/coreboot/+/21774/50/src/mainboard/dell/optipl… PS50, Line 14: > DONE Done -- To view, visit https://review.coreboot.org/c/coreboot/+/21774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3d3a13163d5da1368259a7498019d42fb3ed57f Gerrit-Change-Number: 21774 Gerrit-PatchSet: 65 Gerrit-Owner: Christoph Pomaska <github(a)slrie.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christoph Pomaska <github(a)slrie.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Tue, 25 Feb 2020 15:35:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by Paul Menzel (Code Review) 25 Feb '20

25 Feb '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38998 ) Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support ...................................................................... Patch Set 13: (5 comments) https://review.coreboot.org/c/coreboot/+/38998/13//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38998/13//COMMIT_MSG@13 PS13, Line 13: Upds UPDs https://review.coreboot.org/c/coreboot/+/38998/13/src/mainboard/intel/tglrv… File src/mainboard/intel/tglrvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/38998/13/src/mainboard/intel/tglrv… PS13, Line 48: spd_index = SPD_ID_MICRON; Why this assignment? https://review.coreboot.org/c/coreboot/+/38998/13/src/mainboard/intel/tglrv… PS13, Line 49: printk(BIOS_INFO, "Invalid board_id 0x%x\n", board_id); Sounds more like an error (or at least warning). https://review.coreboot.org/c/coreboot/+/38998/13/src/mainboard/intel/tglrv… PS13, Line 61: if (spd_index == SPD_ADDR_TABLE) { Variable not needed as only used once? https://review.coreboot.org/c/coreboot/+/38998/13/src/mainboard/intel/tglrv… PS13, Line 73: 0 false -- To view, visit https://review.coreboot.org/c/coreboot/+/38998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Gerrit-Change-Number: 38998 Gerrit-PatchSet: 13 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 25 Feb 2020 12:34:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/tianocore: Enable PS2 keyboard module
by Paul Menzel (Code Review) 25 Feb '20

25 Feb '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38960 ) Change subject: payloads/tianocore: Enable PS2 keyboard module ...................................................................... Patch Set 3: (2 comments) Should this be a Kconfig option so only boards with PS/2 controllers enable this? On the other hand, that might be too complex, and the default payload configuration in coreboot should be generic. https://review.coreboot.org/c/coreboot/+/38960/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38960/3//COMMIT_MSG@9 PS3, Line 9: Upstream UEFIPayload now includes support for PS2 keyboards, but Could you please reference the upstream commit adding the support? https://review.coreboot.org/c/coreboot/+/38960/3//COMMIT_MSG@11 PS3, Line 11: Please mention how much this increases the payload size. -- To view, visit https://review.coreboot.org/c/coreboot/+/38960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6d468809142a0049ce1648217d62b070229ad6b Gerrit-Change-Number: 38960 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 25 Feb 2020 11:58:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/hp: Set CBFS_SIZE
by Patrick Rudolph (Code Review) 25 Feb '20

25 Feb '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39073 ) Change subject: mb/hp: Set CBFS_SIZE ...................................................................... mb/hp: Set CBFS_SIZE Overwrite the default of 1 MiB with the actual bios regio size set in the stock IFD. Allows to use payloads like tianocore without manually touching the CBFS_SIZE. Change-Id: Ic1753a38212cc4961671fea11afe88265e73333b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/hp/compaq_8200_elite_sff/Kconfig M src/mainboard/hp/z220_sff_workstation/Kconfig 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/39073/1 diff --git a/src/mainboard/hp/compaq_8200_elite_sff/Kconfig b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig index e3b2ebd..6734d5b 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/Kconfig +++ b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig @@ -19,6 +19,9 @@ select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION +config CBFS_SIZE + default 0x2F0000 + config MAINBOARD_DIR string default "hp/compaq_8200_elite_sff" diff --git a/src/mainboard/hp/z220_sff_workstation/Kconfig b/src/mainboard/hp/z220_sff_workstation/Kconfig index dc288d6..8f28baf 100644 --- a/src/mainboard/hp/z220_sff_workstation/Kconfig +++ b/src/mainboard/hp/z220_sff_workstation/Kconfig @@ -30,6 +30,9 @@ hex default 0x2a +config CBFS_SIZE + default 0x570000 + config MAINBOARD_DIR string default "hp/z220_sff_workstation" -- To view, visit https://review.coreboot.org/c/coreboot/+/39073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1753a38212cc4961671fea11afe88265e73333b Gerrit-Change-Number: 39073 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/{apl,cnl,icl,skl,tgl}: Add comments for above 4GB mem range...
by Subrata Banik (Code Review) 25 Feb '20

25 Feb '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38388 ) Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Add comments for above 4GB mem range macro ...................................................................... soc/intel/{apl,cnl,icl,skl,tgl}: Add comments for above 4GB mem range macro Change-Id: Ibe812031ea91932ec63adb030541b5ab5db8f425 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/cannonlake/include/soc/iomap.h M src/soc/intel/icelake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/tigerlake/include/soc/iomap.h 5 files changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38388/1 diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index e2fa462..6a617bd 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -60,6 +60,16 @@ #define EARLY_I2C_BASE_ADDRESS 0xfe020000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) +/* + * Resource for the Top of Upper Usable DRAM (TOUUD) + * TOUUD base value is TOM minus all memory range as applicable + * (ME stolen memory, reclaim memory etc). + * Base is 2^37 = 128 GB. + * Length is 2^36 = 64 GB. + * The Host interface positively decodes an address towards DRAM if the incoming + * address is less than the value programmed in this register and greater than or + * equal to 4 GB. + */ #define ABOVE_4GB_MEM_BASE_ADDRESS (128ULL * GiB) #define ABOVE_4GB_MEM_BASE_SIZE (64ULL * GiB) diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h index c66cde4..a920940 100644 --- a/src/soc/intel/cannonlake/include/soc/iomap.h +++ b/src/soc/intel/cannonlake/include/soc/iomap.h @@ -68,6 +68,16 @@ #define HECI1_BASE_ADDRESS 0xfeda2000 +/* + * Resource for the Top of Upper Usable DRAM (TOUUD) + * TOUUD base value is TOM minus all memory range as applicable + * (ME stolen memory, reclaim memory etc). + * Base is 2^38 = 256 GB. + * Length is 2^38 = 256 GB. + * The Host interface positively decodes an address towards DRAM if the incoming + * address is less than the value programmed in this register and greater than or + * equal to 4 GB. + */ #define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB) #define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB) diff --git a/src/soc/intel/icelake/include/soc/iomap.h b/src/soc/intel/icelake/include/soc/iomap.h index 50ba005..77a8851 100644 --- a/src/soc/intel/icelake/include/soc/iomap.h +++ b/src/soc/intel/icelake/include/soc/iomap.h @@ -61,6 +61,16 @@ #define VTD_BASE_ADDRESS 0xFED90000 #define VTD_BASE_SIZE 0x00004000 +/* + * Resource for the Top of Upper Usable DRAM (TOUUD) + * TOUUD base value is TOM minus all memory range as applicable + * (ME stolen memory, reclaim memory etc). + * Base is 2^38 = 256 GB. + * Length is 2^38 = 256 GB. + * The Host interface positively decodes an address towards DRAM if the incoming + * address is less than the value programmed in this register and greater than or + * equal to 4 GB. + */ #define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB) #define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB) diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index b447d79..5cde8c1 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -75,6 +75,16 @@ #define PTT_TXT_BASE_ADDRESS 0xfed30800 #define PTT_PRESENT 0x00070000 +/* + * Resource for the Top of Upper Usable DRAM (TOUUD) + * TOUUD base value is TOM minus all memory range as applicable + * (ME stolen memory, reclaim memory etc). + * Base is 2^37 = 128 GB. + * Length is 2^36 = 64 GB. + * The Host interface positively decodes an address towards DRAM if the incoming + * address is less than the value programmed in this register and greater than or + * equal to 4 GB. + */ #define ABOVE_4GB_MEM_BASE_ADDRESS (128ULL * GiB) #define ABOVE_4GB_MEM_BASE_SIZE (64ULL * GiB) diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index 72ac25f..72d0a6d 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -67,6 +67,16 @@ #define VTD_BASE_ADDRESS 0xFED90000 #define VTD_BASE_SIZE 0x00004000 +/* + * Resource for the Top of Upper Usable DRAM (TOUUD) + * TOUUD base value is TOM minus all memory range as applicable + * (ME stolen memory, reclaim memory etc). + * Base is 2^38 = 256 GB. + * Length is 2^38 = 256 GB. + * The Host interface positively decodes an address towards DRAM if the incoming + * address is less than the value programmed in this register and greater than or + * equal to 4 GB. + */ #define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB) #define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB) -- To view, visit https://review.coreboot.org/c/coreboot/+/38388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe812031ea91932ec63adb030541b5ab5db8f425 Gerrit-Change-Number: 38388 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8183: Fix typo error of DRAMC setting
by huayang duan (Code Review) 25 Feb '20

25 Feb '20

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38474 ) Change subject: soc/mediatek/mt8183: Fix typo error of DRAMC setting ...................................................................... soc/mediatek/mt8183: Fix typo error of DRAMC setting 1. The ac timing of 2400Mbps should use diff params with 1600Mbps. 2. Fix the typo error of save shufffle function for DVFS. BRANCH=kukui BUG=none TEST=emerge-kukui coreboot Change-Id: I5edac32938def50836f386426e7deb652b80d42d Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/emi.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/38474/1 diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index cf104f8..3f157e3 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -325,7 +325,7 @@ { struct optimize_ac_time rf_cab_opt[LP4X_DDRFREQ_MAX] = { [LP4X_DDR1600] = {.rfc = 44, .rfc_05t = 0, .tx_ref_cnt = 62}, - [LP4X_DDR2400] = {.rfc = 44, .rfc_05t = 0, .tx_ref_cnt = 62}, + [LP4X_DDR2400] = {.rfc = 72, .rfc_05t = 0, .tx_ref_cnt = 91}, [LP4X_DDR3200] = {.rfc = 100, .rfc_05t = 0, .tx_ref_cnt = 119}, [LP4X_DDR3600] = {.rfc = 118, .rfc_05t = 1, .tx_ref_cnt = 138}, }; @@ -456,9 +456,9 @@ value = read32(src_addr) & 0x7f; if (dst_shuffle == DRAM_DFS_SHUFFLE_2) - clrsetbits32(dst_addr, 0x7f << 0x8, value << 0x8); + clrsetbits_le32(dst_addr, 0x7f << 8, value << 8); else if (dst_shuffle == DRAM_DFS_SHUFFLE_3) - clrsetbits32(dst_addr, 0x7f << 0x16, value << 0x16); + clrsetbits_le32(dst_addr, 0x7f << 16, value << 16); /* DRAMC-exception-2 */ src_addr = (u8 *)&ch[chn].ao.dvfsdll; -- To view, visit https://review.coreboot.org/c/coreboot/+/38474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5edac32938def50836f386426e7deb652b80d42d Gerrit-Change-Number: 38474 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/stdint.h: Remove old refrence to ROMCC
by HAOUAS Elyes (Code Review) 25 Feb '20

25 Feb '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39072 ) Change subject: include/stdint.h: Remove old refrence to ROMCC ...................................................................... include/stdint.h: Remove old refrence to ROMCC Change-Id: I00fdcee177c5d4b5e95bc3d0330fd8934eee2f0a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/stdint.h 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/39072/1 diff --git a/src/include/stdint.h b/src/include/stdint.h index b534add..3c9cdec 100644 --- a/src/include/stdint.h +++ b/src/include/stdint.h @@ -14,9 +14,9 @@ #ifndef STDINT_H #define STDINT_H -/* romcc does not support long long, _Static_assert, or _Bool, so we must ifdef that code out. - Also, GCC can provide its own implementation of stdint.h, so in theory we could use that - instead of this custom file once romcc is no more. */ +/* TODO: GCC can provide its own implementation of stdint.h, + * so in theory we could use that + */ /* Fixed width integer types */ typedef signed char int8_t; -- To view, visit https://review.coreboot.org/c/coreboot/+/39072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00fdcee177c5d4b5e95bc3d0330fd8934eee2f0a Gerrit-Change-Number: 39072 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/supermicro/x11-lga1151-series: fix PNP warning for SUART1/2
by Patrick Georgi (Code Review) 25 Feb '20

25 Feb '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39094 ) Change subject: mb/supermicro/x11-lga1151-series: fix PNP warning for SUART1/2 ...................................................................... mb/supermicro/x11-lga1151-series: fix PNP warning for SUART1/2 Fix PNP warning about missing devicetree entry for SUART1/2 by setting register 0xF0 to a sane (default) value. Change-Id: Ie852696aae09b9b03cebd6c3d8cbbd53a7138d89 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39094 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index f481c77..074e61b 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -100,10 +100,12 @@ device pnp 2e.2 on # SUART1 io 0x60 = 0x3f8 irq 0x70 = 4 + drq 0xf0 = 0x00 end device pnp 2e.3 on # SUART2 io 0x60 = 0x2f8 irq 0x70 = 3 + drq 0xf0 = 0x00 end device pnp 2e.4 on # SWC io 0x60 = 0xa00 diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index 0c7c17f..76e684c 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -87,10 +87,12 @@ device pnp 2e.2 on # SUART1 / COM1 (ext) io 0x60 = 0x3f8 irq 0x70 = 4 + drq 0xf0 = 0x00 end device pnp 2e.3 on # SUART2 / COM2 (int) io 0x60 = 0x2f8 irq 0x70 = 3 + drq 0xf0 = 0x00 end device pnp 2e.4 on # SWC io 0x60 = 0xa00 -- To view, visit https://review.coreboot.org/c/coreboot/+/39094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie852696aae09b9b03cebd6c3d8cbbd53a7138d89 Gerrit-Change-Number: 39094 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit February 2020