coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: payloads/tianocore: Enable PS2 keyboard module
by Benjamin Doron (Code Review) 26 Feb '20

26 Feb '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38960 ) Change subject: payloads/tianocore: Enable PS2 keyboard module ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/c/coreboot/+/38960/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38960/3//COMMIT_MSG@9 PS3, Line 9: Upstream UEFIPayload now includes support for PS2 keyboards, but > 33a3293: UefiPayloadPkg/BootManager: Add PS2 keyboard support Thanks, Matt. Added to commit message. https://review.coreboot.org/c/coreboot/+/38960/3//COMMIT_MSG@11 PS3, Line 11: > Thanks. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/38960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6d468809142a0049ce1648217d62b070229ad6b Gerrit-Change-Number: 38960 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 26 Feb 2020 17:44:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/tianocore: Enable PS2 keyboard module
by Benjamin Doron (Code Review) 26 Feb '20

26 Feb '20

Hello Angel Pons, Matt DeVillier, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38960 to look at the new patch set (#4). Change subject: payloads/tianocore: Enable PS2 keyboard module ...................................................................... payloads/tianocore: Enable PS2 keyboard module Upstream UEFIPayload[1] now includes support for PS2 keyboards, but defaults it to disabled. Enable it, as CorebootPayload does. Note that this increases payload size in coreboot by a little over 5 KiB. 1. https://github.com/tianocore/edk2/commit/33a32936510ecff00d0b6aeaeb9c8b2bf5… Change-Id: If6d468809142a0049ce1648217d62b070229ad6b Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M payloads/external/tianocore/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/38960/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/38960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6d468809142a0049ce1648217d62b070229ad6b Gerrit-Change-Number: 38960 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: ec/purism/librem: fix topstar driver ERAM mapping
by Matt DeVillier (Code Review) 26 Feb '20

26 Feb '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39105 ) Change subject: ec/purism/librem: fix topstar driver ERAM mapping ...................................................................... ec/purism/librem: fix topstar driver ERAM mapping Correct the offset for the Topstar driver enable/disable bit, which was off by 2 bits compared to a dump of the AMI UEFI ACPI. Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Change-Id: Ibc3c39d5b14c753eed6d1ed8cbf161717f8d04e0 --- M src/ec/purism/librem/acpi/ec.asl 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/39105/1 diff --git a/src/ec/purism/librem/acpi/ec.asl b/src/ec/purism/librem/acpi/ec.asl index 6f6ced1..b564727 100644 --- a/src/ec/purism/librem/acpi/ec.asl +++ b/src/ec/purism/librem/acpi/ec.asl @@ -65,6 +65,7 @@ BTLE, 1, /* Bluetooth Enable/Disable */ Offset (0x25), , 5, + FANM, 2, TPSE, 1, /* topstar-laptop driver enable/disable */ Offset (0x31), , 6, -- To view, visit https://review.coreboot.org/c/coreboot/+/39105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc3c39d5b14c753eed6d1ed8cbf161717f8d04e0 Gerrit-Change-Number: 39105 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: soc/intel/tigerlake: Add Legacy 8254 timer support
by Subrata Banik (Code Review) 26 Feb '20

26 Feb '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39098 ) Change subject: soc/intel/tigerlake: Add Legacy 8254 timer support ...................................................................... soc/intel/tigerlake: Add Legacy 8254 timer support This patch overrides required FSP-S UPDs to enable 8254 timer support for TGL. TEST=Required to boot Tiano core payload. Change-Id: Iaeff5c4b92691ed6ba7b71541ed4f947d5d299a8 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/tigerlake/fsp_params_tgl.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/39098/1 diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 305748e..dbee489 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -135,6 +135,10 @@ sizeof(params->SataPortsDevSlp)); } + /* Legacy 8254 timer support */ + params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; + params->Enable8254ClockGatingOnS3 = 1; + mainboard_silicon_init_params(params); } -- To view, visit https://review.coreboot.org/c/coreboot/+/39098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeff5c4b92691ed6ba7b71541ed4f947d5d299a8 Gerrit-Change-Number: 39098 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

6 10

Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by Patrick Georgi (Code Review) 26 Feb '20

26 Feb '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38998 ) Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support ...................................................................... mb/intel/tglrvp: add Tiger Lake memory initialization support Update memory parameters based on memory type supported by Tiger lake RVP 1. Update dq/dqs mappings 2. Update spd data for Tiger lake LPDDR4 SAMSUNG/MICRON memory 3. Add SPD data bin files for supported memory types 4. Update other FSPM UPDs as part of memory initialization BUG=none BRANCH=none TEST= build tglrvp flash and boot to kernel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38998 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/tglrvp/board_id.h M src/mainboard/intel/tglrvp/romstage_fsp_params.c A src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex M src/mainboard/intel/tglrvp/spd/Makefile.inc A src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex A src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex M src/mainboard/intel/tglrvp/spd/spd.h M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc A src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c 10 files changed, 245 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Nick Vaccaro: Looks good to me, approved Srinidhi N Kaushik: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, approved diff --git a/src/mainboard/intel/tglrvp/board_id.h b/src/mainboard/intel/tglrvp/board_id.h index 9aac527..364f4f7 100644 --- a/src/mainboard/intel/tglrvp/board_id.h +++ b/src/mainboard/intel/tglrvp/board_id.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,6 +21,11 @@ /* Board/FAB ID Command */ #define EC_FAB_ID_CMD 0x0D +/* TGL-U Board IDs */ +#define TGL_U_LP4_SAMSUNG 0x3 +#define TGL_U_LP4_HYNIX 0xB +#define TGL_U_LP4_MICRON 0x13 + /* * Returns board information (board id[15:8] and * Fab info[7:0]) on success and < 0 on error diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c index 0ab1f48..89ae0ab 100644 --- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -12,11 +12,55 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - +#include <assert.h> +#include <console/console.h> #include <fsp/api.h> #include <soc/romstage.h> +#include <spd_bin.h> +#include <string.h> +#include <soc/meminit_tgl.h> +#include <baseboard/variants.h> +#include <cbfs.h> +#include "board_id.h" +#include "spd/spd.h" + +static uintptr_t mainboard_get_spd_index(void) +{ + uint8_t board_id = (get_board_id() & 0xFF); + int spd_index; + + printk(BIOS_INFO, "board id is 0x%x\n", board_id); + + switch (board_id) { + case TGL_U_LP4_MICRON: + spd_index = SPD_ID_MICRON; + break; + case TGL_U_LP4_SAMSUNG: + spd_index = SPD_ID_SAMSUNG; + break; + case TGL_U_LP4_HYNIX: + spd_index = SPD_ID_HYNIX; + break; + default: + spd_index = SPD_ID_MICRON; + printk(BIOS_WARNING, "Invalid board_id 0x%x\n", board_id); + } + + printk(BIOS_INFO, "SPD index is 0x%x\n", spd_index); + return spd_index; +} void mainboard_memory_init_params(FSPM_UPD *mupd) { - /* ToDo : Fill FSP-M memory params */ + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + + const struct mb_lpddr4x_cfg *mem_config = variant_memory_params(); + const struct spd_info spd_info = { + .read_type = READ_SPD_CBFS, + .spd_spec.spd_index = mainboard_get_spd_index(), + }; + bool half_populated = false; + + meminit_lpddr4x_dimm0(mem_cfg, mem_config, &spd_info, half_populated); + } diff --git a/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex b/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex new file mode 100644 index 0000000..2ff9ed3 --- /dev/null +++ b/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 1B 21 F9 08 00 40 00 00 0A 01 00 00 +00 00 05 0F 92 54 01 00 8A 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 92 00 A7 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 56 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/tglrvp/spd/Makefile.inc b/src/mainboard/intel/tglrvp/spd/Makefile.inc index b8b059a..21ea65e 100644 --- a/src/mainboard/intel/tglrvp/spd/Makefile.inc +++ b/src/mainboard/intel/tglrvp/spd/Makefile.inc @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 Intel Corporation. +## Copyright (C) 2019-2020 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -13,8 +13,22 @@ ## GNU General Public License for more details. ## -romstage-y += spd_util.c - SPD_BIN = $(obj)/spd.bin -SPD_SOURCES = empty # 0b000 +SPD_SOURCES = Micron-MT53D1G64D8SQ-046 +SPD_SOURCES += Samsung-K4UBE3D4AA-MGCL +SPD_SOURCES += Hynix-H9HKNNNEBMAV-4267 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex b/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex new file mode 100644 index 0000000..40fccaa --- /dev/null +++ b/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex @@ -0,0 +1,32 @@ +23 10 11 0E 15 19 95 08 00 40 00 00 02 21 00 00 +48 00 05 FF 92 55 00 00 8C 00 90 A8 90 90 06 D0 +02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex b/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex new file mode 100644 index 0000000..945b2e8 --- /dev/null +++ b/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 B5 08 00 40 00 00 0A 21 00 00 +48 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 E0 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/tglrvp/spd/spd.h b/src/mainboard/intel/tglrvp/spd/spd.h index ed8b8b6..9e74624 100644 --- a/src/mainboard/intel/tglrvp/spd/spd.h +++ b/src/mainboard/intel/tglrvp/spd/spd.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,14 +16,16 @@ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H -#include <stdint.h> +/* SPD index definition should be matched with the order of SPD_SOURCES */ +#define SPD_ID_MICRON 0x0 +#define SPD_ID_SAMSUNG 0x1 +#define SPD_ID_HYNIX 0x2 -#define RCOMP_TARGET_PARAMS 0x5 +void mainboard_fill_dq_map_ch0(void *dq_map_ptr); +void mainboard_fill_dq_map_ch1(void *dq_map_ptr); +void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr); +void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); -void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr); -void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr); -void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr); -void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr); -void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr); -void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr); #endif diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h index 9220b11..25c9755 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,6 +17,7 @@ #define __BASEBOARD_VARIANTS_H__ #include <soc/gpio.h> +#include <soc/meminit_tgl.h> #include <stdint.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -27,4 +28,7 @@ const struct pad_config *variant_early_gpio_table(size_t *num); const struct cros_gpio *variant_cros_gpios(size_t *num); +size_t variant_memory_sku(void); +const struct mb_lpddr4x_cfg *variant_memory_params(void); + #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc index 23bf160..c272607 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 Intel Corporation. +## Copyright (C) 2019-2020 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -15,4 +15,6 @@ bootblock-y += gpio.c +romstage-y += memory.c + ramstage-y += gpio.c diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c new file mode 100644 index 0000000..67979b6 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <baseboard/variants.h> +#include <intelblocks/mp_init.h> + +size_t __weak variant_memory_sku(void) +{ + return 0; +} + +static const struct mb_lpddr4x_cfg mem_config = { + /* DQ byte map */ + .dq_map = { + { 0, 1, 6, 7, 3, 2, 5, 4, /* Byte 0 */ + 15, 8, 9, 14, 12, 11, 10, 13 }, /* Byte 1 */ + { 11, 12, 8, 15, 9, 14, 10, 13, /* Byte 2 */ + 3, 4, 7, 0, 6, 1, 5, 2 }, /* Byte 3 */ + { 4, 5, 3, 2, 7, 1, 0, 6, /* Byte 4 */ + 11, 10, 12, 13, 8, 9, 14, 15 }, /* Byte 5 */ + { 12, 11, 8, 13, 14, 15, 9, 10, /* Byte 6 */ + 4, 7, 3, 2, 1, 6, 0, 5 }, /* Byte 7 */ + { 11, 10, 9, 8, 12, 13, 15, 14, /* Byte 0 */ + 4, 5, 6, 7, 3, 2, 0, 1 }, /* Byte 1 */ + { 0, 7, 1, 6, 3, 5, 2, 4, /* Byte 2 */ + 9, 8, 10, 11, 14, 15, 13, 12 }, /* Byte 3 */ + { 4, 5, 6, 1, 3, 2, 7, 0, /* Byte 4 */ + 10, 13, 12, 11, 14, 9, 15, 8 }, /* Byte 5 */ + { 10, 12, 9, 15, 8, 11, 13, 14, /* Byte 6 */ + 3, 4, 1, 2, 6, 0, 5, 7 } /* Byte 7 */ + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + /* Ch 0 1 2 3 */ + { 0, 1 }, { 1, 0 }, { 0, 1 }, { 1, 0 }, + { 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 } + }, + + .ect = 1, /* Early Command Training */ +}; + +const struct mb_lpddr4x_cfg *__weak variant_memory_params(void) +{ + return &mem_config; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/38998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Gerrit-Change-Number: 38998 Gerrit-PatchSet: 16 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mainboard/hatch: Fix GPE wake comments
by Edward O'Callaghan (Code Review) 26 Feb '20

26 Feb '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38491 ) Change subject: mainboard/hatch: Fix GPE wake comments ...................................................................... mainboard/hatch: Fix GPE wake comments The indirection of names is exceedingly confusing for ultimately the single interrupt trace of EC_PCH_WAKE_ODL between the EC gpio#74 to GPD2/LAN_WAKE# on the PCH side. This helps folks chase this indirection down though the code. BUG=b:147026979 BRANCH=none TEST=builds Change-Id: I35d746a202dae06d2f6f1edfaa3889864b09f50d Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/hatch/variants/puff/include/variant/ec.h 3 files changed, 8 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/38491/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index dcd987f..527bf93 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -377,7 +377,7 @@ /* H23 : GPP_H23_STRAP */ PAD_NC(GPP_H23, NONE), - /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_OD */ + /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* SD card detect VGPIO */ diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h index e83732c..7bdd912 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h @@ -22,7 +22,7 @@ #define GPIO_PCH_WP GPP_C20 -/* EC wake pin is LAN_WAKE# */ +/* EC wake pin is routed to GPD2/LAN_WAKE# on PCH */ #define GPE_EC_WAKE GPE0_LAN_WAK /* eSPI virtual wire reporting */ diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h index 501fab0..34641c0 100644 --- a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h @@ -54,7 +54,12 @@ /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE -/* Provide wake pin for EC for _PRW WoL method */ +/** + * Defines EC wake pin route for the _PRW WoL method. + * Note that GPE_EC_WAKE is defined, confusingly, as + * GPE_LAN_WAK which is GPD2/LAN_WAKE# on the PCH or + * as the line EC_PCH_WAKE_ODL on the schematic. + */ #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35d746a202dae06d2f6f1edfaa3889864b09f50d Gerrit-Change-Number: 38491 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: mb/google/dedede: Update GPE configuration
by Karthik Ramasubramanian (Code Review) 26 Feb '20

26 Feb '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39112 ) Change subject: mb/google/dedede: Update GPE configuration ...................................................................... mb/google/dedede: Update GPE configuration WWAN wake event is routed to GPP_D0 GPIO and Pen Detect wake event is routed to GPP_C12 GPIO. Update the GPE configuration accordingly. BUG=None TEST=Build the mainboard. Change-Id: Id36d2c8265a0b7ea241565f6bb723df6b37446fa Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/39112/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index c17620b..ea7689e 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -11,13 +11,14 @@ # - GPP_B3 - TRACKPAD_INT_ODL # - GPP_B4 - H1_AP_INT_ODL # DW1 is used by: - # - GPP_D3 - WLAN_PCIE_WAKE_ODL + # - GPP_C12 - AP_PEN_DET_ODL # DW2 is used by: - # - GPP_H16 - WWAN_HOST_WAKE + # - GPP_D0 - WWAN_HOST_WAKE + # - GPP_D3 - WLAN_PCIE_WAKE_ODL # EC_AP_WAKE_ODL is routed to LAN_WAKE#/GPD02 & is part of DW3. register "pmc_gpe0_dw0" = "GPP_B" - register "pmc_gpe0_dw1" = "GPP_D" - register "pmc_gpe0_dw2" = "GPP_H" + register "pmc_gpe0_dw1" = "GPP_C" + register "pmc_gpe0_dw2" = "GPP_D" # USB Port Configuration register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C0 -- To view, visit https://review.coreboot.org/c/coreboot/+/39112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id36d2c8265a0b7ea241565f6bb723df6b37446fa Gerrit-Change-Number: 39112 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: Get rid of ROMCC
by HAOUAS Elyes (Code Review) 26 Feb '20

26 Feb '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39116 ) Change subject: Get rid of ROMCC ...................................................................... Get rid of ROMCC Change-Id: Ib9816f6a4e064a82e81ca68a1906b1107a2abda3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M .gitignore M util/abuild/abuild.1 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/39116/1 diff --git a/.gitignore b/.gitignore index 0cc6ae2..86ddd19 100644 --- a/.gitignore +++ b/.gitignore @@ -115,7 +115,6 @@ util/nvramtool/nvramtool util/optionlist/Options.wiki util/pmh7tool/pmh7tool -util/romcc/build util/runfw/googlesnow util/superiotool/superiotool util/vgabios/testbios diff --git a/util/abuild/abuild.1 b/util/abuild/abuild.1 index 2eee84b..ccdfff6 100644 --- a/util/abuild/abuild.1 +++ b/util/abuild/abuild.1 @@ -78,7 +78,6 @@ .B abuild is covered by the GNU General Public License (GPL), version 2 or later. .SH SEE ALSO -.BR romcc (1), .BR flashrom (1). .SH COPYRIGHT 2004 Stefan Reinauer -- To view, visit https://review.coreboot.org/c/coreboot/+/39116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9816f6a4e064a82e81ca68a1906b1107a2abda3 Gerrit-Change-Number: 39116 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: treewide: capitalize 'USB'
by HAOUAS Elyes (Code Review) 26 Feb '20

26 Feb '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39100 ) Change subject: treewide: capitalize 'USB' ...................................................................... treewide: capitalize 'USB' Change-Id: I7650786ea50465a4c2d11de948fdb81f4e509772 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M payloads/libpayload/drivers/udc/chipidea.c M payloads/libpayload/drivers/udc/chipidea_priv.h M payloads/libpayload/drivers/usb/ehci.c M payloads/libpayload/drivers/usb/usb.c M payloads/libpayload/drivers/usb/usbmsc.c M payloads/libpayload/include/libpayload.h M payloads/libpayload/include/usb/usb.h M src/drivers/usb/ehci_debug.c M src/mainboard/google/butterfly/early_init.c M src/mainboard/google/link/early_init.c M src/mainboard/google/mistral/mainboard.c M src/mainboard/google/oak/mainboard.c M src/mainboard/google/parrot/early_init.c M src/mainboard/google/stout/early_init.c M src/mainboard/intel/emeraldlake2/early_init.c M src/mainboard/intel/harcuvar/hsio.h M src/mainboard/kontron/ktqm77/early_init.c M src/mainboard/lenovo/t430s/variants/t431s/romstage.c M src/mainboard/samsung/lumpy/early_init.c M src/mainboard/samsung/stumpy/early_init.c M src/mainboard/scaleway/tagada/hsio.h M src/soc/intel/apollolake/chip.c M src/soc/intel/common/block/xhci/elog.c M src/soc/mediatek/common/usb.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/intel/i82801gx/early_init.c M util/uio_usbdebug/uio_usbdebug_intel.c 27 files changed, 46 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/39100/1 diff --git a/payloads/libpayload/drivers/udc/chipidea.c b/payloads/libpayload/drivers/udc/chipidea.c index 702cd6e..d8d02f2 100644 --- a/payloads/libpayload/drivers/udc/chipidea.c +++ b/payloads/libpayload/drivers/udc/chipidea.c @@ -81,7 +81,7 @@ memcpy(&this->device_descriptor, dd, sizeof(*dd)); if (p->qhlist == NULL) - die("failed to allocate memory for usb device mode"); + die("failed to allocate memory for USB device mode"); memset(p->qhlist, 0, sizeof(struct qh) * CI_QHELEMENTS); @@ -102,7 +102,7 @@ p->qhlist[1].config = QH_MPS(64) | QH_NO_AUTO_ZLT | QH_IOS; do { - debug("waiting for usb phy clk valid: %x\n", + debug("waiting for USB phy clk valid: %x\n", readl(&p->opreg->susp_ctrl)); mdelay(1); } while ((readl(&p->opreg->susp_ctrl) & (1 << 7)) == 0); diff --git a/payloads/libpayload/drivers/udc/chipidea_priv.h b/payloads/libpayload/drivers/udc/chipidea_priv.h index ede97ab..82870c3 100644 --- a/payloads/libpayload/drivers/udc/chipidea_priv.h +++ b/payloads/libpayload/drivers/udc/chipidea_priv.h @@ -47,7 +47,7 @@ uint32_t portsc; // 0x174 uint32_t pad178[15]; uint32_t devlc; // 0x1b4 - /* 25:26: host-desired usb version + /* 25:26: host-desired USB version * 23: force full speed */ uint32_t pad1b8[16]; uint32_t usbmode; // 0x1f8 diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index 1cfa8bb..bf8a5ea 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -291,7 +291,7 @@ /* Memory barrier to ensure that all memory accesses before we set the * async schedule are complete. It was observed especially in the case of - * arm64, that netboot and usb stuff resulted in lots of errors possibly + * arm64, that netboot and USB stuff resulted in lots of errors possibly * due to CPU reordering. Hence, enforcing strict CPU ordering. */ mb(); diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index d98fd9e..942e1b1 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -634,14 +634,14 @@ /* * Should be called by the hub drivers whenever a physical detach occurs - * and can be called by usb class drivers if they are unsatisfied with a + * and can be called by USB class drivers if they are unsatisfied with a * malfunctioning device. */ void usb_detach_device(hci_t *controller, int devno) { /* check if device exists, as we may have - been called yet by the usb class driver */ + been called yet by the USB class driver */ if (controller->devices[devno]) { controller->devices[devno]->destroy (controller->devices[devno]); diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c index 50fd24b..ed7ad1a 100755 --- a/payloads/libpayload/drivers/usb/usbmsc.c +++ b/payloads/libpayload/drivers/usb/usbmsc.c @@ -126,7 +126,7 @@ * MSC commands can be * successful, * fail with proper response or - * fail totally, which results in detaching of the usb device + * fail totally, which results in detaching of the USB device * and immediate cleanup of the usbdev_t structure. * In the latter case the caller has to make sure, that he won't * use the device any more. @@ -703,14 +703,14 @@ return; if (!prev_ready && msc->ready) { - usb_debug ("usb msc: not ready -> ready (lun %d)\n", msc->lun); + usb_debug ("USB msc: not ready -> ready (lun %d)\n", msc->lun); usb_msc_create_disk (dev); } else if (prev_ready && !msc->ready) { - usb_debug ("usb msc: ready -> not ready (lun %d)\n", msc->lun); + usb_debug ("USB msc: ready -> not ready (lun %d)\n", msc->lun); usb_msc_remove_disk (dev); } else if (!prev_ready && !msc->ready) { u8 new_lun = (msc->lun + 1) % msc->num_luns; - usb_debug("usb msc: not ready (lun %d) -> lun %d\n", msc->lun, + usb_debug("USB msc: not ready (lun %d) -> lun %d\n", msc->lun, new_lun); msc->lun = new_lun; } diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 4b6a250..f8e58fe 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -158,7 +158,7 @@ /** @} */ /** - * @defgroup usb USB functions + * @defgroup USB USB functions * @{ */ int usb_initialize(void); diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h index 8505c4f..5d27f7c 100644 --- a/payloads/libpayload/include/usb/usb.h +++ b/payloads/libpayload/include/usb/usb.h @@ -217,7 +217,7 @@ hci_t *controller; endpoint_t endpoints[32]; int num_endp; - int address; // usb address + int address; // USB address int hub; // hub, device is attached to int port; // port where device is attached usb_speed speed; @@ -263,7 +263,7 @@ u8* (*poll_intr_queue) (void *queue); void *instance; - /* set_address(): Tell the usb device its address (xHCI + /* set_address(): Tell the USB device its address (xHCI controllers want to do this by themselves). Also, allocate the usbdev structure, initialize enpoint 0 diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 5a3f2a6..97b39f4 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -382,7 +382,7 @@ u32 portsc; int loop; - /* Reset the usb debug port */ + /* Reset the USB debug port */ portsc = read32(&ehci_regs->port_status[port - 1]); portsc &= ~PORT_PE; portsc |= PORT_RESET; diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index 13819f1..35f75c4 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -67,7 +67,7 @@ } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power usb oc pin */ + /* enabled power USB oc pin */ { 1, 0, -1 }, /* P0: Right USB 3.0 #1 (no OC) */ { 1, 0, -1 }, /* P1: Right USB 3.0 #2 (no OC) */ { 1, 0, -1 }, /* P2: Camera (no OC) */ @@ -120,7 +120,7 @@ .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600, .usb_port_config = { - /* enabled usb oc pin length */ + /* enabled USB oc pin length */ { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ { 1, 0, 0x0040 }, /* P2: Camera (no OC) */ diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index c234e5b..7d1c177 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -154,7 +154,7 @@ } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power usb oc pin */ + /* enabled power USB oc pin */ { 0, 0, -1 }, /* P0: Empty */ { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c index e36a1c7..4a109f1 100644 --- a/src/mainboard/google/mistral/mainboard.c +++ b/src/mainboard/google/mistral/mainboard.c @@ -26,7 +26,7 @@ static void setup_usb(void) { - /* Setting Secondary usb controller */ + /* Setting Secondary USB controller */ setup_usb_host(HSUSB_HS_PORT_1, &usb1_board_data); } diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 421826c..864837b 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -145,7 +145,7 @@ static void configure_usb_hub(void) { - /* set usb hub reset pin (low active) to high */ + /* set USB hub reset pin (low active) to high */ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4) gpio_output(GPIO(UTXD3), 1); } diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index 01c4526..917d165 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -116,7 +116,7 @@ } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power usb oc pin */ + /* enabled power USB oc pin */ { 0, 0, -1 }, /* P0: Empty */ { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index 07c19c5..b4e96f0 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -131,7 +131,7 @@ .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600, .usb_port_config = { - /* enabled usb oc pin length */ + /* enabled USB oc pin length */ { 1, 0, 0x0040 }, /* P0: USB 3.0 1 (OC0) */ { 1, 0, 0x0040 }, /* P1: USB 3.0 2 (OC0) */ { 0, 1, 0x0000 }, /* P2: Empty */ @@ -171,7 +171,7 @@ } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled usb oc pin length */ + /* enabled USB oc pin length */ {1, 0, 0}, /* P0: USB 3.0 1 (OC0) */ {1, 0, 0}, /* P1: USB 3.0 2 (OC0) */ {0, 0, 0}, /* P2: Empty */ diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index 2d97c85..0bc5884 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -111,7 +111,7 @@ } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power usb oc pin */ + /* enabled power USB oc pin */ { 1, 0, 0 }, /* P0: Front port (OC0) */ { 1, 0, 1 }, /* P1: Back port (OC1) */ { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ diff --git a/src/mainboard/intel/harcuvar/hsio.h b/src/mainboard/intel/harcuvar/hsio.h index ce059fd..c59cfd0 100644 --- a/src/mainboard/intel/harcuvar/hsio.h +++ b/src/mainboard/intel/harcuvar/hsio.h @@ -38,7 +38,7 @@ * Lane[19]->USB3 rear I/O panel connector */ - /* SKU HSIO 20 (pcie [0-15] sata [16-18] usb [19]) */ + /* SKU HSIO 20 (pcie [0-15] sata [16-18] USB [19]) */ {BL_SKU_HSIO_20, {PCIE_BIF_CTRL_x8, PCIE_BIF_CTRL_x4x4}, {/* ME_FIA_MUX_CONFIG */ @@ -155,7 +155,7 @@ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 12 (pcie [0-3, 8-9, 12-13] sata [16-18] usb [19]) */ + /* SKU HSIO 12 (pcie [0-3, 8-9, 12-13] sata [16-18] USB [19]) */ {BL_SKU_HSIO_12, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {/*ME_FIA_MUX_CONFIG */ @@ -272,7 +272,7 @@ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 10 (pcie [0-3, 8-9, 12] sata [16-17] usb [19]) */ + /* SKU HSIO 10 (pcie [0-3, 8-9, 12] sata [16-17] USB [19]) */ {BL_SKU_HSIO_10, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ @@ -388,7 +388,7 @@ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 8 (pcie [0-1, 8-9, 12] sata [16-17] usb [19]) */ + /* SKU HSIO 8 (pcie [0-1, 8-9, 12] sata [16-17] USB [19]) */ {BL_SKU_HSIO_08, {PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ @@ -504,7 +504,7 @@ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 6 (pcie [0-1, 8, 12] sata [16] usb [19]) */ + /* SKU HSIO 6 (pcie [0-1, 8, 12] sata [16] USB [19]) */ {BL_SKU_HSIO_06, {PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index eac19f4..df5f57e 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -99,7 +99,7 @@ .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600, .usb_port_config = { - /* enabled usb oc pin length */ + /* enabled USB oc pin length */ { 1, 0, 0x0040 }, /* P0: lower left USB 3.0 (OC0) */ { 1, 0, 0x0040 }, /* P1: upper left USB 3.0 (OC0) */ { 1, 0, 0x0040 }, /* P2: lower right USB 3.0 (OC0) */ @@ -127,7 +127,7 @@ } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power usb oc pin */ + /* enabled power USB oc pin */ { 1, 0, 0 }, /* P0: lower left USB 3.0 (OC0) */ { 1, 0, 0 }, /* P1: upper left USB 3.0 (OC0) */ { 1, 0, 0 }, /* P2: lower right USB 3.0 (OC0) */ diff --git a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c index 04ddbe07..608ff2c 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c @@ -27,7 +27,7 @@ { 1, 0, 0 }, /* SSP1: right */ { 1, 0, 1 }, /* SSP2: left, EHCI Debug */ { 1, 1, 3 }, /* SSP3: dock usb3 */ - { 1, 1, -1 }, /* B0P4: wwan usb */ + { 1, 1, -1 }, /* B0P4: wwan USB */ { 1, 1, 2 }, /* B0P5: dock usb2 */ { 0, 0, -1 }, /* B0P6 */ { 0, 0, -1 }, /* B0P7 */ @@ -36,7 +36,7 @@ { 0, 2, 5 }, /* B1P2 */ { 1, 1, -1 }, /* B1P3: fingerprint reader */ { 0, 0, -1 }, /* B1P4 */ - { 1, 1, -1 }, /* B1P5: wlan usb */ + { 1, 1, -1 }, /* B1P5: wlan USB */ { 1, 1, -1 }, /* B1P6: Camera */ }; diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index 3380253..0249c3b 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -178,7 +178,7 @@ } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power usb oc pin */ + /* enabled power USB oc pin */ { 1, 1, 0 }, /* P0: Port 0 (OC0) */ { 1, 1, 1 }, /* P1: Port 1 (OC1) */ { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index d7f9b90..13da85a 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -167,7 +167,7 @@ } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power usb oc pin */ + /* enabled power USB oc pin */ { 1, 1, 0 }, /* P0: Front port (OC0) */ { 1, 0, 1 }, /* P1: Back port (OC1) */ { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ diff --git a/src/mainboard/scaleway/tagada/hsio.h b/src/mainboard/scaleway/tagada/hsio.h index e49fefd..aa6af53 100644 --- a/src/mainboard/scaleway/tagada/hsio.h +++ b/src/mainboard/scaleway/tagada/hsio.h @@ -38,7 +38,7 @@ * Lane[19]->USB3 rear I/O panel connector */ - /* SKU HSIO 20 (pcie [12-15] sata [8-11,12,14] usb [19]) */ + /* SKU HSIO 20 (pcie [12-15] sata [8-11,12,14] USB [19]) */ {BL_SKU_HSIO_20, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ @@ -155,7 +155,7 @@ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 12 (pcie [12-15] sata [8-11,12,14] usb [19]) */ + /* SKU HSIO 12 (pcie [12-15] sata [8-11,12,14] USB [19]) */ {BL_SKU_HSIO_12, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ @@ -273,7 +273,7 @@ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 10 (pcie [12-15] sata [8-11,12,14] usb [19]) */ + /* SKU HSIO 10 (pcie [12-15] sata [8-11,12,14] USB [19]) */ {BL_SKU_HSIO_10, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ @@ -391,7 +391,7 @@ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 8 (pcie [12-14] sata [8-11,12,14] usb [19]) */ + /* SKU HSIO 8 (pcie [12-14] sata [8-11,12,14] USB [19]) */ {BL_SKU_HSIO_08, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ @@ -509,7 +509,7 @@ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 6 (pcie [12,14] sata [8-11,12,14] usb []) */ + /* SKU HSIO 6 (pcie [12,14] sata [8-11,12,14] USB []) */ {BL_SKU_HSIO_06, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index b9c5a4f..03e6dbd 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -842,7 +842,7 @@ /* * Override GLK xhci clock gating register(XHCLKGTEN) to - * mitigate usb device suspend and resume failure. + * mitigate USB device suspend and resume failure. */ if (CONFIG(SOC_INTEL_GLK)) { uint32_t *cfg; diff --git a/src/soc/intel/common/block/xhci/elog.c b/src/soc/intel/common/block/xhci/elog.c index 0fd41bf..d8ee29c 100644 --- a/src/soc/intel/common/block/xhci/elog.c +++ b/src/soc/intel/common/block/xhci/elog.c @@ -84,7 +84,7 @@ /* * Check if CSC bit is set and port is capable of wake on * connect/disconnect to identify if the port caused wake - * event for usb attach/detach. + * event for USB attach/detach. */ if (pch_xhci_csc_set(port_status) && pch_xhci_wake_capable(port_status)) { @@ -95,7 +95,7 @@ /* * Check if PLC is set and PLS indicates resume to identify if - * the port caused wake event for usb activity. + * the port caused wake event for USB activity. */ if (pch_xhci_plc_set(port_status) && pch_xhci_resume(port_status)) { diff --git a/src/soc/mediatek/common/usb.c b/src/soc/mediatek/common/usb.c index d80cfe9..b148093 100644 --- a/src/soc/mediatek/common/usb.c +++ b/src/soc/mediatek/common/usb.c @@ -104,7 +104,7 @@ do { if (stopwatch_expired(&sw)) { - u3p_err("usb clocks are not stable!!!\n"); + u3p_err("USB clocks are not stable!!!\n"); return -1; } diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index d6003be..21c578f 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -214,7 +214,7 @@ }; /* - * The pci id of usb ctrl 0 and 1 are the same. + * The pci id of USB ctrl 0 and 1 are the same. */ static const struct pci_driver usb_ohci123_driver __pci_driver = { .ops = &usb_ops, diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index a627cc1..fa578f7 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -99,7 +99,7 @@ reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); - /* usb transient disconnect */ + /* USB transient disconnect */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); reg8 |= (3 << 0); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); diff --git a/util/uio_usbdebug/uio_usbdebug_intel.c b/util/uio_usbdebug/uio_usbdebug_intel.c index 9271896..2295cab 100644 --- a/util/uio_usbdebug/uio_usbdebug_intel.c +++ b/util/uio_usbdebug/uio_usbdebug_intel.c @@ -52,7 +52,7 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) { - /* claim usb debug port */ + /* claim USB debug port */ const unsigned long dbgctl_addr = ((unsigned long)ehci_bar) + CONFIG_EHCI_DEBUG_OFFSET; write32(dbgctl_addr, read32(dbgctl_addr) | (1 << 30)); -- To view, visit https://review.coreboot.org/c/coreboot/+/39100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7650786ea50465a4c2d11de948fdb81f4e509772 Gerrit-Change-Number: 39100 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: mb/kontron/mal10: add options for carrier board selection
by Maxim Polyakov (Code Review) 26 Feb '20

26 Feb '20

Maxim Polyakov has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39045 ) Change subject: mb/kontron/mal10: add options for carrier board selection ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/39045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81388f3c2a5cb751c6b69ef1e398234b05b81c8b Gerrit-Change-Number: 39045 Gerrit-PatchSet: 5 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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