coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

1 participants
1797 discussions

Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header file for Tiger Lake
by Ronak Kanabar (Code Review) 26 Feb '20

26 Feb '20

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39117 ) Change subject: vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header file for Tiger Lake ...................................................................... vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header file for Tiger Lake Update FSP header file for Tiger Lake platform version 2457. Added SerialIoUartAutoFlow, Enable8254ClockGating, Enable8254ClockGatingOnS3 UPD Change-Id: Ib2a08ce73526fb0eb4e7c2a674af78c2913f0a08 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 1 file changed, 62 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/39117/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index 6cf3668..24cbd6e 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -187,7 +187,16 @@ /** Offset 0x00CA - Reserved **/ - UINT8 Reserved4[74]; + UINT8 Reserved4[65]; + +/** Offset 0x010B - Enables UART hardware flow control, CTS and RTS lines + Enables UART hardware flow control, CTS and RTS lines. +**/ + UINT8 SerialIoUartAutoFlow[7]; + +/** Offset 0x0112 - Reserved +**/ + UINT8 Reserved5[2]; /** Offset 0x0114 - SerialIoUartRtsPinMuxPolicy Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* @@ -223,7 +232,7 @@ /** Offset 0x0185 - Reserved **/ - UINT8 Reserved5[7]; + UINT8 Reserved6[7]; /** Offset 0x018C - I2Cn Device Mode Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available @@ -245,7 +254,7 @@ /** Offset 0x01D4 - Reserved **/ - UINT8 Reserved6[192]; + UINT8 Reserved7[192]; /** Offset 0x0294 - USB Per Port HS Preemphasis Bias USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, @@ -297,7 +306,7 @@ /** Offset 0x02FC - Reserved **/ - UINT8 Reserved7[80]; + UINT8 Reserved8[80]; /** Offset 0x034C - Enable LAN Enable/disable LAN controller. @@ -307,7 +316,7 @@ /** Offset 0x034D - Reserved **/ - UINT8 Reserved8[11]; + UINT8 Reserved9[11]; /** Offset 0x0358 - PCIe PTM enable/disable Enable/disable Precision Time Measurement for PCIE Root Ports. @@ -316,7 +325,7 @@ /** Offset 0x0370 - Reserved **/ - UINT8 Reserved9[73]; + UINT8 Reserved10[73]; /** Offset 0x03B9 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX @@ -332,7 +341,7 @@ /** Offset 0x03BB - Reserved **/ - UINT8 Reserved10; + UINT8 Reserved11; /** Offset 0x03BC - Transition time in microseconds from Off (0V) to High Current Mode Voltage This field has 1us resolution. When value is 0 Transition to 0V is disabled. @@ -341,7 +350,7 @@ /** Offset 0x03BE - Reserved **/ - UINT8 Reserved11[38]; + UINT8 Reserved12[38]; /** Offset 0x03E4 - CNVi Configuration This option allows for automatic detection of Connectivity Solution. [Auto Detection] @@ -364,7 +373,7 @@ /** Offset 0x03E7 - Reserved **/ - UINT8 Reserved12; + UINT8 Reserved13; /** Offset 0x03E8 - CNVi RF_RESET pin muxing Select CNVi RF_RESET# pin depending on board routing. TGP-LP: GPP_A8 = 0x2942E408(default) @@ -381,18 +390,18 @@ /** Offset 0x03F0 - Reserved **/ - UINT8 Reserved13[14]; + UINT8 Reserved14[14]; /** Offset 0x03FE - HECI3 state The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. - DEPRECATED 0: disable, 1: enable + 0: disable, 1: enable $EN_DIS **/ UINT8 Heci3Enabled; /** Offset 0x03FF - Reserved **/ - UINT8 Reserved14[141]; + UINT8 Reserved15[141]; /** Offset 0x048C - CdClock Frequency selection 0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: @@ -410,7 +419,7 @@ /** Offset 0x048E - Reserved **/ - UINT8 Reserved15[2]; + UINT8 Reserved16[2]; /** Offset 0x0490 - TypeC port GPIO setting GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined @@ -421,7 +430,7 @@ /** Offset 0x04B0 - Reserved **/ - UINT8 Reserved16[30]; + UINT8 Reserved17[30]; /** Offset 0x04CE - TCSS Aux Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides @@ -435,7 +444,7 @@ /** Offset 0x04D2 - Reserved **/ - UINT8 Reserved17[2]; + UINT8 Reserved18[2]; /** Offset 0x04D4 - ITBT Root Port Enable ITBT Root Port Enable, 0:Disable, 1:Enable @@ -445,7 +454,7 @@ /** Offset 0x04D8 - Reserved **/ - UINT8 Reserved18[11]; + UINT8 Reserved19[11]; /** Offset 0x04E3 - Enable/Disable PTM This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports @@ -455,7 +464,7 @@ /** Offset 0x04E7 - Reserved **/ - UINT8 Reserved19[194]; + UINT8 Reserved20[194]; /** Offset 0x05A9 - Skip Multi-Processor Initialization When this is skipped, boot loader must initialize processors before SilicionInit @@ -466,7 +475,7 @@ /** Offset 0x05AA - Reserved **/ - UINT8 Reserved20[60]; + UINT8 Reserved21[60]; /** Offset 0x05E6 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. @@ -476,7 +485,7 @@ /** Offset 0x05E7 - Reserved **/ - UINT8 Reserved21[36]; + UINT8 Reserved22[36]; /** Offset 0x060B - Enable PCH ISH SPI Cs0 pins assigned Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. @@ -485,7 +494,7 @@ /** Offset 0x060C - Reserved **/ - UINT8 Reserved22[2]; + UINT8 Reserved23[2]; /** Offset 0x060E - Enable PCH ISH SPI pins assigned Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. @@ -509,7 +518,7 @@ /** Offset 0x061C - Reserved **/ - UINT8 Reserved23[2]; + UINT8 Reserved24[2]; /** Offset 0x061E - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region @@ -520,7 +529,7 @@ /** Offset 0x061F - Reserved **/ - UINT8 Reserved24[75]; + UINT8 Reserved25[75]; /** Offset 0x066A - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management. @@ -534,7 +543,7 @@ /** Offset 0x069A - Reserved **/ - UINT8 Reserved25[168]; + UINT8 Reserved26[168]; /** Offset 0x0742 - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. @@ -543,7 +552,7 @@ /** Offset 0x075A - Reserved **/ - UINT8 Reserved26[86]; + UINT8 Reserved27[86]; /** Offset 0x07B0 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is @@ -564,7 +573,7 @@ /** Offset 0x07F8 - Reserved **/ - UINT8 Reserved27[98]; + UINT8 Reserved28[98]; /** Offset 0x085A - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. @@ -574,7 +583,7 @@ /** Offset 0x085B - Reserved **/ - UINT8 Reserved28[50]; + UINT8 Reserved29[50]; /** Offset 0x088D - Enable SATA Port DmVal DITO multiplier. Default is 15. @@ -583,7 +592,7 @@ /** Offset 0x0895 - Reserved **/ - UINT8 Reserved29; + UINT8 Reserved30; /** Offset 0x0896 - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. @@ -592,7 +601,7 @@ /** Offset 0x08A6 - Reserved **/ - UINT8 Reserved30[72]; + UINT8 Reserved31[72]; /** Offset 0x08EE - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. @@ -606,7 +615,27 @@ /** Offset 0x0908 - Reserved **/ - UINT8 Reserved31[456]; + UINT8 Reserved32[16]; + +/** Offset 0x0918 - Enable 8254 Static Clock Gating + Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time + might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support + legacy OS using 8254 timer. Also enable this while S0ix is enabled. + $EN_DIS +**/ + UINT8 Enable8254ClockGating; + +/** Offset 0x0919 - Enable 8254 Static Clock Gating On S3 + This is only applicable when Enable8254ClockGating is disabled. FSP will do the + 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This + avoids the SMI requirement for the programming. + $EN_DIS +**/ + UINT8 Enable8254ClockGatingOnS3; + +/** Offset 0x091A - Reserved +**/ + UINT8 Reserved33[438]; /** Offset 0x0AD0 - RpPtmBytes **/ @@ -614,7 +643,7 @@ /** Offset 0x0AD4 - Reserved **/ - UINT8 Reserved32[101]; + UINT8 Reserved34[101]; /** Offset 0x0B39 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, @@ -632,7 +661,7 @@ /** Offset 0x0B3A - Reserved **/ - UINT8 Reserved33[264]; + UINT8 Reserved35[264]; /** Offset 0x0C42 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. @@ -646,7 +675,7 @@ /** Offset 0x0CA2 - Reserved **/ - UINT8 Reserved34[269]; + UINT8 Reserved36[269]; /** Offset 0x0DAF - LpmStateEnableMask **/ @@ -654,7 +683,7 @@ /** Offset 0x0DB0 - Reserved **/ - UINT8 Reserved35[80]; + UINT8 Reserved37[80]; } FSP_S_CONFIG; /** Fsp S UPD Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/39117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2a08ce73526fb0eb4e7c2a674af78c2913f0a08 Gerrit-Change-Number: 39117 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newchange

9 16

Change in coreboot[master]: soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume
by Subrata Banik (Code Review) 26 Feb '20

26 Feb '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39110 ) Change subject: soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume ...................................................................... soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume This patch makes all legacy 8254 FSP UPDs (Enable8254ClockGating and Enable8254ClockGatingOnS3) depends on CONFIG_USE_LEGACY_8254_TIMER to avoid discrepancy between S0 and S3 resume flow. TEST=Able to boot to TianoCore in both S0 and S3 resume without any hangs and errors. Change-Id: Id6fe74a51537abbb9ff48db925e37a64e5b21f78 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/icelake/fsp_params.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/39110/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index dc4a2a8..f1b8446 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -261,7 +261,7 @@ /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; - params->Enable8254ClockGatingOnS3 = 1; + params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; /* USB */ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 7514be1..334fac8 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -140,7 +140,7 @@ /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; - params->Enable8254ClockGatingOnS3 = 1; + params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; /* S0ix */ params->PchPmSlpS0Enable = config->s0ix_enable; -- To view, visit https://review.coreboot.org/c/coreboot/+/39110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6fe74a51537abbb9ff48db925e37a64e5b21f78 Gerrit-Change-Number: 39110 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

6 8

Change in coreboot[master]: payloads/tianocore: Enable PS2 keyboard module
by Benjamin Doron (Code Review) 26 Feb '20

26 Feb '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38960 ) Change subject: payloads/tianocore: Enable PS2 keyboard module ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/38960/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38960/3//COMMIT_MSG@11 PS3, Line 11: > the payload size is fixed at 4MB uncompressed In builds I've performed, this increased the payload size by a little over 5 KiB (from 701255 to 706674) -- To view, visit https://review.coreboot.org/c/coreboot/+/38960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6d468809142a0049ce1648217d62b070229ad6b Gerrit-Change-Number: 38960 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 26 Feb 2020 02:10:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by Nick Vaccaro (Code Review) 26 Feb '20

26 Feb '20

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38998 ) Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support ...................................................................... Patch Set 15: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/38998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Gerrit-Change-Number: 38998 Gerrit-PatchSet: 15 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 26 Feb 2020 02:02:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by Wonkyu Kim (Code Review) 26 Feb '20

26 Feb '20

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38998 ) Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support ...................................................................... Patch Set 15: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/38998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Gerrit-Change-Number: 38998 Gerrit-PatchSet: 15 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 26 Feb 2020 00:17:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by Srinidhi N Kaushik (Code Review) 26 Feb '20

26 Feb '20

Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38998 ) Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support ...................................................................... Patch Set 15: Code-Review+1 (7 comments) https://review.coreboot.org/c/coreboot/+/38998/13//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38998/13//COMMIT_MSG@13 PS13, Line 13: Upds > UPDs Done https://review.coreboot.org/c/coreboot/+/38998/13/src/mainboard/intel/tglrv… File src/mainboard/intel/tglrvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/38998/13/src/mainboard/intel/tglrv… PS13, Line 48: spd_index = SPD_ID_MICRON; > Why this assignment? default case to chose a more generic/stable spd if we get a board_id not in list. https://review.coreboot.org/c/coreboot/+/38998/13/src/mainboard/intel/tglrv… PS13, Line 49: printk(BIOS_INFO, "Invalid board_id 0x%x\n", board_id); > Sounds more like an error (or at least warning). Done https://review.coreboot.org/c/coreboot/+/38998/13/src/mainboard/intel/tglrv… PS13, Line 51: > Can we add Windows EC case which doesn't report DDR4? […] Will do in the other patch for DDR4 config https://review.coreboot.org/c/coreboot/+/38998/13/src/mainboard/intel/tglrv… PS13, Line 61: if (spd_index == SPD_ADDR_TABLE) { > Variable not needed as only used once? Done https://review.coreboot.org/c/coreboot/+/38998/13/src/mainboard/intel/tglrv… PS13, Line 73: 0 > false Done https://review.coreboot.org/c/coreboot/+/38998/13/src/mainboard/intel/tglrv… File src/mainboard/intel/tglrvp/spd/Makefile.inc: https://review.coreboot.org/c/coreboot/+/38998/13/src/mainboard/intel/tglrv… PS13, Line 22: ifeq ($(SPD_SOURCES),) : SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this) : else > Given that the SPD_SOURCES are set just couple of lines above, this check looks redundant. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/38998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Gerrit-Change-Number: 38998 Gerrit-PatchSet: 15 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 26 Feb 2020 00:13:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by Srinidhi N Kaushik (Code Review) 26 Feb '20

26 Feb '20

Hello Raj Astekar, Patrick Rudolph, Subrata Banik, Nick Vaccaro, Wonkyu Kim, Ravishankar Sarawadi, build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38998 to look at the new patch set (#15). Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support ...................................................................... mb/intel/tglrvp: add Tiger Lake memory initialization support Update memory parameters based on memory type supported by Tiger lake RVP 1. Update dq/dqs mappings 2. Update spd data for Tiger lake LPDDR4 SAMSUNG/MICRON memory 3. Add SPD data bin files for supported memory types 4. Update other FSPM UPDs as part of memory initialization BUG=none BRANCH=none TEST= build tglrvp flash and boot to kernel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e --- M src/mainboard/intel/tglrvp/board_id.h M src/mainboard/intel/tglrvp/romstage_fsp_params.c A src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex M src/mainboard/intel/tglrvp/spd/Makefile.inc A src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex A src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex M src/mainboard/intel/tglrvp/spd/spd.h M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc A src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c 10 files changed, 245 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/38998/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/38998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Gerrit-Change-Number: 38998 Gerrit-PatchSet: 15 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by Srinidhi N Kaushik (Code Review) 26 Feb '20

26 Feb '20

Hello Raj Astekar, Patrick Rudolph, Subrata Banik, Nick Vaccaro, Wonkyu Kim, Ravishankar Sarawadi, build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38998 to look at the new patch set (#14). Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support ...................................................................... mb/intel/tglrvp: add Tiger Lake memory initialization support Update memory parameters based on memory type supported by Tiger lake RVP 1. Update dq/dqs mappings 2. Update spd data for Tiger lake LPDDR4 SAMSUNG/MICRON memory 3. Add SPD data bin files for supported memory types 4. Update other FSPM UPDs as part of memory initialization BUG=none BRANCH=none TEST= build tglrvp flash and boot to kernel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e --- M src/mainboard/intel/tglrvp/board_id.h M src/mainboard/intel/tglrvp/romstage_fsp_params.c A src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex M src/mainboard/intel/tglrvp/spd/Makefile.inc A src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex A src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex M src/mainboard/intel/tglrvp/spd/spd.h M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc A src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c 10 files changed, 245 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/38998/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/38998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Gerrit-Change-Number: 38998 Gerrit-PatchSet: 14 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: lib/malloc: Implement a simple free() only for last malloc()
by Anil Kumar K (Code Review) 26 Feb '20

26 Feb '20

Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37919 ) Change subject: lib/malloc: Implement a simple free() only for last malloc() ...................................................................... Patch Set 11: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/37919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d43cf54b79e6897cf6882335730b2310e4eae45 Gerrit-Change-Number: 37919 Gerrit-PatchSet: 11 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 25 Feb 2020 23:10:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by Srinidhi N Kaushik (Code Review) 25 Feb '20

25 Feb '20

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2020