coreboot-gerrit February 2020

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Change in coreboot[master]: superio/aspeed/ast2400: drop non-onetime-config registers for iLPC2AHB
by Patrick Georgi (Code Review) 25 Feb '20

25 Feb '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39093 ) Change subject: superio/aspeed/ast2400: drop non-onetime-config registers for iLPC2AHB ...................................................................... superio/aspeed/ast2400: drop non-onetime-config registers for iLPC2AHB The specified PNP registers PNP_MSC0-E (F0-FE) are part of the iLPC2AHB bridge's index/value interface. They are no one-time config registers so we can't specify a sane value in the devicetree. Thus, drop them to stop coreboot from complaining about the missing entries. Change-Id: I7d7f16845c755592317f140cca66cca12032f7a6 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39093 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/superio/aspeed/ast2400/superio.c 1 file changed, 1 insertion(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Patrick Rudolph: Looks good to me, approved diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c index a3d92c2..4867f6e 100644 --- a/src/superio/aspeed/ast2400/superio.c +++ b/src/superio/aspeed/ast2400/superio.c @@ -82,10 +82,7 @@ { NULL, AST2400_GPIO, PNP_IRQ0, }, // GPIO LDN has no IO Region { NULL, AST2400_SUART3, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, }, { NULL, AST2400_SUART4, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, }, - { NULL, AST2400_ILPC2AHB, PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2 - | PNP_MSC3 | PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7 - | PNP_MSC8 | PNP_MSC9 | PNP_MSCA | PNP_MSCB | PNP_MSCC - | PNP_MSCD | PNP_MSCE, }, + { NULL, AST2400_ILPC2AHB, PNP_IRQ0 }, { NULL, AST2400_MAILBOX, PNP_IO0 | PNP_IRQ0, 0xfffe, }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/39093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d7f16845c755592317f140cca66cca12032f7a6 Gerrit-Change-Number: 39093 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/supermicro/x11-lga1151-series: fix GPIO reset mapping
by Patrick Georgi (Code Review) 25 Feb '20

25 Feb '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39090 ) Change subject: mb/supermicro/x11-lga1151-series: fix GPIO reset mapping ...................................................................... mb/supermicro/x11-lga1151-series: fix GPIO reset mapping When specifying _PAD_CFG_STRUCT with raw hex values, a logical reset value of 0x0 is only defined for GPD pads. For any other GPIOs this maps to 0x3. On the Supermicro X11 boards a value of 0x0 is set for GPP_D22 and GPP_F23, triggering the error "gpio_pad_reset_config_override: Logical to Chipset mapping not found". Set the right value (0x3<<30) for the affected GPIOs. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I3ae17dfc4d90f88f5b8bc5bee49740745778a91a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39090 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h 2 files changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h index 83fb22d..3eeef29 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h @@ -114,7 +114,7 @@ /* GPIO */ _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D22, 0x04000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D22, 0xc4000102, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000000), /* SATAXPCIE0 */ _PAD_CFG_STRUCT(GPP_E0, 0x44000502, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000000), @@ -152,7 +152,7 @@ /* GPIO */ _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0x04000200, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0xc4000200, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_G2, 0x44000102, 0x00000000), diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h index 6a25128..d27e234 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h @@ -125,7 +125,7 @@ _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000010), /* GPIO */ _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000010), /* GPIO */ _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D22, 0x04000100, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D22, 0xc4000100, 0x00000010), /* GPIO */ _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000010), /* GPIO */ /* GPIO Group GPP_E */ @@ -167,7 +167,7 @@ _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000010), /* GPIO */ _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000010), /* GPIO */ _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F23, 0x04000200, 0x00000010), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F23, 0xc4000200, 0x00000010), /* GPIO */ /* GPIO Group GPP_G */ _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000010), /* GPIO */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ae17dfc4d90f88f5b8bc5bee49740745778a91a Gerrit-Change-Number: 39090 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek: Fix typos in comments
by HAOUAS Elyes (Code Review) 25 Feb '20

25 Feb '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39027 ) Change subject: soc/mediatek: Fix typos in comments ...................................................................... soc/mediatek: Fix typos in comments Also add missing whitespace. Change-Id: I3361122d5232072e68d018e84219a262acf34001 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/mediatek/common/include/soc/pmic_wrap_common.h M src/soc/mediatek/mt8173/dramc_pi_basic_api.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/mediatek/mt8173/emi.c M src/soc/mediatek/mt8173/include/soc/pmic_wrap.h M src/soc/mediatek/mt8173/mt6391.c M src/soc/mediatek/mt8183/spm.c 7 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/39027/1 diff --git a/src/soc/mediatek/common/include/soc/pmic_wrap_common.h b/src/soc/mediatek/common/include/soc/pmic_wrap_common.h index 0b9f2d3..bf64164 100644 --- a/src/soc/mediatek/common/include/soc/pmic_wrap_common.h +++ b/src/soc/mediatek/common/include/soc/pmic_wrap_common.h @@ -69,7 +69,7 @@ return pwrap_wacs2(1, addr, wdata, 0, 0); } -/* dewrapper defaule value */ +/* dewrapper default value */ enum { DEFAULT_VALUE_READ_TEST = 0x5aa5, WRITE_TEST_VALUE = 0xa55a @@ -81,7 +81,7 @@ TIMEOUT_WAIT_IDLE_US = 255 }; -/* manual commnd */ +/* manual command */ enum { OP_WR = 0x1, OP_CSH = 0x0, diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index 58dce72..4fafb04 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -450,7 +450,7 @@ mrs_write(channel, rank, sdram_params->mrs_set.mrs_63, 10); /* MR10 -> ZQ Init, tZQINIT>=1us */ mrs_write(channel, rank, sdram_params->mrs_set.mrs_10, 1); - /* MR3 driving stregth set to max */ + /* MR3 driving strength set to max */ mrs_write(channel, rank, sdram_params->mrs_set.mrs_3, 1); /* MR1 */ mrs_write(channel, rank, sdram_params->mrs_set.mrs_1, 1); diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index 492238a..f6c866b 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -971,9 +971,9 @@ dqdqs_perbit_dly[i].best_last_dqsdly_pass = -2; } - /* 1. delay DQ,find the pass widnow (left boundary) + /* 1. delay DQ,find the pass window (left boundary) * 2. delay DQS find the pass window (right boundary) - * 3. find the best DQ / DQS to satify the middle value + * 3. find the best DQ / DQS to satisfy the middle value * of the overall pass window per bit * 4. set DQS delay to the max per byte, delay DQ to de-skew */ diff --git a/src/soc/mediatek/mt8173/emi.c b/src/soc/mediatek/mt8173/emi.c index f3ea761..d97b4d6 100644 --- a/src/soc/mediatek/mt8173/emi.c +++ b/src/soc/mediatek/mt8173/emi.c @@ -148,7 +148,7 @@ 9; /* check if row address */ - /*00 is 13 bits, 01 is 14 bits, 10 is 15bits, 11 is 16 bits */ + /* 00 is 13 bits, 01 is 14 bits, 10 is 15bits, 11 is 16 bits */ bit_counter += ((value & ROW_ADDR_BITS_MASK) >> ROW_ADDR_BITS_SHIFT) + 13; @@ -159,7 +159,7 @@ /* add bank address bit, LPDDR3 is 8 banks =2^3 */ bit_counter += 3; - /*transfor bits to bytes */ + /* transfer bits to bytes */ return ((size_t)1 << (bit_counter - 3)); } diff --git a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h index 3687a29..d6c58a5 100644 --- a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h +++ b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h @@ -125,7 +125,7 @@ check_member(mt8173_pwrap_regs, dcm_dbc_prd, 0x148); -/* dewrapper regsister */ +/* dewrapper register */ enum { DEW_EVENT_OUT_EN = DEW_BASE + 0x0, DEW_DIO_EN = DEW_BASE + 0x2, diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c index 2656d72..3f77c8a 100644 --- a/src/soc/mediatek/mt8173/mt6391.c +++ b/src/soc/mediatek/mt8173/mt6391.c @@ -201,7 +201,7 @@ pwrap_write_field(PMIC_RG_VSRMCA15_CON8, 0x17, 0x7F, 0); /* [6:0]: VSRMCA15_VOSEL_SLEEP; Sleep mode setting on */ pwrap_write_field(PMIC_RG_VSRMCA15_CON11, 0x00, 0x7F, 0); - /* [8:8]: VSRMCA15_VSLEEP_EN; set sleep mode referenc */ + /* [8:8]: VSRMCA15_VSLEEP_EN; set sleep mode reference */ pwrap_write_field(PMIC_RG_VSRMCA15_CON18, 0x1, 0x1, 8); /* [5:4]: VSRMCA15_VOSEL_TRANS_EN; rising & falling e */ pwrap_write_field(PMIC_RG_VSRMCA15_CON18, 0x3, 0x3, 4); @@ -359,7 +359,7 @@ pwrap_write_field(PMIC_RG_VDRM_CON9, 0x43, 0x7F, 0); pwrap_write_field(PMIC_RG_VDRM_CON10, 0x43, 0x7F, 0); - /* 26M clock amplitute adjust */ + /* 26M clock amplitude adjust */ pwrap_write_field(PMIC_RG_DCXO_ANALOG_CON1, 0x0, 0x3, 2); pwrap_write_field(PMIC_RG_DCXO_ANALOG_CON1, 0x1, 0x3, 11); diff --git a/src/soc/mediatek/mt8183/spm.c b/src/soc/mediatek/mt8183/spm.c index 024fe1c..020da93 100644 --- a/src/soc/mediatek/mt8183/spm.c +++ b/src/soc/mediatek/mt8183/spm.c @@ -274,7 +274,7 @@ offset += copy_size; /* version */ - /* The termintating character should be contained in the spm binary */ + /* The terminating character should be contained in the spm binary */ assert(spm_bin[file_size - 1] == '\0'); assert(offset < file_size); printk(BIOS_DEBUG, "SPM: version = %s\n", spm_bin + offset); -- To view, visit https://review.coreboot.org/c/coreboot/+/39027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3361122d5232072e68d018e84219a262acf34001 Gerrit-Change-Number: 39027 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: commonlib/timestamp_serialized.h: Drop outdated remark
by Angel Pons (Code Review) 25 Feb '20

25 Feb '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39084 ) Change subject: commonlib/timestamp_serialized.h: Drop outdated remark ...................................................................... commonlib/timestamp_serialized.h: Drop outdated remark The timestamps for decompression have been relevant on x86 for a very long time. Henceforth, eliminate the `(ignore for x86)` remarks. Change-Id: I924e4e2dbb07db49408c77be8f3de59f8c3a8f00 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/commonlib/include/commonlib/timestamp_serialized.h 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/39084/1 diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index d7d636e..964efd5 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -168,10 +168,10 @@ { TS_END_BOOTBLOCK, "end of bootblock" }, { TS_START_COPYROM, "starting to load romstage" }, { TS_END_COPYROM, "finished loading romstage" }, - { TS_START_ULZMA, "starting LZMA decompress (ignore for x86)" }, - { TS_END_ULZMA, "finished LZMA decompress (ignore for x86)" }, - { TS_START_ULZ4F, "starting LZ4 decompress (ignore for x86)" }, - { TS_END_ULZ4F, "finished LZ4 decompress (ignore for x86)" }, + { TS_START_ULZMA, "starting LZMA decompress" }, + { TS_END_ULZMA, "finished LZMA decompress" }, + { TS_START_ULZ4F, "starting LZ4 decompress" }, + { TS_END_ULZ4F, "finished LZ4 decompress" }, { TS_DEVICE_ENUMERATE, "device enumeration" }, { TS_DEVICE_CONFIGURE, "device configuration" }, { TS_DEVICE_ENABLE, "device enable" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/39084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I924e4e2dbb07db49408c77be8f3de59f8c3a8f00 Gerrit-Change-Number: 39084 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: lib/lzma: Fix out-of-bounds read
by Alexandre Rebert (Code Review) 25 Feb '20

25 Feb '20

Alexandre Rebert has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39085 ) Change subject: lib/lzma: Fix out-of-bounds read ...................................................................... lib/lzma: Fix out-of-bounds read Fix an out-of-bounds read in the LZMA decoder which happens when the src buffer is too small to contain the 13-byte LZMA header. Change-Id: Id5893e60fc9a48deb83560b7917f5558cd30ef4e Signed-off-by: Alex Rebert <alexandre.rebert(a)gmail.com> Found-by: Mayhem --- M src/lib/lzma.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/39085/1 diff --git a/src/lib/lzma.c b/src/lib/lzma.c index 71c016e..16b6e22 100644 --- a/src/lib/lzma.c +++ b/src/lib/lzma.c @@ -29,6 +29,11 @@ MAYBE_STATIC_BSS unsigned char scratchpad[15980]; const unsigned char *cp; + if (srcn < data_offset) { + printk(BIOS_WARNING, "lzma: Input too small.\n"); + return 0; + } + memcpy(properties, src, LZMA_PROPERTIES_SIZE); /* The outSize in LZMA stream is a 64bit integer stored in little-endian * (ref: lzma.cc@LZMACompress: put_64). To prevent accessing by -- To view, visit https://review.coreboot.org/c/coreboot/+/39085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5893e60fc9a48deb83560b7917f5558cd30ef4e Gerrit-Change-Number: 39085 Gerrit-PatchSet: 1 Gerrit-Owner: Alexandre Rebert <alexandre.rebert(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/intel/common: Update Jasperlake Device IDs
by Meera Ravindranath (Code Review) 25 Feb '20

25 Feb '20

Hello Varshit B Pandya, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38849 to review the following change. Change subject: soc/intel/common: Update Jasperlake Device IDs ...................................................................... soc/intel/common: Update Jasperlake Device IDs Update Jasperlake CPU, SA and PCH IDs Change-Id: I2c9ec1eb4236184b981d99250f263172c82f7117 Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Signed-off-by: Varshit Pandya <varshit.b.pandya(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/mmc.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/tigerlake/bootblock/report_platform.c 22 files changed, 100 insertions(+), 72 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38849/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index e117ac2..cfd511e 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2809,8 +2809,6 @@ #define PCI_DEVICE_ID_INTEL_TGP_ESPI_24 0xA09D #define PCI_DEVICE_ID_INTEL_TGP_ESPI_25 0xA09E #define PCI_DEVICE_ID_INTEL_TGP_ESPI_26 0xA09F -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1 0x3887 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2 0x4d80 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_0 0x4b00 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_1 0x4b04 #define PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI 0x4b03 @@ -2819,6 +2817,7 @@ #define PCI_DEVICE_ID_INTEL_MCC_ESPI_2 0x4b05 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_3 0x4b06 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_4 0x4b07 +#define PCI_DEVICE_ID_INTEL_JSP_ESPI_7 0X4d87 /* Intel PCIE device ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10 @@ -3014,6 +3013,7 @@ #define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP14 0x02b5 #define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP15 0x02b6 #define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP16 0x02b7 + #define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP1 0x06b8 #define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP2 0x06b9 #define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP3 0x06ba @@ -3038,14 +3038,15 @@ #define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP22 0x06ad #define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP23 0x06ae #define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP24 0x06af -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP1 0x38b8 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP2 0x38b9 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP3 0x38ba -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP4 0x38bb -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP5 0x38bc -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP6 0x38bd -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP7 0x38be -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP8 0x38bf + +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP1 0x4db8 +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP2 0x4db9 +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP3 0x4dba +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP4 0x4dbb +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP5 0x4dbc +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP6 0x4dbd +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP7 0x4dbe +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP8 0x4dbf #define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP1 0x4b38 #define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP2 0x4b39 @@ -3089,8 +3090,8 @@ #define PCI_DEVICE_ID_INTEL_TGP_SATA 0xa0d5 #define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA 0xa0d7 #define PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA 0x282a -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SATA 0x38d3 #define PCI_DEVICE_ID_INTEL_MCC_AHCI_SATA 0x4b60 +#define PCI_DEVICE_ID_INTEL_JSP_SATA 0x4dd3 /* Intel PMC device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21 @@ -3106,8 +3107,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_PMC 0x02a1 #define PCI_DEVICE_ID_INTEL_CMP_H_PMC 0x06a1 #define PCI_DEVICE_ID_INTEL_TGP_PMC 0xa0a1 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PMC 0x38a1 #define PCI_DEVICE_ID_INTEL_MCC_PMC 0x4b21 +#define PCI_DEVICE_ID_INTEL_JSP_PMC 0x4da1 /* Intel I2C device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60 @@ -3178,12 +3179,13 @@ #define PCI_DEVICE_ID_INTEL_MCC_I2C5 0x4b4c #define PCI_DEVICE_ID_INTEL_MCC_I2C6 0x4b44 #define PCI_DEVICE_ID_INTEL_MCC_I2C7 0x4b45 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C0 0x38e8 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C1 0x38e9 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C2 0x38ea -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C3 0x38eb -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C4 0x38c5 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C5 0x38c6 + +#define PCI_DEVICE_ID_INTEL_JSP_I2C0 0x4de8 +#define PCI_DEVICE_ID_INTEL_JSP_I2C1 0x4de9 +#define PCI_DEVICE_ID_INTEL_JSP_I2C2 0x4dea +#define PCI_DEVICE_ID_INTEL_JSP_I2C3 0x4deb +#define PCI_DEVICE_ID_INTEL_JSP_I2C4 0x4dc5 +#define PCI_DEVICE_ID_INTEL_JSP_I2C5 0x4dc6 /* Intel UART device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27 @@ -3224,9 +3226,9 @@ #define PCI_DEVICE_ID_INTEL_MCC_UART0 0x4b28 #define PCI_DEVICE_ID_INTEL_MCC_UART1 0x4b29 #define PCI_DEVICE_ID_INTEL_MCC_UART2 0x4b4d -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART0 0x38a8 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART1 0x38a9 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART2 0x38c7 +#define PCI_DEVICE_ID_INTEL_JSP_UART0 0x4da8 +#define PCI_DEVICE_ID_INTEL_JSP_UART1 0x4da9 +#define PCI_DEVICE_ID_INTEL_JSP_UART2 0x4dc7 /* Intel SPI device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24 @@ -3273,10 +3275,10 @@ #define PCI_DEVICE_ID_INTEL_MCC_GSPI0 0x4b2a #define PCI_DEVICE_ID_INTEL_MCC_GSPI1 0x4b2b #define PCI_DEVICE_ID_INTEL_MCC_GSPI2 0x4b37 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI0 0x38aa -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI1 0x38ab -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI2 0x38fb -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_HWSEQ_SPI 0x38a4 +#define PCI_DEVICE_ID_INTEL_JSP_SPI0 0x4daa +#define PCI_DEVICE_ID_INTEL_JSP_SPI1 0x4dab +#define PCI_DEVICE_ID_INTEL_JSP_SPI2 0x4dfb +#define PCI_DEVICE_ID_INTEL_JSP_HWSEQ_SPI 0x4da4 /* Intel IGD device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_GT1F_DT2 0x1902 @@ -3387,7 +3389,10 @@ #define PCI_DEVICE_ID_INTEL_EHL_GT2_2 0x4550 #define PCI_DEVICE_ID_INTEL_EHL_GT1_3 0x4571 #define PCI_DEVICE_ID_INTEL_EHL_GT2_3 0x4570 -#define PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0 0x4569 +#define PCI_DEVICE_ID_INTEL_JSL_GT8 0x4E41 +#define PCI_DEVICE_ID_INTEL_JSL_GT16 0x4E51 +#define PCI_DEVICE_ID_INTEL_JSL_GT32 0x4E71 +#define PCI_DEVICE_ID_INTEL_JSL_NOGT 0x4E69 /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 @@ -3446,9 +3451,12 @@ #define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14 #define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12 #define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A10 -#define PCI_DEVICE_ID_INTEL_JSL_PRE_PROD 0x4e2a #define PCI_DEVICE_ID_INTEL_JSL_EHL 0x4532 #define PCI_DEVICE_ID_INTEL_EHL_ID_1 0x4510 +#define PCI_DEVICE_ID_INTEL_JSL_ID_Y 0x4510 +#define PCI_DEVICE_ID_INTEL_JSL_1 0x4532 +#define PCI_DEVICE_ID_INTEL_JSL_2 0x4518 +#define PCI_DEVICE_ID_INTEL_JSP_SA 0x4e22 /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 @@ -3461,8 +3469,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_SMBUS 0x02a3 #define PCI_DEVICE_ID_INTEL_CMP_H_SMBUS 0x06a3 #define PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS 0xa0a3 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SMBUS 0x38a3 #define PCI_DEVICE_ID_INTEL_MCC_SMBUS 0x4b23 +#define PCI_DEVICE_ID_INTEL_JSP_SMBUS 0x4da3 /* Intel XHCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 @@ -3478,8 +3486,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_LP_XHCI 0x02ed #define PCI_DEVICE_ID_INTEL_CMP_H_XHCI 0x06ed #define PCI_DEVICE_ID_INTEL_TGP_LP_XHCI 0xa0ed -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_XHCI 0x38ed #define PCI_DEVICE_ID_INTEL_MCC_XHCI 0x4b7d +#define PCI_DEVICE_ID_INTEL_JSP_XHCI 0x4ded /* Intel P2SB device Ids */ #define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92 @@ -3495,8 +3503,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_P2SB 0x02a0 #define PCI_DEVICE_ID_INTEL_CMP_H_P2SB 0x06a0 #define PCI_DEVICE_ID_INTEL_TGL_P2SB 0xa0a0 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_P2SB 0x38a0 #define PCI_DEVICE_ID_INTEL_EHL_P2SB 0x4b20 +#define PCI_DEVICE_ID_INTEL_JSP_P2SB 0x4da0 /* Intel SRAM device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec @@ -3507,8 +3515,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_SRAM 0x02ef #define PCI_DEVICE_ID_INTEL_CMP_H_SRAM 0x06ef #define PCI_DEVICE_ID_INTEL_TGL_SRAM 0xa0ef -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SRAM 0x38ef #define PCI_DEVICE_ID_INTEL_MCC_SRAM 0x4b7f +#define PCI_DEVICE_ID_INTEL_JSP_SRAM 0x4def /* Intel AUDIO device Ids */ #define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98 @@ -3525,8 +3533,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_H_AUDIO 0x06c8 #define PCI_DEVICE_ID_INTEL_BSW_AUDIO 0x2284 #define PCI_DEVICE_ID_INTEL_TGL_AUDIO 0xa0c8 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_AUDIO 0x38c8 #define PCI_DEVICE_ID_INTEL_MCC_AUDIO 0x4b55 +#define PCI_DEVICE_ID_INTEL_JSP_AUDIO 0x4dc8 /* Intel HECI/ME device Ids */ #define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a @@ -3544,11 +3552,14 @@ #define PCI_DEVICE_ID_INTEL_CMP_CSE0 0x02e0 #define PCI_DEVICE_ID_INTEL_CMP_H_CSE0 0x06e0 #define PCI_DEVICE_ID_INTEL_TGL_CSE0 0xa0e0 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_CSE0 0x38e0 #define PCI_DEVICE_ID_INTEL_MCC_CSE0 0x4b70 #define PCI_DEVICE_ID_INTEL_MCC_CSE1 0x4b71 #define PCI_DEVICE_ID_INTEL_MCC_CSE2 0x4b74 #define PCI_DEVICE_ID_INTEL_MCC_CSE3 0x4b75 +#define PCI_DEVICE_ID_INTEL_JSP_CSE0 0x4de0 +#define PCI_DEVICE_ID_INTEL_JSP_CSE1 0x4de1 +#define PCI_DEVICE_ID_INTEL_JSP_CSE2 0x4de4 +#define PCI_DEVICE_ID_INTEL_JSP_CSE3 0x4de5 /* Intel XDCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa @@ -3561,6 +3572,7 @@ #define PCI_DEVICE_ID_INTEL_CMP_H_XDCI 0x06ee #define PCI_DEVICE_ID_INTEL_TGP_LP_XDCI 0xa0ee #define PCI_DEVICE_ID_INTEL_MCC_XDCI 0x4b7e +#define PCI_DEVICE_ID_INTEL_JSP_XDCI 0x4dee /* Intel SD device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca @@ -3571,12 +3583,13 @@ #define PCI_DEVICE_ID_INTEL_ICL_SD 0x34f8 #define PCI_DEVICE_ID_INTEL_CMP_SD 0x02f5 #define PCI_DEVICE_ID_INTEL_CMP_H_SD 0x06f5 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SD 0x38f8 #define PCI_DEVICE_ID_INTEL_MCC_SD 0x4b48 +#define PCI_DEVICE_ID_INTEL_JSP_SD 0x4df8 /* Intel EMMC device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_EMMC 0x9d2b #define PCI_DEVICE_ID_INTEL_CMP_EMMC 0x02c4 +#define PCI_DEVICE_ID_INTEL_JSP_EMMC 0x4dc4 /* Intel WIFI Ids */ #define PCI_DEVICE_ID_1000_SERIES_WIFI 0x0084 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 66a358f..62f2d1f 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -87,6 +87,7 @@ { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_Q0_P1 }, { X86_VENDOR_INTEL, CPUID_TIGERLAKE_A0 }, { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_A0 }, + { X86_VENDOR_INTEL, CPUID_JASPERLAKE}, { 0, 0 }, }; diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index c82f3bd..9005266 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -756,11 +756,14 @@ PCI_DEVICE_ID_INTEL_CMP_CSE0, PCI_DEVICE_ID_INTEL_CMP_H_CSE0, PCI_DEVICE_ID_INTEL_TGL_CSE0, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_CSE0, PCI_DEVICE_ID_INTEL_MCC_CSE0, PCI_DEVICE_ID_INTEL_MCC_CSE1, PCI_DEVICE_ID_INTEL_MCC_CSE2, PCI_DEVICE_ID_INTEL_MCC_CSE3, + PCI_DEVICE_ID_INTEL_JSP_CSE0, + PCI_DEVICE_ID_INTEL_JSP_CSE1, + PCI_DEVICE_ID_INTEL_JSP_CSE2, + PCI_DEVICE_ID_INTEL_JSP_CSE3, 0, }; diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 78f43a0..dc21b8e 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -36,8 +36,8 @@ PCI_DEVICE_ID_INTEL_CMP_H_AUDIO, PCI_DEVICE_ID_INTEL_ICL_AUDIO, PCI_DEVICE_ID_INTEL_TGL_AUDIO, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_AUDIO, PCI_DEVICE_ID_INTEL_MCC_AUDIO, + PCI_DEVICE_ID_INTEL_JSP_AUDIO, 0, }; diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 6c1436a..8d8445c 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -219,13 +219,16 @@ PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, - PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0, PCI_DEVICE_ID_INTEL_EHL_GT1_1, PCI_DEVICE_ID_INTEL_EHL_GT2_1, PCI_DEVICE_ID_INTEL_EHL_GT1_2, PCI_DEVICE_ID_INTEL_EHL_GT2_2, PCI_DEVICE_ID_INTEL_EHL_GT1_3, PCI_DEVICE_ID_INTEL_EHL_GT2_3, + PCI_DEVICE_ID_INTEL_JSL_GT8, + PCI_DEVICE_ID_INTEL_JSL_GT16, + PCI_DEVICE_ID_INTEL_JSL_GT32, + PCI_DEVICE_ID_INTEL_JSL_NOGT, 0, }; diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index ca854a9..57dad62 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -249,12 +249,6 @@ PCI_DEVICE_ID_INTEL_TGP_I2C5, PCI_DEVICE_ID_INTEL_TGP_I2C6, PCI_DEVICE_ID_INTEL_TGP_I2C7, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C0, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C1, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C2, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C3, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C4, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C5, PCI_DEVICE_ID_INTEL_MCC_I2C0, PCI_DEVICE_ID_INTEL_MCC_I2C1, PCI_DEVICE_ID_INTEL_MCC_I2C2, @@ -263,6 +257,12 @@ PCI_DEVICE_ID_INTEL_MCC_I2C5, PCI_DEVICE_ID_INTEL_MCC_I2C6, PCI_DEVICE_ID_INTEL_MCC_I2C7, + PCI_DEVICE_ID_INTEL_JSP_I2C0, + PCI_DEVICE_ID_INTEL_JSP_I2C1, + PCI_DEVICE_ID_INTEL_JSP_I2C2, + PCI_DEVICE_ID_INTEL_JSP_I2C3, + PCI_DEVICE_ID_INTEL_JSP_I2C4, + PCI_DEVICE_ID_INTEL_JSP_I2C5, 0, }; diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index c0c58af..5d32068 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -46,6 +46,7 @@ #define CPUID_COFFEELAKE_R0 0x906ed #define CPUID_ICELAKE_A0 0x706e0 #define CPUID_ICELAKE_B0 0x706e1 +#define CPUID_JASPERLAKE 0x906c0 #define CPUID_COMETLAKE_U_A0 0xa0660 #define CPUID_COMETLAKE_U_K0_S0 0xa0661 #define CPUID_COMETLAKE_H_S_6_2_G0 0xa0650 diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index af90df6..8690e7c 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -231,8 +231,6 @@ PCI_DEVICE_ID_INTEL_TGP_ESPI_24, PCI_DEVICE_ID_INTEL_TGP_ESPI_25, PCI_DEVICE_ID_INTEL_TGP_ESPI_26, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2, PCI_DEVICE_ID_INTEL_MCC_ESPI_0, PCI_DEVICE_ID_INTEL_MCC_ESPI_1, PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI, @@ -241,6 +239,7 @@ PCI_DEVICE_ID_INTEL_MCC_ESPI_2, PCI_DEVICE_ID_INTEL_MCC_ESPI_3, PCI_DEVICE_ID_INTEL_MCC_ESPI_4, + PCI_DEVICE_ID_INTEL_JSP_ESPI_7, 0 }; diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 34b6e06..89b5dd4 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -181,8 +181,8 @@ PCI_DEVICE_ID_INTEL_CMP_P2SB, PCI_DEVICE_ID_INTEL_CMP_H_P2SB, PCI_DEVICE_ID_INTEL_TGL_P2SB, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_P2SB, PCI_DEVICE_ID_INTEL_EHL_P2SB, + PCI_DEVICE_ID_INTEL_JSP_P2SB, 0, }; diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index eab6667..cc20a48 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -290,14 +290,6 @@ PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP14, PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP15, PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP16, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP1, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP2, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP3, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP4, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP5, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP6, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP7, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP8, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP1, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP2, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP3, @@ -305,6 +297,14 @@ PCI_DEVICE_ID_INTEL_MCC_PCIE_RP5, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP6, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP7, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP1, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP2, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP3, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP4, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP5, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP6, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP7, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP8, 0 }; diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 3a9431b..ba64063 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -135,8 +135,8 @@ PCI_DEVICE_ID_INTEL_CMP_PMC, PCI_DEVICE_ID_INTEL_CMP_H_PMC, PCI_DEVICE_ID_INTEL_TGP_PMC, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PMC, PCI_DEVICE_ID_INTEL_MCC_PMC, + PCI_DEVICE_ID_INTEL_JSP_PMC, 0 }; diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index cb12ad3..69e66d8 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -103,8 +103,8 @@ PCI_DEVICE_ID_INTEL_TGP_SATA, PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA, PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SATA, PCI_DEVICE_ID_INTEL_MCC_AHCI_SATA, + PCI_DEVICE_ID_INTEL_JSP_SATA, 0 }; diff --git a/src/soc/intel/common/block/scs/mmc.c b/src/soc/intel/common/block/scs/mmc.c index 4ff3ac5..bbdde39 100644 --- a/src/soc/intel/common/block/scs/mmc.c +++ b/src/soc/intel/common/block/scs/mmc.c @@ -85,6 +85,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_EMMC, + PCI_DEVICE_ID_INTEL_JSP_EMMC, 0 }; diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c index 6b360d5..3f036e9 100644 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -74,8 +74,8 @@ PCI_DEVICE_ID_INTEL_ICL_SD, PCI_DEVICE_ID_INTEL_CMP_SD, PCI_DEVICE_ID_INTEL_CMP_H_SD, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SD, PCI_DEVICE_ID_INTEL_MCC_SD, + PCI_DEVICE_ID_INTEL_JSP_SD, 0 }; diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 44b2165..d647cf8 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -97,8 +97,8 @@ PCI_DEVICE_ID_INTEL_CMP_SMBUS, PCI_DEVICE_ID_INTEL_CMP_H_SMBUS, PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SMBUS, PCI_DEVICE_ID_INTEL_MCC_SMBUS, + PCI_DEVICE_ID_INTEL_JSP_SMBUS, 0 }; diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 95981be..51ac697 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -93,14 +93,14 @@ PCI_DEVICE_ID_INTEL_TGP_GSPI4, PCI_DEVICE_ID_INTEL_TGP_GSPI5, PCI_DEVICE_ID_INTEL_TGP_GSPI6, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI0, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI1, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI2, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_HWSEQ_SPI, PCI_DEVICE_ID_INTEL_MCC_SPI0, PCI_DEVICE_ID_INTEL_MCC_GSPI0, PCI_DEVICE_ID_INTEL_MCC_GSPI1, PCI_DEVICE_ID_INTEL_MCC_GSPI2, + PCI_DEVICE_ID_INTEL_JSP_SPI0, + PCI_DEVICE_ID_INTEL_JSP_SPI1, + PCI_DEVICE_ID_INTEL_JSP_SPI2, + PCI_DEVICE_ID_INTEL_JSP_HWSEQ_SPI, 0 }; diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index 6498d40..bfbacea 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -53,8 +53,8 @@ PCI_DEVICE_ID_INTEL_CMP_SRAM, PCI_DEVICE_ID_INTEL_CMP_H_SRAM, PCI_DEVICE_ID_INTEL_TGL_SRAM, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SRAM, PCI_DEVICE_ID_INTEL_MCC_SRAM, + PCI_DEVICE_ID_INTEL_JSP_SRAM, 0, }; diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 4c7d8c8..1f75534 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -399,9 +399,12 @@ PCI_DEVICE_ID_INTEL_TGL_ID_U, PCI_DEVICE_ID_INTEL_TGL_ID_U_1, PCI_DEVICE_ID_INTEL_TGL_ID_Y, - PCI_DEVICE_ID_INTEL_JSL_PRE_PROD, PCI_DEVICE_ID_INTEL_JSL_EHL, PCI_DEVICE_ID_INTEL_EHL_ID_1, + PCI_DEVICE_ID_INTEL_JSL_ID_Y, + PCI_DEVICE_ID_INTEL_JSL_1, + PCI_DEVICE_ID_INTEL_JSL_2, + PCI_DEVICE_ID_INTEL_JSP_SA, 0 }; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 08c0090..6f027e7 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -281,12 +281,12 @@ PCI_DEVICE_ID_INTEL_TGP_UART0, PCI_DEVICE_ID_INTEL_TGP_UART1, PCI_DEVICE_ID_INTEL_TGP_UART2, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART0, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART1, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART2, PCI_DEVICE_ID_INTEL_MCC_UART0, PCI_DEVICE_ID_INTEL_MCC_UART1, PCI_DEVICE_ID_INTEL_MCC_UART2, + PCI_DEVICE_ID_INTEL_JSP_UART0, + PCI_DEVICE_ID_INTEL_JSP_UART1, + PCI_DEVICE_ID_INTEL_JSP_UART2, 0, }; diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 5b70f9d..ff43201 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -46,6 +46,7 @@ PCI_DEVICE_ID_INTEL_CMP_H_XDCI, PCI_DEVICE_ID_INTEL_TGP_LP_XDCI, PCI_DEVICE_ID_INTEL_MCC_XDCI, + PCI_DEVICE_ID_INTEL_JSP_XDCI, 0 }; diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 4b8a5cc..e4f98eb 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -133,8 +133,8 @@ PCI_DEVICE_ID_INTEL_CMP_LP_XHCI, PCI_DEVICE_ID_INTEL_CMP_H_XHCI, PCI_DEVICE_ID_INTEL_TGP_LP_XHCI, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_XHCI, PCI_DEVICE_ID_INTEL_MCC_XHCI, + PCI_DEVICE_ID_INTEL_JSP_XHCI, 0 }; diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index 127994d..3246219 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -38,6 +38,7 @@ const char *name; } cpu_table[] = { { CPUID_TIGERLAKE_A0, "Tigerlake A0" }, + { CPUID_JASPERLAKE, "Jasperlake" }, }; static struct { @@ -47,7 +48,7 @@ { PCI_DEVICE_ID_INTEL_TGL_ID_U, "Tigerlake-U-4-2" }, { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" }, { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" }, - { PCI_DEVICE_ID_INTEL_JSL_PRE_PROD, "Jasperlake Pre Prod" }, + { PCI_DEVICE_ID_INTEL_JSP_SA, "Jasperlake" }, { PCI_DEVICE_ID_INTEL_JSL_EHL, "Jasperlake Elkhartlake" }, { PCI_DEVICE_ID_INTEL_EHL_ID_1, "Elkhartlake-1" }, }; @@ -88,8 +89,7 @@ { PCI_DEVICE_ID_INTEL_TGP_ESPI_24, "Tigerlake-Base SKU" }, { PCI_DEVICE_ID_INTEL_TGP_ESPI_25, "Tigerlake-Base SKU" }, { PCI_DEVICE_ID_INTEL_TGP_ESPI_26, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1, "Jasperlake Pre Prod" }, - { PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2, "Jasperlake Pre Prod" }, + { PCI_DEVICE_ID_INTEL_JSP_ESPI_7, "Jasperlake PCH N" }, { PCI_DEVICE_ID_INTEL_MCC_ESPI_0, "Elkhartlake-0" }, { PCI_DEVICE_ID_INTEL_MCC_ESPI_1, "Elkhartlake-1" }, { PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI, "Elkhartlake Base" }, @@ -105,7 +105,10 @@ { PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, "Tigerlake U GT2" }, { PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, "Tigerlake Y GT2" }, { PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, "Tigerlake U GT3" }, - { PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0, "Jasperlake Pre Prod GT0" }, + { PCI_DEVICE_ID_INTEL_JSL_NOGT, "Jasperlake A0 NO GT" }, + { PCI_DEVICE_ID_INTEL_JSL_GT8, "Jasperlake A0 GT1 (8 EU)" }, + { PCI_DEVICE_ID_INTEL_JSL_GT16, "Jasperlake A0 GT1 (16 EU)" }, + { PCI_DEVICE_ID_INTEL_JSL_GT32, "Jasperlake A0 GT1 (32 EU)" }, { PCI_DEVICE_ID_INTEL_EHL_GT1_1, "Elkhartlake GT1 1" }, { PCI_DEVICE_ID_INTEL_EHL_GT2_1, "Elkhartlake GT2 1" }, { PCI_DEVICE_ID_INTEL_EHL_GT1_2, "Elkhartlake GT1 2" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/38849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c9ec1eb4236184b981d99250f263172c82f7117 Gerrit-Change-Number: 38849 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

7 25

Change in coreboot[master]: soc/intel/common/block: Move cse common functions into block/cse
by Patrick Georgi (Code Review) 25 Feb '20

25 Feb '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/26133 ) Change subject: soc/intel/common/block: Move cse common functions into block/cse ...................................................................... soc/intel/common/block: Move cse common functions into block/cse This patch cleans soc/intel/{cnl, icl, tgl} by moving common soc code into common/block/cse. Supported SoC can select existing HECI_DISABLE_USING_SMM option to select common cse code block to make heci function disable using sideband interface during SMM mode at preboot envionment. BUG=b:78109109 TEST=Able to make HECI disable in SMM mode successfully without any hang or errors in CNL, ICL and TGL platform. Change-Id: I22a4cc05d3967c7653d2abe2c829b4876516d179 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26133 Reviewed-by: V Sowmya <v.sowmya(a)intel.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc A src/soc/intel/common/block/cse/disable_heci.c M src/soc/intel/common/block/include/intelblocks/cse.h M src/soc/intel/icelake/smihandler.c M src/soc/intel/tigerlake/smihandler.c 7 files changed, 76 insertions(+), 117 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved V Sowmya: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 550c92d..4be7897 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -18,49 +18,11 @@ #include <console/console.h> #include <device/pci_def.h> #include <intelblocks/cse.h> -#include <intelblocks/p2sb.h> -#include <intelblocks/pcr.h> #include <intelblocks/smihandler.h> #include <soc/soc_chip.h> #include <soc/pci_devs.h> -#include <soc/pcr_ids.h> #include <soc/pm.h> -#define CSME0_FBE 0xf -#define CSME0_BAR 0x0 -#define CSME0_FID 0xb0 - -static void pch_disable_heci(void) -{ - struct pcr_sbi_msg msg = { - .pid = PID_CSME0, - .offset = 0, - .opcode = PCR_WRITE, - .is_posted = false, - .fast_byte_enable = CSME0_FBE, - .bar = CSME0_BAR, - .fid = CSME0_FID - }; - /* Bit 0: Set to make HECI#1 Function disable */ - uint32_t data32 = 1; - uint8_t response; - int status; - - /* unhide p2sb device */ - p2sb_unhide(); - - /* Send SBI command to make HECI#1 function disable */ - status = pcr_execute_sideband_msg(&msg, &data32, &response); - if (status && response) - printk(BIOS_ERR, "Fail to make CSME function disable\n"); - - /* Ensure to Lock SBI interface after this command */ - p2sb_disable_sideband_access(); - - /* hide p2sb device */ - p2sb_hide(); -} - /* * Specific SOC SMI handler during ramstage finalize phase * @@ -75,7 +37,7 @@ config = config_of_soc(); if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) - pch_disable_heci(); + heci_disable(); } const smi_handler_t southbridge_smi[SMI_STS_BITS] = { diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 321d34c..15de0b0 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -4,3 +4,11 @@ help Driver for communication with Converged Security Engine (CSE) over Host Embedded Controller Interface (HECI) + +config SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM + bool + default y if HECI_DISABLE_USING_SMM + select SOC_INTEL_COMMON_BLOCK_P2SB + help + Use this config to include common CSE block to make HECI function + disable in SMM mode diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 376f00f..90f76d5 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -1,3 +1,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c diff --git a/src/soc/intel/common/block/cse/disable_heci.c b/src/soc/intel/common/block/cse/disable_heci.c new file mode 100644 index 0000000..f560a37 --- /dev/null +++ b/src/soc/intel/common/block/cse/disable_heci.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Intel Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <commonlib/helpers.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <intelblocks/cse.h> +#include <intelblocks/p2sb.h> +#include <intelblocks/pcr.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <string.h> + +#define CSME0_FBE 0xf +#define CSME0_BAR 0x0 +#define CSME0_FID 0xb0 + +/* Disable HECI using Sideband interface communication */ +void heci_disable(void) +{ + struct pcr_sbi_msg msg = { + .pid = PID_CSME0, + .offset = 0, + .opcode = PCR_WRITE, + .is_posted = false, + .fast_byte_enable = CSME0_FBE, + .bar = CSME0_BAR, + .fid = CSME0_FID + }; + /* Bit 0: Set to make HECI#1 Function disable */ + uint32_t data32 = 1; + uint8_t response; + int status; + + /* unhide p2sb device */ + p2sb_unhide(); + + /* Send SBI command to make HECI#1 function disable */ + status = pcr_execute_sideband_msg(&msg, &data32, &response); + if (status || response) + printk(BIOS_ERR, "Fail to make CSME function disable\n"); + + /* Ensure to Lock SBI interface after this command */ + p2sb_disable_sideband_access(); + + /* hide p2sb device */ + p2sb_hide(); +} diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index c597a3f..59ddc5b 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -97,6 +97,8 @@ * Returns 0 on failure and 1 on success. */ int heci_reset(void); +/* Disable HECI using Sideband interface communication */ +void heci_disable(void); /* Reads config value from a specified offset in the CSE PCI Config space. */ uint32_t me_read_config32(int offset); diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index 5228f5d..6be7b70 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -16,49 +16,11 @@ #include <console/console.h> #include <device/pci_def.h> #include <intelblocks/cse.h> -#include <intelblocks/p2sb.h> -#include <intelblocks/pcr.h> #include <intelblocks/smihandler.h> #include <soc/soc_chip.h> #include <soc/pci_devs.h> -#include <soc/pcr_ids.h> #include <soc/pm.h> -#define CSME0_FBE 0xf -#define CSME0_BAR 0x0 -#define CSME0_FID 0xb0 - -static void pch_disable_heci(void) -{ - struct pcr_sbi_msg msg = { - .pid = PID_CSME0, - .offset = 0, - .opcode = PCR_WRITE, - .is_posted = false, - .fast_byte_enable = CSME0_FBE, - .bar = CSME0_BAR, - .fid = CSME0_FID - }; - /* Bit 0: Set to make HECI#1 Function disable */ - uint32_t data32 = 1; - uint8_t response; - int status; - - /* unhide p2sb device */ - p2sb_unhide(); - - /* Send SBI command to make HECI#1 function disable */ - status = pcr_execute_sideband_msg(&msg, &data32, &response); - if (status && response) - printk(BIOS_ERR, "Fail to make CSME function disable\n"); - - /* Ensure to Lock SBI interface after this command */ - p2sb_disable_sideband_access(); - - /* hide p2sb device */ - p2sb_hide(); -} - /* * Specific SOC SMI handler during ramstage finalize phase * @@ -73,7 +35,7 @@ config = config_of_soc(); if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) - pch_disable_heci(); + heci_disable(); } const smi_handler_t southbridge_smi[SMI_STS_BITS] = { diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c index 68954eb..0e8d345 100644 --- a/src/soc/intel/tigerlake/smihandler.c +++ b/src/soc/intel/tigerlake/smihandler.c @@ -16,49 +16,11 @@ #include <console/console.h> #include <device/pci_def.h> #include <intelblocks/cse.h> -#include <intelblocks/p2sb.h> -#include <intelblocks/pcr.h> #include <intelblocks/smihandler.h> #include <soc/soc_chip.h> #include <soc/pci_devs.h> -#include <soc/pcr_ids.h> #include <soc/pm.h> -#define CSME0_FBE 0xf -#define CSME0_BAR 0x0 -#define CSME0_FID 0xb0 - -static void pch_disable_heci(void) -{ - struct pcr_sbi_msg msg = { - .pid = PID_CSME0, - .offset = 0, - .opcode = PCR_WRITE, - .is_posted = false, - .fast_byte_enable = CSME0_FBE, - .bar = CSME0_BAR, - .fid = CSME0_FID - }; - /* Bit 0: Set to make HECI#1 Function disable */ - uint32_t data32 = 1; - uint8_t response; - int status; - - /* unhide p2sb device */ - p2sb_unhide(); - - /* Send SBI command to make HECI#1 function disable */ - status = pcr_execute_sideband_msg(&msg, &data32, &response); - if (status && response) - printk(BIOS_ERR, "Fail to make CSME function disable\n"); - - /* Ensure to Lock SBI interface after this command */ - p2sb_disable_sideband_access(); - - /* hide p2sb device */ - p2sb_hide(); -} - /* * Specific SOC SMI handler during ramstage finalize phase * @@ -73,7 +35,7 @@ config = config_of_soc(); if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) - pch_disable_heci(); + heci_disable(); } const smi_handler_t southbridge_smi[SMI_STS_BITS] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/26133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22a4cc05d3967c7653d2abe2c829b4876516d179 Gerrit-Change-Number: 26133 Gerrit-PatchSet: 41 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/block: Move smihandler common functions into common ...
by Patrick Georgi (Code Review) 25 Feb '20

25 Feb '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/26138 ) Change subject: soc/intel/common/block: Move smihandler common functions into common code ...................................................................... soc/intel/common/block: Move smihandler common functions into common code This patch cleans soc/intel/{apl/cnl/skl/icl/tgl} by moving common soc code into common/block/smihandler.c BUG=b:78109109 TEST=Build and boot KBL/CNL/APL/ICL/TGL platform. Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26138 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/apollolake/smihandler.c M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/common/block/include/intelblocks/smihandler.h M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/icelake/smihandler.c M src/soc/intel/skylake/smihandler.c M src/soc/intel/tigerlake/smihandler.c 7 files changed, 44 insertions(+), 185 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index 424d66f..e37de92 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. + * Copyright (C) 2015-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -34,16 +34,6 @@ return &em64t100_smm_ops; } -/* SMI handlers that should be serviced in SCI mode too. */ -uint32_t smihandler_soc_get_sci_mask(void) -{ - uint32_t sci_mask = - SMI_HANDLER_SCI_EN(APM_STS_BIT) | - SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT); - - return sci_mask; -} - const smi_handler_t southbridge_smi[32] = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 4d0b241..550c92d 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -3,7 +3,7 @@ * * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,26 +17,19 @@ #include <console/console.h> #include <device/pci_def.h> -#include <intelblocks/fast_spi.h> +#include <intelblocks/cse.h> #include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> #include <intelblocks/smihandler.h> -#include <soc/p2sb.h> +#include <soc/soc_chip.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> #include <soc/pm.h> -#include "chip.h" - #define CSME0_FBE 0xf #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 -const struct smm_save_state_ops *get_smm_save_state_ops(void) -{ - return &em64t101_smm_ops; -} - static void pch_disable_heci(void) { struct pcr_sbi_msg msg = { @@ -85,36 +78,6 @@ pch_disable_heci(); } -void smihandler_soc_check_illegal_access(uint32_t tco_sts) -{ - if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) - && fast_spi_wpd_status())) - return; - - /* - * BWE is RW, so the SMI was caused by a - * write to BWE, not by a write to the BIOS - * - * This is the place where we notice someone - * is trying to tinker with the BIOS. We are - * trying to be nice and just ignore it. A more - * resolute answer would be to power down the - * box. - */ - printk(BIOS_DEBUG, "Switching back to RO\n"); - fast_spi_enable_wp(); -} - -/* SMI handlers that should be serviced in SCI mode too. */ -uint32_t smihandler_soc_get_sci_mask(void) -{ - uint32_t sci_mask = - SMI_HANDLER_SCI_EN(APM_STS_BIT) | - SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT); - - return sci_mask; -} - const smi_handler_t southbridge_smi[SMI_STS_BITS] = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, diff --git a/src/soc/intel/common/block/include/intelblocks/smihandler.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h index d8520f1..06b9e21 100644 --- a/src/soc/intel/common/block/include/intelblocks/smihandler.h +++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h @@ -156,15 +156,6 @@ */ int smihandler_soc_disable_busmaster(pci_devfn_t dev); -/* SMI handlers that should be serviced in SCI mode too. */ -uint32_t smihandler_soc_get_sci_mask(void); - -/* - * SoC needs to implement the mechanism to know if an illegal attempt - * has been made to write to the BIOS area. - */ -void smihandler_soc_check_illegal_access(uint32_t tco_sts); - /* Mainboard overrides. */ /* Mainboard handler for GPI SMIs */ diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 4677d27..54f4e41 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2017 Intel Corp. + * Copyright (C) 2015-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -44,6 +44,11 @@ /* SoC overrides. */ +__weak const struct smm_save_state_ops *get_smm_save_state_ops(void) +{ + return &em64t101_smm_ops; +} + /* Specific SOC SMI handler during ramstage finalize phase */ __weak void smihandler_soc_at_finalize(void) { @@ -55,20 +60,29 @@ return 1; } -/* SMI handlers that should be serviced in SCI mode too. */ -__weak uint32_t smihandler_soc_get_sci_mask(void) -{ - return 0; /* No valid SCI mask for SMI handler */ -} - /* * Needs to implement the mechanism to know if an illegal attempt * has been made to write to the BIOS area. */ -__weak void smihandler_soc_check_illegal_access( +static void smihandler_soc_check_illegal_access( uint32_t tco_sts) { - return; + if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) + && fast_spi_wpd_status())) + return; + + /* + * BWE is RW, so the SMI was caused by a + * write to BWE, not by a write to the BIOS + * + * This is the place where we notice someone + * is trying to tinker with the BIOS. We are + * trying to be nice and just ignore it. A more + * resolute answer would be to power down the + * box. + */ + printk(BIOS_DEBUG, "Switching back to RO\n"); + fast_spi_enable_wp(); } /* Mainboard overrides. */ @@ -472,6 +486,16 @@ mainboard_smi_espi_handler(); } +/* SMI handlers that should be serviced in SCI mode too. */ +static uint32_t smihandler_soc_get_sci_mask(void) +{ + uint32_t sci_mask = + SMI_HANDLER_SCI_EN(APM_STS_BIT) | + SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT); + + return sci_mask; +} + void southbridge_smi_handler(void) { int i; diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index b7c37d4..5228f5d 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. + * Copyright (C) 2018-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,25 +15,19 @@ #include <console/console.h> #include <device/pci_def.h> -#include <intelblocks/fast_spi.h> +#include <intelblocks/cse.h> #include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> #include <intelblocks/smihandler.h> -#include <soc/p2sb.h> +#include <soc/soc_chip.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> #include <soc/pm.h> -#include <soc/soc_chip.h> #define CSME0_FBE 0xf #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 -const struct smm_save_state_ops *get_smm_save_state_ops(void) -{ - return &em64t101_smm_ops; -} - static void pch_disable_heci(void) { struct pcr_sbi_msg msg = { @@ -82,36 +76,6 @@ pch_disable_heci(); } -void smihandler_soc_check_illegal_access(uint32_t tco_sts) -{ - if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) - && fast_spi_wpd_status())) - return; - - /* - * BWE is RW, so the SMI was caused by a - * write to BWE, not by a write to the BIOS - * - * This is the place where we notice someone - * is trying to tinker with the BIOS. We are - * trying to be nice and just ignore it. A more - * resolute answer would be to power down the - * box. - */ - printk(BIOS_DEBUG, "Switching back to RO\n"); - fast_spi_enable_wp(); -} - -/* SMI handlers that should be serviced in SCI mode too. */ -uint32_t smihandler_soc_get_sci_mask(void) -{ - uint32_t sci_mask = - SMI_HANDLER_SCI_EN(APM_STS_BIT) | - SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT); - - return sci_mask; -} - const smi_handler_t southbridge_smi[SMI_STS_BITS] = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 2e93075..4818c02 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -3,7 +3,7 @@ * * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. + * Copyright (C) 2015-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,46 +15,9 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <intelblocks/fast_spi.h> #include <intelblocks/smihandler.h> #include <soc/pm.h> -const struct smm_save_state_ops *get_smm_save_state_ops(void) -{ - return &em64t101_smm_ops; -} - -void smihandler_soc_check_illegal_access(uint32_t tco_sts) -{ - if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) - && fast_spi_wpd_status())) - return; - - /* - * BWE is RW, so the SMI was caused by a - * write to BWE, not by a write to the BIOS - * - * This is the place where we notice someone - * is trying to tinker with the BIOS. We are - * trying to be nice and just ignore it. A more - * resolute answer would be to power down the - * box. - */ - printk(BIOS_DEBUG, "Switching back to RO\n"); - fast_spi_enable_wp(); -} - -/* SMI handlers that should be serviced in SCI mode too. */ -uint32_t smihandler_soc_get_sci_mask(void) -{ - uint32_t sci_mask = - SMI_HANDLER_SCI_EN(APM_STS_BIT) | - SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT); - - return sci_mask; -} - const smi_handler_t southbridge_smi[SMI_STS_BITS] = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c index bf07bea..68954eb 100644 --- a/src/soc/intel/tigerlake/smihandler.c +++ b/src/soc/intel/tigerlake/smihandler.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. + * Copyright (C) 2019-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,25 +15,19 @@ #include <console/console.h> #include <device/pci_def.h> -#include <intelblocks/fast_spi.h> +#include <intelblocks/cse.h> #include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> #include <intelblocks/smihandler.h> -#include <soc/p2sb.h> +#include <soc/soc_chip.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> #include <soc/pm.h> -#include <soc/soc_chip.h> #define CSME0_FBE 0xf #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 -const struct smm_save_state_ops *get_smm_save_state_ops(void) -{ - return &em64t101_smm_ops; -} - static void pch_disable_heci(void) { struct pcr_sbi_msg msg = { @@ -82,36 +76,6 @@ pch_disable_heci(); } -void smihandler_soc_check_illegal_access(uint32_t tco_sts) -{ - if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) - && fast_spi_wpd_status())) - return; - - /* - * BWE is RW, so the SMI was caused by a - * write to BWE, not by a write to the BIOS - * - * This is the place where we notice someone - * is trying to tinker with the BIOS. We are - * trying to be nice and just ignore it. A more - * resolute answer would be to power down the - * box. - */ - printk(BIOS_DEBUG, "Switching back to RO\n"); - fast_spi_enable_wp(); -} - -/* SMI handlers that should be serviced in SCI mode too. */ -uint32_t smihandler_soc_get_sci_mask(void) -{ - uint32_t sci_mask = - SMI_HANDLER_SCI_EN(APM_STS_BIT) | - SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT); - - return sci_mask; -} - const smi_handler_t southbridge_smi[SMI_STS_BITS] = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, -- To view, visit https://review.coreboot.org/c/coreboot/+/26138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03 Gerrit-Change-Number: 26138 Gerrit-PatchSet: 45 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: superio/aspeed/ast2400: rename SWAK to SWC to match the datasheet
by Patrick Georgi (Code Review) 25 Feb '20

25 Feb '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39095 ) Change subject: superio/aspeed/ast2400: rename SWAK to SWC to match the datasheet ...................................................................... superio/aspeed/ast2400: rename SWAK to SWC to match the datasheet The datasheet uses "SWC" as shortcut for "System Wake-up Controller", thus rename it in the code. Change-Id: I8b3a14946e37f805d1c4e3df343dfcd7f67f6dc8 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39095 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/superio/aspeed/ast2400/ast2400.h M src/superio/aspeed/ast2400/superio.c 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Frans Hendriks: Looks good to me, approved diff --git a/src/superio/aspeed/ast2400/ast2400.h b/src/superio/aspeed/ast2400/ast2400.h index d9e4ea1..d361c8b 100644 --- a/src/superio/aspeed/ast2400/ast2400.h +++ b/src/superio/aspeed/ast2400/ast2400.h @@ -6,7 +6,7 @@ #define AST2400_SUART1 0x2 /* Com1 */ #define AST2400_SUART2 0x3 /* Com2 */ -#define AST2400_SWAK 0x4 /* System Wake-Up control */ +#define AST2400_SWC 0x4 /* System Wake-Up Control */ #define AST2400_KBC 0x5 /* Keyboard controller */ #define AST2400_GPIO 0x7 /* GPIO */ #define AST2400_SUART3 0xB /* Com3 */ diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c index 0941663..a3d92c2 100644 --- a/src/superio/aspeed/ast2400/superio.c +++ b/src/superio/aspeed/ast2400/superio.c @@ -75,7 +75,7 @@ static struct pnp_info pnp_dev_info[] = { { NULL, AST2400_SUART1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, }, { NULL, AST2400_SUART2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, }, - { NULL, AST2400_SWAK, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 + { NULL, AST2400_SWC, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0, 0xfff8, 0xfff8, 0xfff8, 0xfff8, }, { NULL, AST2400_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1 | PNP_MSC0, 0xffff, 0xffff, }, -- To view, visit https://review.coreboot.org/c/coreboot/+/39095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b3a14946e37f805d1c4e3df343dfcd7f67f6dc8 Gerrit-Change-Number: 39095 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: payloads/tianocore: Enable PS2 keyboard module
by Angel Pons (Code Review) 25 Feb '20

25 Feb '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38960 ) Change subject: payloads/tianocore: Enable PS2 keyboard module ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/38960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6d468809142a0049ce1648217d62b070229ad6b Gerrit-Change-Number: 38960 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 25 Feb 2020 10:04:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2020