coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

1 participants
1797 discussions

Change in coreboot[master]: mb/supermicro/x11-lga1151-series: devicetree: fix iLPC2AHB irq
by Michael Niewöhner (Code Review) 24 Feb '20

24 Feb '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39092 ) Change subject: mb/supermicro/x11-lga1151-series: devicetree: fix iLPC2AHB irq ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/39092/1/src/mainboard/supermicro/x… File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb: https://review.coreboot.org/c/coreboot/+/39092/1/src/mainboard/supermicro/x… PS1, Line 109: irq 0x70 = 0x0 > I couldn't find a reference in the Aspeed datasheet that "0" means disable and INT0 is assigned to t […] Yep, I just set what the vendor set - we could use another value as well here - suggestions? -- To view, visit https://review.coreboot.org/c/coreboot/+/39092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc1cd04e995d68f4c779e9aa9c09bb7bf9f26363 Gerrit-Change-Number: 39092 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 24 Feb 2020 16:13:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Comment-In-Reply-To: Michael Niewöhner Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/supermicro/x11-lga1151-series: devicetree: fix superio interrupts
by Michael Niewöhner (Code Review) 24 Feb '20

24 Feb '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39091 ) Change subject: mb/supermicro/x11-lga1151-series: devicetree: fix superio interrupts ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/39091/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39091/1//COMMIT_MSG@9 PS1, Line 9: The default interrupt (0xb) of the GPIO device conflicts with the > There are less than 16 legacy interrupts. […] Hmm, I wasn't aware of that. At least 0xb never got set for the SWC as specified in the devicetree. That only worked after this "fix". Have to recheck -- To view, visit https://review.coreboot.org/c/coreboot/+/39091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e045dc32a9c594f4f43e4fb8237f67dd26df5cf Gerrit-Change-Number: 39091 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 24 Feb 2020 16:12:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/supermicro/x11-lga1151-series: fix GPIO reset mapping
by Michael Niewöhner (Code Review) 24 Feb '20

24 Feb '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39090 ) Change subject: mb/supermicro/x11-lga1151-series: fix GPIO reset mapping ...................................................................... Patch Set 1: > Patch Set 1: Code-Review+2 > > Doesn't make it easier to read, though, looks like hardware values > but isn't. Better to get rid of _PAD_CFG_STRUCT(), it's not intended > for the mainboard level. Agreed. As soon as I have a little time I could try to complete Maxims work on that go converter (there were some bits missing). -- To view, visit https://review.coreboot.org/c/coreboot/+/39090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ae17dfc4d90f88f5b8bc5bee49740745778a91a Gerrit-Change-Number: 39090 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 24 Feb 2020 16:10:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mainboard: Add OCP Tioga Pass board
by Angel Pons (Code Review) 24 Feb '20

24 Feb '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38840 ) Change subject: mainboard: Add OCP Tioga Pass board ...................................................................... Patch Set 13: (4 comments) https://review.coreboot.org/c/coreboot/+/38840/13/src/mainboard/ocp/tiogapa… File src/mainboard/ocp/tiogapass/Kconfig: https://review.coreboot.org/c/coreboot/+/38840/13/src/mainboard/ocp/tiogapa… PS13, Line 21: select CPU_INTEL_MODEL_XEONSP : select CPU_INTEL_MODEL_XEONSP_SKX Would selecting only one of these suffice? https://review.coreboot.org/c/coreboot/+/38840/13/src/mainboard/ocp/tiogapa… File src/mainboard/ocp/tiogapass/Kconfig.name: https://review.coreboot.org/c/coreboot/+/38840/13/src/mainboard/ocp/tiogapa… PS13, Line 1: BOARD_OCP_TIOGAPASS Would `BOARD_OCP_TIOGA_PASS` look better? https://review.coreboot.org/c/coreboot/+/38840/13/src/mainboard/ocp/tiogapa… File src/mainboard/ocp/tiogapass/board_info.txt: https://review.coreboot.org/c/coreboot/+/38840/13/src/mainboard/ocp/tiogapa… PS13, Line 3: eval server ? https://review.coreboot.org/c/coreboot/+/38840/13/src/mainboard/ocp/tiogapa… File src/mainboard/ocp/tiogapass/devicetree.cb: https://review.coreboot.org/c/coreboot/+/38840/13/src/mainboard/ocp/tiogapa… PS13, Line 7: Intel Corporation I would think this part is redundant -- To view, visit https://review.coreboot.org/c/coreboot/+/38840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6c5da3c3856b035af5f2b3b80f0894f6fb81696 Gerrit-Change-Number: 38840 Gerrit-PatchSet: 13 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 24 Feb 2020 15:49:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/intel/xeonsp: Add initial Skylake-SP support
by Angel Pons (Code Review) 24 Feb '20

24 Feb '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38839 ) Change subject: cpu/intel/xeonsp: Add initial Skylake-SP support ...................................................................... Patch Set 11: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/38839/11/src/cpu/intel/Kconfig File src/cpu/intel/Kconfig: https://review.coreboot.org/c/coreboot/+/38839/11/src/cpu/intel/Kconfig@17 PS11, Line 17: source "src/cpu/intel/xeonsp/cpu/*/Kconfig" Maybe source that from within "src/cpu/intel/xeonsp/Kconfig" ? -- To view, visit https://review.coreboot.org/c/coreboot/+/38839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaccd8e0034abd5954e3169bf7e585b5f59fe1ead Gerrit-Change-Number: 38839 Gerrit-PatchSet: 11 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 24 Feb 2020 15:46:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu: Add initial xeonsp support boilerplate
by Angel Pons (Code Review) 24 Feb '20

24 Feb '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38838 ) Change subject: cpu: Add initial xeonsp support boilerplate ...................................................................... Patch Set 11: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/38838/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38838/2//COMMIT_MSG@10 PS2, Line 10: xeonsp > I like xeon_scalable more than xeonsp, thanks. […] Ack. In any case, I would at least add some spacing for readability: "xeon_sp" -- To view, visit https://review.coreboot.org/c/coreboot/+/38838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24346b8a5c30342419db23b5f1adf27d4d0ebc5f Gerrit-Change-Number: 38838 Gerrit-PatchSet: 11 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 24 Feb 2020 15:39:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Andrey Petrov <anpetrov(a)fb.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [TESTME]mb/amd/parmer: Switch away from ROMCC_BOOTBLOCK
by Mike Banon (Code Review) 24 Feb '20

24 Feb '20

Hello HAOUAS Elyes, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38879 to review the following change. Change subject: [TESTME]mb/amd/parmer: Switch away from ROMCC_BOOTBLOCK ...................................................................... [TESTME]mb/amd/parmer: Switch away from ROMCC_BOOTBLOCK Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ic3fda4e598af8df9c9ddc97f7eb7fdcdaff6580b --- M src/mainboard/amd/parmer/Kconfig M src/mainboard/amd/parmer/Kconfig.name M src/mainboard/amd/parmer/Makefile.inc R src/mainboard/amd/parmer/bootblock.c 4 files changed, 6 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/38879/1 diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index ae024dd..820d43e 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -13,14 +13,10 @@ # GNU General Public License for more details. # -config BOARD_AMD_PARMER - def_bool n - if BOARD_AMD_PARMER config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/amd/parmer/Kconfig.name b/src/mainboard/amd/parmer/Kconfig.name index 0771468..3aedc95 100644 --- a/src/mainboard/amd/parmer/Kconfig.name +++ b/src/mainboard/amd/parmer/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_AMD_PARMER -# bool"Parmer" +config BOARD_AMD_PARMER + bool "Parmer" diff --git a/src/mainboard/amd/parmer/Makefile.inc b/src/mainboard/amd/parmer/Makefile.inc index f8895fa..4dde2cf 100644 --- a/src/mainboard/amd/parmer/Makefile.inc +++ b/src/mainboard/amd/parmer/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/bootblock.c similarity index 68% rename from src/mainboard/amd/parmer/romstage.c rename to src/mainboard/amd/parmer/bootblock.c index 6366c4e..fea4d7b 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/bootblock.c @@ -13,14 +13,9 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <device/pci_ops.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/agesa/hudson/hudson.h> -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - - /* For serial port option, plug-in card on LPC. */ - pci_write_config32(dev, 0x44, 0xff03ffd5); } -- To view, visit https://review.coreboot.org/c/coreboot/+/38879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3fda4e598af8df9c9ddc97f7eb7fdcdaff6580b Gerrit-Change-Number: 38879 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: [TESTME]mb/amd/persimmon: Switch away from ROMCC_BOOTBLOCK
by Mike Banon (Code Review) 24 Feb '20

24 Feb '20

Hello HAOUAS Elyes, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38873 to review the following change. Change subject: [TESTME]mb/amd/persimmon: Switch away from ROMCC_BOOTBLOCK ...................................................................... [TESTME]mb/amd/persimmon: Switch away from ROMCC_BOOTBLOCK Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I51d42f137fa539225bca5631bec38144ffd4f1d5 --- M src/mainboard/amd/persimmon/Kconfig M src/mainboard/amd/persimmon/Kconfig.name M src/mainboard/amd/persimmon/Makefile.inc R src/mainboard/amd/persimmon/bootblock.c 4 files changed, 6 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/38873/1 diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index f243f0f..41bf3c9 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -13,14 +13,10 @@ # GNU General Public License for more details. # -config BOARD_AMD_PERSIMMON - def_bool n - if BOARD_AMD_PERSIMMON config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/persimmon/Kconfig.name b/src/mainboard/amd/persimmon/Kconfig.name index d50ebbe..ba24b13a 100644 --- a/src/mainboard/amd/persimmon/Kconfig.name +++ b/src/mainboard/amd/persimmon/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_AMD_PERSIMMON -# bool"Persimmon" +config BOARD_AMD_PERSIMMON + bool "Persimmon" diff --git a/src/mainboard/amd/persimmon/Makefile.inc b/src/mainboard/amd/persimmon/Makefile.inc index ba56286..bf86007 100644 --- a/src/mainboard/amd/persimmon/Makefile.inc +++ b/src/mainboard/amd/persimmon/Makefile.inc @@ -20,6 +20,8 @@ pci$(stripped_ahcibios_id).rom-type := optionrom endif +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/bootblock.c similarity index 84% rename from src/mainboard/amd/persimmon/romstage.c rename to src/mainboard/amd/persimmon/bootblock.c index 7ccf167..6cd9e2a 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/bootblock.c @@ -13,15 +13,13 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/state_machine.h> +#include <bootblock_common.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> -#include <sb_cimx.h> #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { - sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } -- To view, visit https://review.coreboot.org/c/coreboot/+/38873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51d42f137fa539225bca5631bec38144ffd4f1d5 Gerrit-Change-Number: 38873 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: include/arch/cpu.h: Remove old refrence to ROMCC
by HAOUAS Elyes (Code Review) 24 Feb '20

24 Feb '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39071 ) Change subject: include/arch/cpu.h: Remove old refrence to ROMCC ...................................................................... include/arch/cpu.h: Remove old refrence to ROMCC Change-Id: I17d13c53baf16f58e6e2ba45f439c36f7ba28690 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/include/arch/cpu.h 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/39071/1 diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index c8cf8c7..59eb9ad 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -261,7 +261,6 @@ return ci; } -/* romcc is segfaulting in some cases. */ struct cpuinfo_x86 { uint8_t x86; /* CPU family */ uint8_t x86_vendor; /* CPU vendor */ @@ -281,7 +280,6 @@ } -/* romcc does not understand regparm. */ #define asmlinkage __attribute__((regparm(0))) /* -- To view, visit https://review.coreboot.org/c/coreboot/+/39071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17d13c53baf16f58e6e2ba45f439c36f7ba28690 Gerrit-Change-Number: 39071 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: Documentation/project_ideas: Update after 2019
by Patrick Georgi (Code Review) 24 Feb '20

24 Feb '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39086 ) Change subject: Documentation/project_ideas: Update after 2019 ...................................................................... Documentation/project_ideas: Update after 2019 The coverity project is done, for the most part, so drop it. Expand a bit on the scope of the toolchain binary project, and point out that the Ghidra project already has code from GSoC 2019 but could be developed further. Change-Id: I7342cc3133494f69b175b11b1f8342a0f40840e7 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/contributing/project_ideas.md 1 file changed, 8 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/39086/1 diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index 90164a2..8271ea9 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -27,7 +27,9 @@ Provide packages/installers of our compiler toolchain for Linux distros, Windows, Mac OS. For Windows, this should also include the environment -(shell, make, ...). +(shell, make, ...). A student doesn't have to cover _all_ platforms, but +pick a set of systems that match their interest and knowledge and lay +out a plan on how to do this. The scripts to generate these packages should be usable on a Linux host, as that's what we're using for our automated build testing system @@ -131,26 +133,6 @@ ### Mentors * Patrick Georgi <patrick(a)georgi.software> -## Make coreboot coverity clean -coreboot and several other of our projects are automatically tested -using Synopsys' free "Coverity Scan" service. While some fare pretty -good, like [em100](https://scan.coverity.com/projects/em100) at 0 known -defects, there are still many open issues in other projects, most notably -[coreboot](https://scan.coverity.com/projects/coreboot) itself (which -is also the largest codebase). - -Not all of the reports are actual issues, but the project benefits a -lot if the list of unhandled reports is down to 0 because that provides -a baseline when future changes reintroduce new issues: it's easier to -triage and handle a list of 5 issues rather than more than 350. - -This project would be going through all reports and handling them -appropriately: Figure out if reports are valid or not and mark them -as such. For valid reports, provide patches to fix the underlying issue. - -### Mentors -* Patrick Georgi <patrick(a)georgi.software> - ## Extend Ghidra to support analysis of firmware images [Ghidra](https://ghidra-sre.org) is a recently released cross-platform disassembler and decompiler that is extensible through plugins. Make it @@ -158,6 +140,11 @@ integrating UEFITool, cbfstool, decompressors), automatically identify 16/32/64bit code on x86/amd64, etc. +This has been done in 2019 with [some neat +features](https://github.com/al3xtjames/ghidra-firmware-utils) being +developed, but it may be possible to expand support for all kinds of firmware +analyses. + ## Learn hardware behavior from I/O and memory access logs [SerialICE](https://www.serialice.com) is a tool to trace the behavior of executable code like firmware images. One result of that is a long log file -- To view, visit https://review.coreboot.org/c/coreboot/+/39086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7342cc3133494f69b175b11b1f8342a0f40840e7 Gerrit-Change-Number: 39086 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 4

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2020