coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

1 participants
1797 discussions

Change in coreboot[master]: [TESTME]mb/elmex/pcm20540*: Switch away from ROMCC_BOOTBLOCK
by Mike Banon (Code Review) 24 Feb '20

24 Feb '20

Hello HAOUAS Elyes, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38870 to review the following change. Change subject: [TESTME]mb/elmex/pcm20540*: Switch away from ROMCC_BOOTBLOCK ...................................................................... [TESTME]mb/elmex/pcm20540*: Switch away from ROMCC_BOOTBLOCK Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I53b80fe97370c99968f073dfad61b5e5709e4ab6 --- M src/mainboard/elmex/pcm205400/Kconfig M src/mainboard/elmex/pcm205400/Kconfig.name M src/mainboard/elmex/pcm205400/Makefile.inc R src/mainboard/elmex/pcm205400/bootblock.c M src/mainboard/elmex/pcm205401/Kconfig M src/mainboard/elmex/pcm205401/Kconfig.name 6 files changed, 8 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/38870/1 diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig index e94a6d8..7dc67d1 100644 --- a/src/mainboard/elmex/pcm205400/Kconfig +++ b/src/mainboard/elmex/pcm205400/Kconfig @@ -13,9 +13,6 @@ # GNU General Public License for more details. # -config BOARD_ELMEX_PCM205400 - def_bool n - if BOARD_ELMEX_PCM205400 config MAINBOARD_PART_NUMBER @@ -32,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/elmex/pcm205400/Kconfig.name b/src/mainboard/elmex/pcm205400/Kconfig.name index 6488992..445b588 100644 --- a/src/mainboard/elmex/pcm205400/Kconfig.name +++ b/src/mainboard/elmex/pcm205400/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_ELMEX_PCM205400 -# bool"pcm205400" +config BOARD_ELMEX_PCM205400 + bool "pcm205400" diff --git a/src/mainboard/elmex/pcm205400/Makefile.inc b/src/mainboard/elmex/pcm205400/Makefile.inc index ba56286..bf86007 100644 --- a/src/mainboard/elmex/pcm205400/Makefile.inc +++ b/src/mainboard/elmex/pcm205400/Makefile.inc @@ -20,6 +20,8 @@ pci$(stripped_ahcibios_id).rom-type := optionrom endif +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/elmex/pcm205400/romstage.c b/src/mainboard/elmex/pcm205400/bootblock.c similarity index 84% rename from src/mainboard/elmex/pcm205400/romstage.c rename to src/mainboard/elmex/pcm205400/bootblock.c index 7ccf167..6cd9e2a 100644 --- a/src/mainboard/elmex/pcm205400/romstage.c +++ b/src/mainboard/elmex/pcm205400/bootblock.c @@ -13,15 +13,13 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/state_machine.h> +#include <bootblock_common.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> -#include <sb_cimx.h> #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { - sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/elmex/pcm205401/Kconfig b/src/mainboard/elmex/pcm205401/Kconfig index 15c741a..a9bbe6e 100644 --- a/src/mainboard/elmex/pcm205401/Kconfig +++ b/src/mainboard/elmex/pcm205401/Kconfig @@ -13,9 +13,6 @@ # GNU General Public License for more details. # -config BOARD_ELMEX_PCM205401 - def_bool n - if BOARD_ELMEX_PCM205401 config MAINBOARD_PART_NUMBER diff --git a/src/mainboard/elmex/pcm205401/Kconfig.name b/src/mainboard/elmex/pcm205401/Kconfig.name index 050b94c..f70b215 100644 --- a/src/mainboard/elmex/pcm205401/Kconfig.name +++ b/src/mainboard/elmex/pcm205401/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_ELMEX_PCM205401 -# bool "pcm205401" +config BOARD_ELMEX_PCM205401 + bool "pcm205401" -- To view, visit https://review.coreboot.org/c/coreboot/+/38870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53b80fe97370c99968f073dfad61b5e5709e4ab6 Gerrit-Change-Number: 38870 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: [TESTME]mb/amd/union_station: Switch away from ROMCC_BOOTBLOCK
by Mike Banon (Code Review) 24 Feb '20

24 Feb '20

Hello HAOUAS Elyes, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38875 to review the following change. Change subject: [TESTME]mb/amd/union_station: Switch away from ROMCC_BOOTBLOCK ...................................................................... [TESTME]mb/amd/union_station: Switch away from ROMCC_BOOTBLOCK Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I0edfc7bb6d01eb1a12299fddd3d3ac45b43edfdb --- M src/mainboard/amd/union_station/Kconfig M src/mainboard/amd/union_station/Kconfig.name M src/mainboard/amd/union_station/Makefile.inc R src/mainboard/amd/union_station/bootblock.c 4 files changed, 6 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/38875/1 diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index 1532d34..72881b8 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -13,14 +13,10 @@ # GNU General Public License for more details. # -config BOARD_AMD_UNIONSTATION - def_bool n - if BOARD_AMD_UNIONSTATION config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/union_station/Kconfig.name b/src/mainboard/amd/union_station/Kconfig.name index b4dc5365..9af3c82 100644 --- a/src/mainboard/amd/union_station/Kconfig.name +++ b/src/mainboard/amd/union_station/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_AMD_UNIONSTATION -# bool"Unionstation" +config BOARD_AMD_UNIONSTATION + bool "Unionstation" diff --git a/src/mainboard/amd/union_station/Makefile.inc b/src/mainboard/amd/union_station/Makefile.inc index 440744c..ffea060 100644 --- a/src/mainboard/amd/union_station/Makefile.inc +++ b/src/mainboard/amd/union_station/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/bootblock.c similarity index 80% rename from src/mainboard/amd/union_station/romstage.c rename to src/mainboard/amd/union_station/bootblock.c index af64ad8..f0361d6 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/bootblock.c @@ -13,10 +13,8 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/state_machine.h> -#include <sb_cimx.h> +#include <bootblock_common.h> -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { - sb_Poweron_Init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/38875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0edfc7bb6d01eb1a12299fddd3d3ac45b43edfdb Gerrit-Change-Number: 38875 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: [TESTME]mb/lippert/frontrunner-af: Switch away from ROMCC_BOOTBLOCK
by Mike Banon (Code Review) 24 Feb '20

24 Feb '20

Hello HAOUAS Elyes, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38872 to review the following change. Change subject: [TESTME]mb/lippert/frontrunner-af: Switch away from ROMCC_BOOTBLOCK ...................................................................... [TESTME]mb/lippert/frontrunner-af: Switch away from ROMCC_BOOTBLOCK Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I63dd15ade28acb06da8d320edc8ae1fd433aa0e0 --- M src/mainboard/lippert/frontrunner-af/Kconfig M src/mainboard/lippert/frontrunner-af/Kconfig.name M src/mainboard/lippert/frontrunner-af/Makefile.inc R src/mainboard/lippert/frontrunner-af/bootblock.c 4 files changed, 6 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/38872/1 diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index 4a007bf..92d7743 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -13,14 +13,10 @@ # GNU General Public License for more details. # -config BOARD_LIPPERT_FRONTRUNNER_AF - def_bool n - if BOARD_LIPPERT_FRONTRUNNER_AF config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig.name b/src/mainboard/lippert/frontrunner-af/Kconfig.name index 1939264..2a8cba5 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig.name +++ b/src/mainboard/lippert/frontrunner-af/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_LIPPERT_FRONTRUNNER_AF -# bool"FrontRunner-AF aka ADLINK CoreModule2-GF" +config BOARD_LIPPERT_FRONTRUNNER_AF + bool "FrontRunner-AF aka ADLINK CoreModule2-GF" diff --git a/src/mainboard/lippert/frontrunner-af/Makefile.inc b/src/mainboard/lippert/frontrunner-af/Makefile.inc index 3ea57cd..46a44d2 100644 --- a/src/mainboard/lippert/frontrunner-af/Makefile.inc +++ b/src/mainboard/lippert/frontrunner-af/Makefile.inc @@ -20,6 +20,8 @@ pci$(stripped_ahcibios_id).rom-type := optionrom endif +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/bootblock.c similarity index 89% rename from src/mainboard/lippert/frontrunner-af/romstage.c rename to src/mainboard/lippert/frontrunner-af/bootblock.c index f8e6091..e0dddc2 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/bootblock.c @@ -13,14 +13,13 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <northbridge/amd/agesa/state_machine.h> #include <superio/smsc/smscsuperio/smscsuperio.h> -#include <sb_cimx.h> #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { - sb_Poweron_Init(); smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } -- To view, visit https://review.coreboot.org/c/coreboot/+/38872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63dd15ade28acb06da8d320edc8ae1fd433aa0e0 Gerrit-Change-Number: 38872 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: [TESTME]mb/amd/thatcher: Switch away from ROMCC_BOOTBLOCK
by Mike Banon (Code Review) 24 Feb '20

24 Feb '20

Hello HAOUAS Elyes, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38877 to review the following change. Change subject: [TESTME]mb/amd/thatcher: Switch away from ROMCC_BOOTBLOCK ...................................................................... [TESTME]mb/amd/thatcher: Switch away from ROMCC_BOOTBLOCK Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I948eeaaeb7975561fffc1218c70dba6a784101fe --- M src/mainboard/amd/thatcher/Kconfig M src/mainboard/amd/thatcher/Kconfig.name M src/mainboard/amd/thatcher/Makefile.inc A src/mainboard/amd/thatcher/bootblock.c D src/mainboard/amd/thatcher/romstage.c 5 files changed, 38 insertions(+), 60 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/38877/1 diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index e556592..e1c5aee 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -13,14 +13,10 @@ # GNU General Public License for more details. # -config BOARD_AMD_THATCHER - def_bool n - if BOARD_AMD_THATCHER config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/amd/thatcher/Kconfig.name b/src/mainboard/amd/thatcher/Kconfig.name index b57bdb9..aff5246 100644 --- a/src/mainboard/amd/thatcher/Kconfig.name +++ b/src/mainboard/amd/thatcher/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_AMD_THATCHER -# bool"Thatcher" +config BOARD_AMD_THATCHER + bool "Thatcher" diff --git a/src/mainboard/amd/thatcher/Makefile.inc b/src/mainboard/amd/thatcher/Makefile.inc index f8895fa..4dde2cf 100644 --- a/src/mainboard/amd/thatcher/Makefile.inc +++ b/src/mainboard/amd/thatcher/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/amd/thatcher/bootblock.c b/src/mainboard/amd/thatcher/bootblock.c new file mode 100644 index 0000000..d251025 --- /dev/null +++ b/src/mainboard/amd/thatcher/bootblock.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/acpimmio.h> +#include <bootblock_common.h> +#include <stdint.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <superio/smsc/lpc47n217/lpc47n217.h> + +#define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1) + +void bootblock_mainboard_early_init(void) +{ + post_code(0x30); + post_code(0x31); + + gpio_100_write8(0x1, 0x98); + + /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ + pm_write8(0xea, 0x1); + + lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c deleted file mode 100644 index dff516c..0000000 --- a/src/mainboard/amd/thatcher/romstage.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <amdblocks/acpimmio.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <console/console.h> -#include <device/pci_ops.h> -#include <amdblocks/acpimmio.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/agesa/hudson/hudson.h> -#include <superio/smsc/lpc47n217/lpc47n217.h> - -#define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1) - -void board_BeforeAgesa(struct sysinfo *cb) -{ - u8 byte; - pci_devfn_t dev; - - /* Set LPC decode enables. */ - dev = PCI_DEV(0, 0x14, 3); - - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - - post_code(0x30); - /* For serial port. */ - pci_write_config32(dev, 0x44, 0xff03ffd5); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - - post_code(0x31); - lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - pm_io_write8(0x24, 1); - pm_io_write8(0xea, 1); - gpio_100_write8(0x1, 0x98); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/38877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I948eeaaeb7975561fffc1218c70dba6a784101fe Gerrit-Change-Number: 38877 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: [TESTME]mb/bap/ode_e20XX: Switch away from ROMCC_BOOTBLOCK
by Mike Banon (Code Review) 24 Feb '20

24 Feb '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38869 ) Change subject: [TESTME]mb/bap/ode_e20XX: Switch away from ROMCC_BOOTBLOCK ...................................................................... [TESTME]mb/bap/ode_e20XX: Switch away from ROMCC_BOOTBLOCK Warning: not tested on hardware. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I37a1a95bdf07d99916247095a5bc3ac5349cd98f --- M src/mainboard/bap/ode_e20XX/Kconfig M src/mainboard/bap/ode_e20XX/Kconfig.name M src/mainboard/bap/ode_e20XX/Makefile.inc R src/mainboard/bap/ode_e20XX/bootblock.c 4 files changed, 7 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/38869/1 diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index 2a72deb..4df74c0 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -14,14 +14,10 @@ # GNU General Public License for more details. # -config BOARD_ODE_E20XX - def_bool n - if BOARD_ODE_E20XX config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/bap/ode_e20XX/Kconfig.name b/src/mainboard/bap/ode_e20XX/Kconfig.name index 54ddcac..a482846 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig.name +++ b/src/mainboard/bap/ode_e20XX/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_ODE_E20XX -# bool"ODE_e20xx" +config BOARD_ODE_E20XX + bool "ODE_e20xx" diff --git a/src/mainboard/bap/ode_e20XX/Makefile.inc b/src/mainboard/bap/ode_e20XX/Makefile.inc index 4d8eb8d..8747d2f 100644 --- a/src/mainboard/bap/ode_e20XX/Makefile.inc +++ b/src/mainboard/bap/ode_e20XX/Makefile.inc @@ -14,6 +14,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/bootblock.c similarity index 61% rename from src/mainboard/bap/ode_e20XX/romstage.c rename to src/mainboard/bap/ode_e20XX/bootblock.c index c1b96f12..8744547 100644 --- a/src/mainboard/bap/ode_e20XX/romstage.c +++ b/src/mainboard/bap/ode_e20XX/bootblock.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects - * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -15,26 +11,17 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <amdblocks/acpimmio.h> -#include <device/pci_ops.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -#include <northbridge/amd/agesa/state_machine.h> +#include <bootblock_common.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81866d/f81866d.h> - #define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ - pm_io_write(0xea, 1); - - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); + pm_write8(0xea, 0x1); fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); } -- To view, visit https://review.coreboot.org/c/coreboot/+/38869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37a1a95bdf07d99916247095a5bc3ac5349cd98f Gerrit-Change-Number: 38869 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: [TESTME]mb/lippert/toucan-af: Switch away from ROMCC_BOOTBLOCK
by Mike Banon (Code Review) 24 Feb '20

24 Feb '20

Hello HAOUAS Elyes, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38878 to review the following change. Change subject: [TESTME]mb/lippert/toucan-af: Switch away from ROMCC_BOOTBLOCK ...................................................................... [TESTME]mb/lippert/toucan-af: Switch away from ROMCC_BOOTBLOCK Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I22774a6d6a32c2fb8340f5ac678befe0d5f8ad75 --- M src/mainboard/lippert/toucan-af/Kconfig M src/mainboard/lippert/toucan-af/Kconfig.name M src/mainboard/lippert/toucan-af/Makefile.inc R src/mainboard/lippert/toucan-af/bootblock.c 4 files changed, 6 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/38878/1 diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index b62da2e..74b335a 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -13,14 +13,10 @@ # GNU General Public License for more details. # -config BOARD_LIPPERT_TOUCAN_AF - def_bool n - if BOARD_LIPPERT_TOUCAN_AF config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/lippert/toucan-af/Kconfig.name b/src/mainboard/lippert/toucan-af/Kconfig.name index 6eceb51..3481f92 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig.name +++ b/src/mainboard/lippert/toucan-af/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_LIPPERT_TOUCAN_AF -# bool"Toucan-AF aka cExpress-GFR (+W83627DHG SIO)" +config BOARD_LIPPERT_TOUCAN_AF + bool "Toucan-AF aka cExpress-GFR (+W83627DHG SIO)" diff --git a/src/mainboard/lippert/toucan-af/Makefile.inc b/src/mainboard/lippert/toucan-af/Makefile.inc index 1080c64..7e4f280 100644 --- a/src/mainboard/lippert/toucan-af/Makefile.inc +++ b/src/mainboard/lippert/toucan-af/Makefile.inc @@ -20,6 +20,8 @@ pci$(stripped_ahcibios_id).rom-type := optionrom endif +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/bootblock.c similarity index 84% rename from src/mainboard/lippert/toucan-af/romstage.c rename to src/mainboard/lippert/toucan-af/bootblock.c index ebbe4fc..39b108e 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/bootblock.c @@ -13,15 +13,13 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/state_machine.h> +#include <bootblock_common.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> -#include <sb_cimx.h> #define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1) -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { - sb_Poweron_Init(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } -- To view, visit https://review.coreboot.org/c/coreboot/+/38878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22774a6d6a32c2fb8340f5ac678befe0d5f8ad75 Gerrit-Change-Number: 38878 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: [TESTME]mb/jetway/nf81-t56n-lf: Switch away from ROMCC_BOOTBLOCK
by Mike Banon (Code Review) 24 Feb '20

24 Feb '20

Hello HAOUAS Elyes, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38874 to review the following change. Change subject: [TESTME]mb/jetway/nf81-t56n-lf: Switch away from ROMCC_BOOTBLOCK ...................................................................... [TESTME]mb/jetway/nf81-t56n-lf: Switch away from ROMCC_BOOTBLOCK Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I2ccdb10b7e06e4c159b5a0203131f6ac4c37aacf --- M src/mainboard/jetway/nf81-t56n-lf/Kconfig M src/mainboard/jetway/nf81-t56n-lf/Kconfig.name M src/mainboard/jetway/nf81-t56n-lf/Makefile.inc R src/mainboard/jetway/nf81-t56n-lf/bootblock.c 4 files changed, 6 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/38874/1 diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index dfa01b9..d2dda67 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -14,14 +14,10 @@ # GNU General Public License for more details. # -config BOARD_JETWAY_NF81_T56N_LF - def_bool n - if BOARD_JETWAY_NF81_T56N_LF config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name b/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name index 0b67627..2e660f9 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_JETWAY_NF81_T56N_LF -# bool"NF81_T56N_LF" +config BOARD_JETWAY_NF81_T56N_LF + bool "NF81_T56N_LF" diff --git a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc index ba56286..bf86007 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc +++ b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc @@ -20,6 +20,8 @@ pci$(stripped_ahcibios_id).rom-type := optionrom endif +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/bootblock.c similarity index 87% rename from src/mainboard/jetway/nf81-t56n-lf/romstage.c rename to src/mainboard/jetway/nf81-t56n-lf/bootblock.c index 5e61bdd..5ecfaf7 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/bootblock.c @@ -14,16 +14,14 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/state_machine.h> +#include <bootblock_common.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71869ad/f71869ad.h> -#include <sb_cimx.h> /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1) -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { - sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } -- To view, visit https://review.coreboot.org/c/coreboot/+/38874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ccdb10b7e06e4c159b5a0203131f6ac4c37aacf Gerrit-Change-Number: 38874 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: [TESTME]mb/amd/olivehill: Switch away from ROMCC_BOOTBLOCK
by Mike Banon (Code Review) 24 Feb '20

24 Feb '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38867 ) Change subject: [TESTME]mb/amd/olivehill: Switch away from ROMCC_BOOTBLOCK ...................................................................... [TESTME]mb/amd/olivehill: Switch away from ROMCC_BOOTBLOCK Warning: not tested on hardware. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: If8dd531db4a4a16ad7a068ceb281a01f4f245386 --- M src/mainboard/amd/olivehill/Kconfig M src/mainboard/amd/olivehill/Kconfig.name M src/mainboard/amd/olivehill/Makefile.inc A src/mainboard/amd/olivehill/bootblock.c D src/mainboard/amd/olivehill/romstage.c 5 files changed, 33 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/38867/1 diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index 78f768f..bd3dd93 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -13,14 +13,10 @@ # GNU General Public License for more details. # -config BOARD_AMD_OLIVEHILL - def_bool n - if BOARD_AMD_OLIVEHILL config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/amd/olivehill/Kconfig.name b/src/mainboard/amd/olivehill/Kconfig.name index d065472..fd1a713 100644 --- a/src/mainboard/amd/olivehill/Kconfig.name +++ b/src/mainboard/amd/olivehill/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_AMD_OLIVEHILL -# bool"Olive Hill" +config BOARD_AMD_OLIVEHILL + bool "Olive Hill" diff --git a/src/mainboard/amd/olivehill/Makefile.inc b/src/mainboard/amd/olivehill/Makefile.inc index f8895fa..4dde2cf 100644 --- a/src/mainboard/amd/olivehill/Makefile.inc +++ b/src/mainboard/amd/olivehill/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/amd/olivehill/bootblock.c b/src/mainboard/amd/olivehill/bootblock.c new file mode 100644 index 0000000..d1f8d60 --- /dev/null +++ b/src/mainboard/amd/olivehill/bootblock.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/acpimmio.h> +#include <bootblock_common.h> +#include <device/pnp_ops.h> + +void bootblock_mainboard_early_init(void) +{ + int i; + u32 val; + + /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ + pm_write8(0xea, 0x1); + + /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ + for (i = 0; i < 200000; i++) + val = inb(0xcd6); +} diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c deleted file mode 100644 index dfe7c49..0000000 --- a/src/mainboard/amd/olivehill/romstage.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <amdblocks/acpimmio.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pci_ops.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -void board_BeforeAgesa(struct sysinfo *cb) -{ - int i; - u32 val; - - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - pm_io_write8(0xd2, 0); - - /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ - pm_io_write8(0xea, 1); - - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - - /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ - for (i = 0; i < 200000; i++) - val = inb(0xcd6); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/38867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8dd531db4a4a16ad7a068ceb281a01f4f245386 Gerrit-Change-Number: 38867 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: [TESTME]src/mb/hp/abm: Switch away from ROMCC_BOOTBLOCK
by Mike Banon (Code Review) 24 Feb '20

24 Feb '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38866 ) Change subject: [TESTME]src/mb/hp/abm: Switch away from ROMCC_BOOTBLOCK ...................................................................... [TESTME]src/mb/hp/abm: Switch away from ROMCC_BOOTBLOCK Warning: not tested on hardware. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ifb50fd22f5ef4db204a3427e03430177cad211cd --- M src/mainboard/hp/abm/Kconfig M src/mainboard/hp/abm/Kconfig.name M src/mainboard/hp/abm/Makefile.inc A src/mainboard/hp/abm/bootblock.c D src/mainboard/hp/abm/romstage.c 5 files changed, 43 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/38866/1 diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig index 907c025..f4883b0 100644 --- a/src/mainboard/hp/abm/Kconfig +++ b/src/mainboard/hp/abm/Kconfig @@ -14,14 +14,10 @@ # GNU General Public License for more details. # -config BOARD_HP_ABM - def_bool n - if BOARD_HP_ABM config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/hp/abm/Kconfig.name b/src/mainboard/hp/abm/Kconfig.name index 27eda0c..4ace573 100644 --- a/src/mainboard/hp/abm/Kconfig.name +++ b/src/mainboard/hp/abm/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_HP_ABM -# bool"ABM" +config BOARD_HP_ABM + bool "ABM" diff --git a/src/mainboard/hp/abm/Makefile.inc b/src/mainboard/hp/abm/Makefile.inc index f8895fa..4dde2cf 100644 --- a/src/mainboard/hp/abm/Makefile.inc +++ b/src/mainboard/hp/abm/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/hp/abm/bootblock.c b/src/mainboard/hp/abm/bootblock.c new file mode 100644 index 0000000..a48ba77 --- /dev/null +++ b/src/mainboard/hp/abm/bootblock.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/acpimmio.h> +#include <bootblock_common.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct5104d/nct5104d.h> + +#define SERIAL_DEV PNP_DEV(0x4E, NCT5104D_SP4) + +void bootblock_mainboard_early_init(void) +{ + u32 reg32; + + /* Set auxiliary output clock frequency on OSCOUT1 pin to be 25MHz */ + /* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */ + reg32 = misc_read32(0x28); + reg32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16] + reg32 |= 0x00010000; // Set bit 16 for 25MHz + misc_write32(0x28, reg32); + + /* Enable Auxiliary OSCOUT1/OSCOUT2 */ + reg32 = misc_read32(0x40); + reg32 &= 0xffffff7b; // clear 2, 7 + misc_write32(0x40, reg32); + + nct5104d_enable_uartd(SERIAL_DEV); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c deleted file mode 100644 index 5092e17..0000000 --- a/src/mainboard/hp/abm/romstage.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <amdblocks/acpimmio.h> -#include <arch/io.h> -#include <device/pci_ops.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/agesa/hudson/hudson.h> -#include <amdblocks/acpimmio.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct5104d/nct5104d.h> - -#define SERIAL_DEV PNP_DEV(0x4E, NCT5104D_SP4) - -void board_BeforeAgesa(struct sysinfo *cb) -{ - u32 t32; - - /* For serial port option, plug-in card on LPC. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - pm_io_write8(0xd2, 0); - - /* Enable the AcpiMmio space */ - pm_io_write8(0x24, 1); - - /* Set auxiliary output clock frequency on OSCOUT1 pin to be 25MHz */ - /* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */ - t32 = misc_read32(0x28); - t32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16] - t32 |= 0x00010000; // Set bit 16 for 25MHz - misc_write(0x28, t32); - - /* Enable Auxiliary OSCOUT1/OSCOUT2 */ - t32 = misc_write32(0x40, misc_read32(0x40) & 0xffffff7b); - - nct5104d_enable_uartd(SERIAL_DEV); - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/38866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb50fd22f5ef4db204a3427e03430177cad211cd Gerrit-Change-Number: 38866 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: superio/aspeed/ast2400: drop non-onetime-config registers for iLPC2AHB
by Felix Held (Code Review) 24 Feb '20

24 Feb '20

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39093 ) Change subject: superio/aspeed/ast2400: drop non-onetime-config registers for iLPC2AHB ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/39093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d7f16845c755592317f140cca66cca12032f7a6 Gerrit-Change-Number: 39093 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 24 Feb 2020 13:30:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2020