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Change in coreboot[master]: mb/google: Fix typos
by HAOUAS Elyes (Code Review) 24 Feb '20

24 Feb '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39081 ) Change subject: mb/google: Fix typos ...................................................................... mb/google: Fix typos Change-Id: I77c33c19b56dc9bd54e7555ce59f6a07bde3dbb6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h M src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h M src/mainboard/google/auron/variants/buddy/include/variant/hda_verb.h M src/mainboard/google/auron/variants/buddy/pei_data.c M src/mainboard/google/auron/variants/buddy/variant.c M src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h M src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h M src/mainboard/google/beltino/variants/mccloud/hda_verb.c M src/mainboard/google/beltino/variants/monroe/hda_verb.c M src/mainboard/google/beltino/variants/panther/hda_verb.c M src/mainboard/google/beltino/variants/tricky/hda_verb.c M src/mainboard/google/beltino/variants/zako/hda_verb.c M src/mainboard/google/jecht/hda_verb.c M src/mainboard/google/parrot/hda_verb.c M src/mainboard/google/slippy/variants/falco/hda_verb.c M src/mainboard/google/slippy/variants/leon/hda_verb.c M src/mainboard/google/slippy/variants/peppy/hda_verb.c M src/mainboard/google/slippy/variants/wolf/hda_verb.c 18 files changed, 19 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/39081/1 diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h index 520879b..d560ccf 100644 --- a/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h @@ -72,7 +72,7 @@ /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, Internal, Location N/A AZALIA_PIN_CFG(0, 0x1D, 0x4015812d), diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h index 31b97a0..7091321 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h @@ -68,7 +68,7 @@ /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, Internal, Location N/A AZALIA_PIN_CFG(0, 0x1D, 0x4015812d), diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/buddy/include/variant/hda_verb.h index 7fd9853..7d0af93 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/buddy/include/variant/hda_verb.h @@ -85,7 +85,7 @@ /* Pin Complex (NID 0x1D) PCBeep */ 0x01d71c2d, // eapd low on ex-amp, laptop, custom enable 0x01d71d81, // mute spkr on hpout - 0x01d71e15, // pcbeep en able, checksum + 0x01d71e15, // pcbeep enable, checksum 0x01d71f40, // no physical, Internal, Location N/A /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/ diff --git a/src/mainboard/google/auron/variants/buddy/pei_data.c b/src/mainboard/google/auron/variants/buddy/pei_data.c index f346372..a0436ecc 100644 --- a/src/mainboard/google/auron/variants/buddy/pei_data.c +++ b/src/mainboard/google/auron/variants/buddy/pei_data.c @@ -32,7 +32,7 @@ /* P2: Rear USB3.0 port, USB3R2 */ pei_data_usb2_port(pei_data, 2, 0x0080, 1, 1, USB_PORT_INTERNAL); - /* P3: Card Rearder, CRS1 */ + /* P3: Card Reader, CRS1 */ pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL); /* P4: Rear USB2.0 port, USB2R1 */ @@ -54,6 +54,6 @@ pei_data_usb3_port(pei_data, 1, 1, 0, 0); /* P3: Rear USB3.0 port, USB3R2 */ pei_data_usb3_port(pei_data, 2, 1, 1, 0); - /* P4: Card Rearder, CRS1 */ + /* P4: Card Reader, CRS1 */ pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); } diff --git a/src/mainboard/google/auron/variants/buddy/variant.c b/src/mainboard/google/auron/variants/buddy/variant.c index 58fee1e..4e05711 100644 --- a/src/mainboard/google/auron/variants/buddy/variant.c +++ b/src/mainboard/google/auron/variants/buddy/variant.c @@ -179,7 +179,7 @@ /* * Battery life time - LAN PCIe should enter ASPM L1 to save * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 + * enable CLKREQ: LAN PCI config space 0x81h=01 */ pci_write_config8(ethernet_dev, 0x81, 0x01); } diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h index 4841974..23e9146 100644 --- a/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h @@ -72,7 +72,7 @@ /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, Internal, Location N/A AZALIA_PIN_CFG(0, 0x1D, 0x4015812d), diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h index e00d5b0..cfc279a 100644 --- a/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h @@ -72,7 +72,7 @@ /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, Internal, Location N/A AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), diff --git a/src/mainboard/google/beltino/variants/mccloud/hda_verb.c b/src/mainboard/google/beltino/variants/mccloud/hda_verb.c index 14f1410..57e5fa2 100644 --- a/src/mainboard/google/beltino/variants/mccloud/hda_verb.c +++ b/src/mainboard/google/beltino/variants/mccloud/hda_verb.c @@ -59,7 +59,7 @@ /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, internal AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), diff --git a/src/mainboard/google/beltino/variants/monroe/hda_verb.c b/src/mainboard/google/beltino/variants/monroe/hda_verb.c index 964687c..0e71960 100644 --- a/src/mainboard/google/beltino/variants/monroe/hda_verb.c +++ b/src/mainboard/google/beltino/variants/monroe/hda_verb.c @@ -55,7 +55,7 @@ /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, internal AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), diff --git a/src/mainboard/google/beltino/variants/panther/hda_verb.c b/src/mainboard/google/beltino/variants/panther/hda_verb.c index 14f1410..57e5fa2 100644 --- a/src/mainboard/google/beltino/variants/panther/hda_verb.c +++ b/src/mainboard/google/beltino/variants/panther/hda_verb.c @@ -59,7 +59,7 @@ /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, internal AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), diff --git a/src/mainboard/google/beltino/variants/tricky/hda_verb.c b/src/mainboard/google/beltino/variants/tricky/hda_verb.c index 14f1410..57e5fa2 100644 --- a/src/mainboard/google/beltino/variants/tricky/hda_verb.c +++ b/src/mainboard/google/beltino/variants/tricky/hda_verb.c @@ -59,7 +59,7 @@ /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, internal AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), diff --git a/src/mainboard/google/beltino/variants/zako/hda_verb.c b/src/mainboard/google/beltino/variants/zako/hda_verb.c index 14f1410..57e5fa2 100644 --- a/src/mainboard/google/beltino/variants/zako/hda_verb.c +++ b/src/mainboard/google/beltino/variants/zako/hda_verb.c @@ -59,7 +59,7 @@ /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, internal AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), diff --git a/src/mainboard/google/jecht/hda_verb.c b/src/mainboard/google/jecht/hda_verb.c index 535e7e8..0b0127e 100644 --- a/src/mainboard/google/jecht/hda_verb.c +++ b/src/mainboard/google/jecht/hda_verb.c @@ -59,7 +59,7 @@ /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, internal AZALIA_PIN_CFG(0, 0x1D, 0x4015812d), diff --git a/src/mainboard/google/parrot/hda_verb.c b/src/mainboard/google/parrot/hda_verb.c index c91cd29..e22f6ed 100644 --- a/src/mainboard/google/parrot/hda_verb.c +++ b/src/mainboard/google/parrot/hda_verb.c @@ -78,7 +78,7 @@ /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, internal AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), diff --git a/src/mainboard/google/slippy/variants/falco/hda_verb.c b/src/mainboard/google/slippy/variants/falco/hda_verb.c index 02d3907..745a3a7 100644 --- a/src/mainboard/google/slippy/variants/falco/hda_verb.c +++ b/src/mainboard/google/slippy/variants/falco/hda_verb.c @@ -63,7 +63,7 @@ /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, internal AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), diff --git a/src/mainboard/google/slippy/variants/leon/hda_verb.c b/src/mainboard/google/slippy/variants/leon/hda_verb.c index 6e01ca5..13fbb4d 100644 --- a/src/mainboard/google/slippy/variants/leon/hda_verb.c +++ b/src/mainboard/google/slippy/variants/leon/hda_verb.c @@ -63,7 +63,7 @@ /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, Internal, Location N/A AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), diff --git a/src/mainboard/google/slippy/variants/peppy/hda_verb.c b/src/mainboard/google/slippy/variants/peppy/hda_verb.c index 4d6ef34..0b1b69c 100644 --- a/src/mainboard/google/slippy/variants/peppy/hda_verb.c +++ b/src/mainboard/google/slippy/variants/peppy/hda_verb.c @@ -67,7 +67,7 @@ /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, Internal, Location N/A AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), diff --git a/src/mainboard/google/slippy/variants/wolf/hda_verb.c b/src/mainboard/google/slippy/variants/wolf/hda_verb.c index 11ff65b..e1eb5ed 100644 --- a/src/mainboard/google/slippy/variants/wolf/hda_verb.c +++ b/src/mainboard/google/slippy/variants/wolf/hda_verb.c @@ -68,7 +68,7 @@ /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable // mute spkr on hpout - // pcbeep en able, checksum + // pcbeep enable, checksum // no physical, Internal, Location N/A AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), -- To view, visit https://review.coreboot.org/c/coreboot/+/39081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77c33c19b56dc9bd54e7555ce59f6a07bde3dbb6 Gerrit-Change-Number: 39081 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: mb/amd: Fix typos
by HAOUAS Elyes (Code Review) 24 Feb '20

24 Feb '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39080 ) Change subject: mb/amd: Fix typos ...................................................................... mb/amd: Fix typos Change-Id: I9abc0837b72b13e7614ecffa5b21c3d4bf41d0f8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/amd/gardenia/irq_tables.c M src/mainboard/amd/padmelon/gpio.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39080/1 diff --git a/src/mainboard/amd/gardenia/irq_tables.c b/src/mainboard/amd/gardenia/irq_tables.c index 66dafb7..2aefaea 100644 --- a/src/mainboard/amd/gardenia/irq_tables.c +++ b/src/mainboard/amd/gardenia/irq_tables.c @@ -76,7 +76,7 @@ pirq_info = (void *)(&pirq->checksum + 1); slot_num = 0; - /* pci bridge */ + /* PCI bridge */ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); diff --git a/src/mainboard/amd/padmelon/gpio.c b/src/mainboard/amd/padmelon/gpio.c index df53c4a..09e580e 100644 --- a/src/mainboard/amd/padmelon/gpio.c +++ b/src/mainboard/amd/padmelon/gpio.c @@ -24,7 +24,7 @@ * ramstage. */ static const struct soc_amd_gpio gpio_set_stage_reset[] = { - /* GFX presense detect */ + /* GFX presence detect */ PAD_GPI(GPIO_9, PULL_DOWN), /* VDDP_VCTRL */ PAD_GPO(GPIO_40, HIGH), -- To view, visit https://review.coreboot.org/c/coreboot/+/39080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9abc0837b72b13e7614ecffa5b21c3d4bf41d0f8 Gerrit-Change-Number: 39080 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: Documentation: getting_started/gpio.md - fix quotes
by Ivan Labáth (Code Review) 24 Feb '20

24 Feb '20

Ivan Labáth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39082 ) Change subject: Documentation: getting_started/gpio.md - fix quotes ...................................................................... Documentation: getting_started/gpio.md - fix quotes Change-Id: I2c61770d60a4f290fd8d516850f16bc3808ad48d Signed-off-by: Ivan Labáth <iger(a)labo.rs> --- M Documentation/getting_started/gpio.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/39082/1 diff --git a/Documentation/getting_started/gpio.md b/Documentation/getting_started/gpio.md index 26939ce..81a06eb 100644 --- a/Documentation/getting_started/gpio.md +++ b/Documentation/getting_started/gpio.md @@ -25,7 +25,7 @@ based on a baseboard/variant model, where several variant mainboards may share a lot of their circuitry and ICs and the commonality between the boards is collected into a virtual ``baseboard.`` In that case, the GPIOs which are shared -between multiple boards are placed in the baseboard's ``gpio.c` file, while the +between multiple boards are placed in the baseboard's ``gpio.c`` file, while the ones that are board-specific go into each variant's ``gpio.c`` file. ## Intel SoCs -- To view, visit https://review.coreboot.org/c/coreboot/+/39082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c61770d60a4f290fd8d516850f16bc3808ad48d Gerrit-Change-Number: 39082 Gerrit-PatchSet: 1 Gerrit-Owner: Ivan Labáth <iger(a)labo.rs> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: src: capitalize 'RAM'
by HAOUAS Elyes (Code Review) 24 Feb '20

24 Feb '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39029 ) Change subject: src: capitalize 'RAM' ...................................................................... src: capitalize 'RAM' Change-Id: Ia05cb2de1b9f2a36fc9ecc22fb82f0c14da00a76 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/commonlib/include/commonlib/timestamp_serialized.h M src/cpu/intel/microcode/Kconfig M src/drivers/intel/fsp1_1/exit_car.S M src/drivers/intel/fsp2_0/Kconfig M src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex M src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex M src/mainboard/hp/snb_ivb_laptops/Makefile.inc M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/soc/intel/apollolake/glk_page_map.txt M src/soc/intel/denverton_ns/Kconfig 15 files changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/39029/1 diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index d7d636e..ca72734 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -156,8 +156,8 @@ /* Marker to report base_time. */ { 0, "1st timestamp" }, { TS_START_ROMSTAGE, "start of romstage" }, - { TS_BEFORE_INITRAM, "before ram initialization" }, - { TS_AFTER_INITRAM, "after ram initialization" }, + { TS_BEFORE_INITRAM, "before RAM initialization" }, + { TS_AFTER_INITRAM, "after RAM initialization" }, { TS_END_ROMSTAGE, "end of romstage" }, { TS_START_VBOOT, "start of verified boot" }, { TS_END_VBOOT, "end of verified boot" }, diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig index 238aad7..c7bbecb 100644 --- a/src/cpu/intel/microcode/Kconfig +++ b/src/cpu/intel/microcode/Kconfig @@ -4,4 +4,4 @@ default y help Select this option if you want to update the microcode - during the cache as ram setup. + during the cache as RAM setup. diff --git a/src/drivers/intel/fsp1_1/exit_car.S b/src/drivers/intel/fsp1_1/exit_car.S index 4b2822a..a8db68a 100644 --- a/src/drivers/intel/fsp1_1/exit_car.S +++ b/src/drivers/intel/fsp1_1/exit_car.S @@ -17,7 +17,7 @@ chipset_teardown_car: pop %ebx - /* Move the stack pointer to real ram */ + /* Move the stack pointer to real RAM */ movl post_car_stack_top, %esp /* Align the stack 16 bytes */ andl $0xfffffff0, %esp diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index a8b3ac4..2d45343 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -61,7 +61,7 @@ and FSP_FD_PATH correctly so FSP splitting works. config FSP_T_FILE - string "Intel FSP-T (temp ram init) binary path and filename" + string "Intel FSP-T (temp RAM init) binary path and filename" depends on FSP_CAR default "$(obj)/Fsp_T.fd" if FSP_USE_REPO help diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex b/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex index 111310a..f3e3e75 100644 --- a/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex +++ b/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex @@ -15,7 +15,7 @@ # GNU General Public License for more details. # Memory chip: Hynix H5TQ4G63MFR-PBC with ECC -# BAP ODE E20XX has 2GB ram soldered down on the Q7 +# BAP ODE E20XX has 2GB RAM soldered down on the Q7 # Memory setting for DDR-1066 # 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex b/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex index ba3d5ac..6e90bfa 100644 --- a/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex +++ b/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex @@ -15,7 +15,7 @@ # GNU General Public License for more details. # Memory chip: Hynix H5TQ4G63MFR-PBC with ECC -# BAP ODE E20XX has 2GB ram soldered down on the Q7 +# BAP ODE E20XX has 2GB RAM soldered down on the Q7 # Memory setting for DDR-800 # 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage diff --git a/src/mainboard/hp/snb_ivb_laptops/Makefile.inc b/src/mainboard/hp/snb_ivb_laptops/Makefile.inc index d949ad8..50cea25 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Makefile.inc +++ b/src/mainboard/hp/snb_ivb_laptops/Makefile.inc @@ -20,5 +20,5 @@ ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads -# FIXME: Other variants with same size onboard ram may exist. +# FIXME: Other variants with same size onboard RAM may exist. SPD_SOURCES = hynix_4g diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index d34820e..33abc51 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -133,8 +133,8 @@ { uintptr_t top_of_ram; - /* Cache 8 MiB region below the top of ram and 2 MiB above top of - * ram to cover both cbmem as the TSEG region. + /* Cache 8 MiB region below the top of RAM and 2 MiB above top of + * RAM to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 5414120..83157d8 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -99,8 +99,8 @@ { uintptr_t top_of_ram; - /* Cache 8 MiB region below the top of ram and 2 MiB above top of - * ram to cover both cbmem as the TSEG region. + /* Cache 8 MiB region below the top of RAM and 2 MiB above top of + * RAM to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index 0aa70cd..9fde9f7 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -149,8 +149,8 @@ { uintptr_t top_of_ram; - /* Cache 8 MiB region below the top of ram and 2 MiB above top of - * ram to cover both cbmem as the TSEG region. + /* Cache 8 MiB region below the top of RAM and 2 MiB above top of + * RAM to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 6ebd7e0..0784c11 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -58,12 +58,12 @@ top_of_ram = (uintptr_t)cbmem_top(); /* Cache 8MiB below the top of ram. On sandybridge systems the top of - * ram under 4GiB is the start of the TSEG region. It is required to + * RAM under 4GiB is the start of the TSEG region. It is required to * be 8MiB aligned. Set this area as cacheable so it can be used later * for ramstage before setting up the entire RAM as cacheable. */ postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); - /* Cache 8MiB at the top of ram. Top of ram on sandybridge systems + /* Cache 8MiB at the top of ram. Top of RAM on sandybridge systems * is where the TSEG region resides. However, it is not restricted * to SMM mode until SMM has been relocated. By setting the region * to cacheable it provides faster access when relocating the SMM diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index 1924ddf..334e6c7 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -144,8 +144,8 @@ { uintptr_t top_of_ram; - /* Cache 8 MiB region below the top of ram and 2 MiB above top of - * ram to cover both cbmem as the TSEG region. + /* Cache 8 MiB region below the top of RAM and 2 MiB above top of + * RAM to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index dd48d8a..1e871c7 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1636,7 +1636,7 @@ dual_channel_size = MIN(size_ch0, size_ch1) * 2; } else { if (size_ch0 == 0) { - /* ME needs ram on CH0 */ + /* ME needs RAM on CH0 */ size_me = 0; /* TOTEST: bailout? */ } else { diff --git a/src/soc/intel/apollolake/glk_page_map.txt b/src/soc/intel/apollolake/glk_page_map.txt index e96a2db..1a5f11f 100644 --- a/src/soc/intel/apollolake/glk_page_map.txt +++ b/src/soc/intel/apollolake/glk_page_map.txt @@ -1,7 +1,7 @@ 0x00000000, 0x100000000, WB, # RAM # Above entry is needed because below 4G allocated memory range is # only known after FSP memory init completes. However, FSP migrates to memory -# from cache as ram before it exits FSP Memory Init. Hence we need to add +# from cache as RAM before it exits FSP Memory Init. Hence we need to add # page table entries for this entire range before FSP Memory Init. The # overlapped MMIO ranges will be overridden by below entries. 0xd0000000, 0x100000000, UC, NX # All of MMIO diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index aed2beb..9a61127 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -59,7 +59,7 @@ default 0xe0000000 config FSP_T_ADDR - hex "Intel FSP-T (temp ram init) binary location" + hex "Intel FSP-T (temp RAM init) binary location" depends on ADD_FSP_BINARIES && FSP_CAR default 0xfff30000 help -- To view, visit https://review.coreboot.org/c/coreboot/+/39029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia05cb2de1b9f2a36fc9ecc22fb82f0c14da00a76 Gerrit-Change-Number: 39029 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: superio/aspeed/ast2400: rename SWAK to SWC to match the datasheet
by Frans Hendriks (Code Review) 24 Feb '20

24 Feb '20

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39095 ) Change subject: superio/aspeed/ast2400: rename SWAK to SWC to match the datasheet ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/39095/1/src/superio/aspeed/ast2400… File src/superio/aspeed/ast2400/ast2400.h: https://review.coreboot.org/c/coreboot/+/39095/1/src/superio/aspeed/ast2400… PS1, Line 9: #define AST2400_SWC 0x4 /* System Wake-Up control */ > Keep SWAK in the comment? Would keep it. In ASpeed spec: The device is named 'System Wake-Up Control (SWC)'. Might start control with Capital 'C' -- To view, visit https://review.coreboot.org/c/coreboot/+/39095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b3a14946e37f805d1c4e3df343dfcd7f67f6dc8 Gerrit-Change-Number: 39095 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 24 Feb 2020 12:55:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: gfx: Move drivers/generic/gfx to drivers/gfx/generic
by Furquan Shaikh (Code Review) 24 Feb '20

24 Feb '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39047 ) Change subject: gfx: Move drivers/generic/gfx to drivers/gfx/generic ...................................................................... gfx: Move drivers/generic/gfx to drivers/gfx/generic This change creates gfx directory under drivers/ so that all drivers handling gfx devices can be located in the same place. In follow-up CLs, we will be adding another driver that handles gfx devices. This change also updates the names used within the driver from *generic_gfx* to *gfx_generic*. In addition to that, mainboard drallion using this driver is updated to match the correct path and Kconfig name. TEST=Verified that drallion still builds. Change-Id: I377743e0f6d770eed143c7b6041dab2a101e6252 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- D src/drivers/generic/gfx/Makefile.inc R src/drivers/gfx/generic/Kconfig A src/drivers/gfx/generic/Makefile.inc R src/drivers/gfx/generic/chip.h R src/drivers/gfx/generic/generic.c M src/mainboard/google/drallion/Kconfig M src/mainboard/google/drallion/variants/drallion/devicetree.cb 7 files changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/39047/1 diff --git a/src/drivers/generic/gfx/Makefile.inc b/src/drivers/generic/gfx/Makefile.inc deleted file mode 100644 index c31986b..0000000 --- a/src/drivers/generic/gfx/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-$(CONFIG_DRIVERS_GENERIC_GFX) += gfx.c diff --git a/src/drivers/generic/gfx/Kconfig b/src/drivers/gfx/generic/Kconfig similarity index 80% rename from src/drivers/generic/gfx/Kconfig rename to src/drivers/gfx/generic/Kconfig index 1152f5b..dcd1a8b 100644 --- a/src/drivers/generic/gfx/Kconfig +++ b/src/drivers/gfx/generic/Kconfig @@ -1,4 +1,4 @@ -config DRIVERS_GENERIC_GFX +config DRIVERS_GFX_GENERIC bool default n depends on HAVE_ACPI_TABLES diff --git a/src/drivers/gfx/generic/Makefile.inc b/src/drivers/gfx/generic/Makefile.inc new file mode 100644 index 0000000..4ffe8dc --- /dev/null +++ b/src/drivers/gfx/generic/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GFX_GENERIC) += generic.c diff --git a/src/drivers/generic/gfx/chip.h b/src/drivers/gfx/generic/chip.h similarity index 81% rename from src/drivers/generic/gfx/chip.h rename to src/drivers/gfx/generic/chip.h index ee5bd1f..5e855e3 100644 --- a/src/drivers/generic/gfx/chip.h +++ b/src/drivers/gfx/generic/chip.h @@ -13,11 +13,11 @@ * GNU General Public License for more details. */ -#ifndef __DRIVERS_GENERIC_GFX_CHIP_H__ -#define __DRIVERS_GENERIC_GFX_CHIP_H__ +#ifndef __DRIVERS_GFX_GENERIC_CHIP_H__ +#define __DRIVERS_GFX_GENERIC_CHIP_H__ /* Config for electronic privacy screen */ -struct drivers_generic_gfx_privacy_screen_config { +struct drivers_gfx_generic_privacy_screen_config { /* Is privacy screen available on this graphics device */ int enabled; /* ACPI namespace path to privacy screen detection function */ @@ -31,17 +31,17 @@ }; /* Config for an output device as defined in section A.5 of the ACPI spec */ -struct drivers_generic_gfx_device_config { +struct drivers_gfx_generic_device_config { /* ACPI device name of the output device */ const char *name; /* The address of the output device. See section A.3.2 */ unsigned int addr; /* Electronic privacy screen specific config */ - struct drivers_generic_gfx_privacy_screen_config privacy; + struct drivers_gfx_generic_privacy_screen_config privacy; }; /* Config for an ACPI video device defined in Appendix A of the ACPI spec */ -struct drivers_generic_gfx_config { +struct drivers_gfx_generic_config { /* * ACPI device name of the graphics card, "GFX0" will be used if name is * not set @@ -50,7 +50,7 @@ /* The number of output devices defined */ int device_count; /* Config for output devices */ - struct drivers_generic_gfx_device_config device[5]; + struct drivers_gfx_generic_device_config device[5]; }; -#endif /* __DRIVERS_GENERIC_GFX_CHIP_H__ */ +#endif /* __DRIVERS_GFX_GENERIC_CHIP_H__ */ diff --git a/src/drivers/generic/gfx/gfx.c b/src/drivers/gfx/generic/generic.c similarity index 83% rename from src/drivers/generic/gfx/gfx.c rename to src/drivers/gfx/generic/generic.c index 0386e9b..8488040 100644 --- a/src/drivers/generic/gfx/gfx.c +++ b/src/drivers/gfx/generic/generic.c @@ -26,7 +26,7 @@ static void privacy_screen_detect_cb(void *arg) { - struct drivers_generic_gfx_privacy_screen_config *config = arg; + struct drivers_gfx_generic_privacy_screen_config *config = arg; acpigen_write_store(); acpigen_emit_namestring(config->detect_function); @@ -37,20 +37,20 @@ } static void privacy_screen_get_status_cb(void *arg) { - struct drivers_generic_gfx_privacy_screen_config *config = arg; + struct drivers_gfx_generic_privacy_screen_config *config = arg; acpigen_emit_byte(RETURN_OP); acpigen_emit_namestring(config->status_function); } static void privacy_screen_enable_cb(void *arg) { - struct drivers_generic_gfx_privacy_screen_config *config = arg; + struct drivers_gfx_generic_privacy_screen_config *config = arg; acpigen_emit_namestring(config->enable_function); } static void privacy_screen_disable_cb(void *arg) { - struct drivers_generic_gfx_privacy_screen_config *config = arg; + struct drivers_gfx_generic_privacy_screen_config *config = arg; acpigen_emit_namestring(config->disable_function); } @@ -65,7 +65,7 @@ static void gfx_fill_ssdt_generator(struct device *dev) { size_t i; - struct drivers_generic_gfx_config *config = dev->chip_info; + struct drivers_gfx_generic_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); @@ -103,7 +103,7 @@ static const char *gfx_acpi_name(const struct device *dev) { - struct drivers_generic_gfx_config *config = dev->chip_info; + struct drivers_gfx_generic_config *config = dev->chip_info; return config->name ? : "GFX0"; } @@ -115,7 +115,7 @@ static void gfx_enable(struct device *dev) { - struct drivers_generic_gfx_config *config = dev->chip_info; + struct drivers_gfx_generic_config *config = dev->chip_info; if (!config) return; @@ -123,7 +123,7 @@ dev->ops = &gfx_ops; } -struct chip_operations drivers_generic_gfx_ops = { - CHIP_NAME("Graphics Device") +struct chip_operations drivers_gfx_generic_ops = { + CHIP_NAME("Generic Graphics Device") .enable_dev = gfx_enable }; diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index a006858..61bae2b 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -2,7 +2,7 @@ config BOARD_GOOGLE_BASEBOARD_DRALLION def_bool n select BOARD_ROMSIZE_KB_32768 - select DRIVERS_GENERIC_GFX + select DRIVERS_GFX_GENERIC select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_INTEL_ISH diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index cdb6288..d0006d6 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -226,7 +226,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on - chip drivers/generic/gfx + chip drivers/gfx/generic register "device_count" = "1" register "device[0].name" = ""LCD"" # Address is set following the ACPI spec section A.3.2 -- To view, visit https://review.coreboot.org/c/coreboot/+/39047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I377743e0f6d770eed143c7b6041dab2a101e6252 Gerrit-Change-Number: 39047 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: util/inteltool: Add missing entry for WPT-LP Premium
by Angel Pons (Code Review) 24 Feb '20

24 Feb '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39046 ) Change subject: util/inteltool: Add missing entry for WPT-LP Premium ...................................................................... util/inteltool: Add missing entry for WPT-LP Premium Tested on a laptop with an i7-5500U processor, the device is now found. Change-Id: I49ddec862520d0d5492d78fec89efd841c141790 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/inteltool/inteltool.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/39046/1 diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index de66811..c20aafe 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -226,8 +226,10 @@ "Lynx Point Low Power Premium SKU" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE, "Lynx Point Low Power Base SKU" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM, + "Wildcat Point Low Power Premium SKU" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP, - "Wildcat Point Low Power SKU" }, + "Wildcat Point Low Power Base SKU" }, { PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC, "Bay Trail" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE, -- To view, visit https://review.coreboot.org/c/coreboot/+/39046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49ddec862520d0d5492d78fec89efd841c141790 Gerrit-Change-Number: 39046 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: vboot: remove rogue vboot_struct.h include
by Joel Kitching (Code Review) 24 Feb '20

24 Feb '20

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39024 ) Change subject: vboot: remove rogue vboot_struct.h include ...................................................................... vboot: remove rogue vboot_struct.h include As part of vboot1 deprecation, remove an unused vboot_struct.h include. coreboot is now free of vboot1 data structure use. One vboot_api.h include remains as part of security/vboot/ec_sync.c. BUG=b:124141368 TEST=make clean && make test-abuild BRANCH=none Change-Id: I042d692aa252f8f859d4005455eb6a2eabc24a87 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/vendorcode/google/chromeos/gnvs.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/39024/1 diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 8115455..04680c0 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -22,7 +22,6 @@ #include <fmap.h> #include <security/vboot/vbnv.h> #include <security/vboot/vboot_common.h> -#include <vboot_struct.h> #include "chromeos.h" #include "gnvs.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/39024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I042d692aa252f8f859d4005455eb6a2eabc24a87 Gerrit-Change-Number: 39024 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/sarien: Remove MAC address pass through
by Dtrain Hsu (Code Review) 24 Feb '20

24 Feb '20

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39042 ) Change subject: mb/google/sarien: Remove MAC address pass through ...................................................................... mb/google/sarien: Remove MAC address pass through Remove MAC address pass through because when MAC address pass through setting change to "Use dock built-in MAC address", the MAC address always keeps the VPD value. BUG=b:149813043 TEST=tested on sarien and the result as below. (Option) (Result) - Use pre-assigned MAC address : Pass - Use Chromebook built-in address : Pass - Use dock built-in MAC address : Pass Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: Ia85ef6ed0c4db82301375edd0968cf7dd2f62dc1 --- M src/mainboard/google/sarien/dsdt.asl 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/39042/1 diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index c32470e..8acd0b5 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -48,8 +48,6 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* VPD support */ #include <vendorcode/google/chromeos/acpi/vpd.asl> - /* MAC address passthru */ - #include <vendorcode/google/chromeos/acpi/amac.asl> #endif #include <southbridge/intel/common/acpi/sleepstates.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/39042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia85ef6ed0c4db82301375edd0968cf7dd2f62dc1 Gerrit-Change-Number: 39042 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/ifdtool: Mention MeDisable in help text
by Evgeny Zinoviev (Code Review) 24 Feb '20

24 Feb '20

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38934 ) Change subject: util/ifdtool: Mention MeDisable in help text ...................................................................... util/ifdtool: Mention MeDisable in help text The -M option of ifdtool sets not only AltMeDisable bit, but also MeDisable bit in ICH0 and MCH0 straps. Make it obvious and mention in the help message. Change-Id: I9dba2fa6509a9c833f72414367944bc606671e7b Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M util/ifdtool/ifdtool.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/38934/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 2bf2f4d..1ff33c9 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -1438,8 +1438,8 @@ " Dual Output Fast Read Support\n" " -l | --lock Lock firmware descriptor and ME region\n" " -u | --unlock Unlock firmware descriptor and ME region\n" - " -M | --altmedisable <0|1> Set the AltMeDisable (or HAP for skylake or newer platform)\n" - " bit to disable ME\n" + " -M | --altmedisable <0|1> Set the MeDisable and AltMeDisable (or HAP for skylake or newer platform)\n" + " bits to disable ME\n" " -p | --platform Add platform-specific quirks\n" " aplk - Apollo Lake\n" " cnl - Cannon Lake\n" -- To view, visit https://review.coreboot.org/c/coreboot/+/38934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dba2fa6509a9c833f72414367944bc606671e7b Gerrit-Change-Number: 38934 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

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