coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: superio/aspeed/ast2400: rename SWAK to SWC to match the datasheet
by Felix Held (Code Review) 24 Feb '20

24 Feb '20

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39095 ) Change subject: superio/aspeed/ast2400: rename SWAK to SWC to match the datasheet ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/39095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b3a14946e37f805d1c4e3df343dfcd7f67f6dc8 Gerrit-Change-Number: 39095 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 24 Feb 2020 13:29:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/icelake: Avoid redundant if condition
by Subrata Banik (Code Review) 24 Feb '20

24 Feb '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38992 ) Change subject: soc/intel/icelake: Avoid redundant if condition ...................................................................... soc/intel/icelake: Avoid redundant if condition This patch overrides "GtFreqMax" and "CdClock" FSP UPD as part of existing IGD enable if condition check itself. Change-Id: Ie500dd5fad5cd358ea3fad4d5c0be1b0c148584b Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/icelake/fsp_params.c 1 file changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/38992/1 diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 448b82c..8efdb56 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -92,14 +92,16 @@ mainboard_silicon_init_params(params); dev = pcidev_path_on_root(SA_DEVFN_IGD); - if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) + if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) { params->PeiGraphicsPeimInit = 1; - else - params->PeiGraphicsPeimInit = 0; - if (dev && dev->enabled) { params->GtFreqMax = 2; params->CdClock = 3; - } + } else + /* + * Skip IGD initialization in FSP in case device is disabled + * in the devicetree.cb. + */ + params->PeiGraphicsPeimInit = 0; /* Unlock upper 8 bytes of RTC RAM */ params->PchLockDownRtcMemoryLock = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/38992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie500dd5fad5cd358ea3fad4d5c0be1b0c148584b Gerrit-Change-Number: 38992 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

7 22

Change in coreboot[master]: mb/intel/jasperlake_rvp: Disable SATA support for JSL
by Usha P (Code Review) 24 Feb '20

24 Feb '20

Usha P has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38996 ) Change subject: mb/intel/jasperlake_rvp: Disable SATA support for JSL ...................................................................... mb/intel/jasperlake_rvp: Disable SATA support for JSL This patch disables the SATA config from devicetree for JSL Change-Id: I9cbcbf96e70b79bfb60f228b77a1065c26cd1aa2 Signed-off-by: Usha P <usha.p(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb 1 file changed, 1 insertion(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/38996/1 diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 843de14..2700a41 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -66,25 +66,7 @@ # ClkReq-to-ClkSrc mapping for CLK SRC 0 register "PcieClkSrcClkReq[0]" = "0x00" - register "SataEnable" = "1" - register "SataSalpSupport" = "1" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "1" - register "SataPortsEnable[3]" = "1" - register "SataPortsEnable[4]" = "1" - register "SataPortsEnable[5]" = "1" - register "SataPortsEnable[6]" = "1" - register "SataPortsEnable[7]" = "1" - - register "SataPortsDevSlp[0]" = "1" - register "SataPortsDevSlp[1]" = "1" - register "SataPortsDevSlp[2]" = "1" - register "SataPortsDevSlp[3]" = "1" - register "SataPortsDevSlp[4]" = "1" - register "SataPortsDevSlp[5]" = "1" - register "SataPortsDevSlp[6]" = "1" - register "SataPortsDevSlp[7]" = "1" + register "SataEnable" = "0" register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, -- To view, visit https://review.coreboot.org/c/coreboot/+/38996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cbcbf96e70b79bfb60f228b77a1065c26cd1aa2 Gerrit-Change-Number: 38996 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newchange

9 15

Change in coreboot[master]: mainboard: Add missing include <device/pci_def.h>
by Mike Banon (Code Review) 24 Feb '20

24 Feb '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38903 ) Change subject: mainboard: Add missing include <device/pci_def.h> ...................................................................... mainboard: Add missing include <device/pci_def.h> Add missing include <device/pci_def.h> for the boards that are being switched away from ROMCC_BOOTBLOCK. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I83ff712f99388c4e6ea00a942eb57bcabb53a3fd --- M src/mainboard/amd/inagua/irq_tables.c M src/mainboard/amd/olivehill/irq_tables.c M src/mainboard/amd/parmer/irq_tables.c M src/mainboard/amd/persimmon/irq_tables.c M src/mainboard/amd/south_station/irq_tables.c M src/mainboard/amd/thatcher/irq_tables.c M src/mainboard/amd/union_station/irq_tables.c M src/mainboard/bap/ode_e20XX/irq_tables.c M src/mainboard/elmex/pcm205400/irq_tables.c M src/mainboard/gizmosphere/gizmo2/irq_tables.c M src/mainboard/hp/abm/irq_tables.c M src/mainboard/lippert/frontrunner-af/irq_tables.c M src/mainboard/lippert/toucan-af/irq_tables.c 13 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/38903/1 diff --git a/src/mainboard/amd/inagua/irq_tables.c b/src/mainboard/amd/inagua/irq_tables.c index a066864..1d1e81f 100644 --- a/src/mainboard/amd/inagua/irq_tables.c +++ b/src/mainboard/amd/inagua/irq_tables.c @@ -14,6 +14,7 @@ */ #include <console/console.h> +#include <device/pci_def.h> #include <string.h> #include <stdint.h> #include <arch/pirq_routing.h> diff --git a/src/mainboard/amd/olivehill/irq_tables.c b/src/mainboard/amd/olivehill/irq_tables.c index 530c132..181908a 100644 --- a/src/mainboard/amd/olivehill/irq_tables.c +++ b/src/mainboard/amd/olivehill/irq_tables.c @@ -14,6 +14,7 @@ */ #include <console/console.h> +#include <device/pci_def.h> #include <string.h> #include <stdint.h> #include <arch/pirq_routing.h> diff --git a/src/mainboard/amd/parmer/irq_tables.c b/src/mainboard/amd/parmer/irq_tables.c index 530c132..181908a 100644 --- a/src/mainboard/amd/parmer/irq_tables.c +++ b/src/mainboard/amd/parmer/irq_tables.c @@ -14,6 +14,7 @@ */ #include <console/console.h> +#include <device/pci_def.h> #include <string.h> #include <stdint.h> #include <arch/pirq_routing.h> diff --git a/src/mainboard/amd/persimmon/irq_tables.c b/src/mainboard/amd/persimmon/irq_tables.c index a066864..1d1e81f 100644 --- a/src/mainboard/amd/persimmon/irq_tables.c +++ b/src/mainboard/amd/persimmon/irq_tables.c @@ -14,6 +14,7 @@ */ #include <console/console.h> +#include <device/pci_def.h> #include <string.h> #include <stdint.h> #include <arch/pirq_routing.h> diff --git a/src/mainboard/amd/south_station/irq_tables.c b/src/mainboard/amd/south_station/irq_tables.c index a066864..1d1e81f 100644 --- a/src/mainboard/amd/south_station/irq_tables.c +++ b/src/mainboard/amd/south_station/irq_tables.c @@ -14,6 +14,7 @@ */ #include <console/console.h> +#include <device/pci_def.h> #include <string.h> #include <stdint.h> #include <arch/pirq_routing.h> diff --git a/src/mainboard/amd/thatcher/irq_tables.c b/src/mainboard/amd/thatcher/irq_tables.c index 530c132..181908a 100644 --- a/src/mainboard/amd/thatcher/irq_tables.c +++ b/src/mainboard/amd/thatcher/irq_tables.c @@ -14,6 +14,7 @@ */ #include <console/console.h> +#include <device/pci_def.h> #include <string.h> #include <stdint.h> #include <arch/pirq_routing.h> diff --git a/src/mainboard/amd/union_station/irq_tables.c b/src/mainboard/amd/union_station/irq_tables.c index a066864..1d1e81f 100644 --- a/src/mainboard/amd/union_station/irq_tables.c +++ b/src/mainboard/amd/union_station/irq_tables.c @@ -14,6 +14,7 @@ */ #include <console/console.h> +#include <device/pci_def.h> #include <string.h> #include <stdint.h> #include <arch/pirq_routing.h> diff --git a/src/mainboard/bap/ode_e20XX/irq_tables.c b/src/mainboard/bap/ode_e20XX/irq_tables.c index 530c132..181908a 100644 --- a/src/mainboard/bap/ode_e20XX/irq_tables.c +++ b/src/mainboard/bap/ode_e20XX/irq_tables.c @@ -14,6 +14,7 @@ */ #include <console/console.h> +#include <device/pci_def.h> #include <string.h> #include <stdint.h> #include <arch/pirq_routing.h> diff --git a/src/mainboard/elmex/pcm205400/irq_tables.c b/src/mainboard/elmex/pcm205400/irq_tables.c index 804f52d..d114996 100644 --- a/src/mainboard/elmex/pcm205400/irq_tables.c +++ b/src/mainboard/elmex/pcm205400/irq_tables.c @@ -15,6 +15,7 @@ #include <console/console.h> +#include <device/pci_def.h> #include <string.h> #include <stdint.h> #include <arch/pirq_routing.h> diff --git a/src/mainboard/gizmosphere/gizmo2/irq_tables.c b/src/mainboard/gizmosphere/gizmo2/irq_tables.c index 530c132..181908a 100644 --- a/src/mainboard/gizmosphere/gizmo2/irq_tables.c +++ b/src/mainboard/gizmosphere/gizmo2/irq_tables.c @@ -14,6 +14,7 @@ */ #include <console/console.h> +#include <device/pci_def.h> #include <string.h> #include <stdint.h> #include <arch/pirq_routing.h> diff --git a/src/mainboard/hp/abm/irq_tables.c b/src/mainboard/hp/abm/irq_tables.c index 530c132..181908a 100644 --- a/src/mainboard/hp/abm/irq_tables.c +++ b/src/mainboard/hp/abm/irq_tables.c @@ -14,6 +14,7 @@ */ #include <console/console.h> +#include <device/pci_def.h> #include <string.h> #include <stdint.h> #include <arch/pirq_routing.h> diff --git a/src/mainboard/lippert/frontrunner-af/irq_tables.c b/src/mainboard/lippert/frontrunner-af/irq_tables.c index a066864..1d1e81f 100644 --- a/src/mainboard/lippert/frontrunner-af/irq_tables.c +++ b/src/mainboard/lippert/frontrunner-af/irq_tables.c @@ -14,6 +14,7 @@ */ #include <console/console.h> +#include <device/pci_def.h> #include <string.h> #include <stdint.h> #include <arch/pirq_routing.h> diff --git a/src/mainboard/lippert/toucan-af/irq_tables.c b/src/mainboard/lippert/toucan-af/irq_tables.c index a066864..1d1e81f 100644 --- a/src/mainboard/lippert/toucan-af/irq_tables.c +++ b/src/mainboard/lippert/toucan-af/irq_tables.c @@ -14,6 +14,7 @@ */ #include <console/console.h> +#include <device/pci_def.h> #include <string.h> #include <stdint.h> #include <arch/pirq_routing.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/38903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83ff712f99388c4e6ea00a942eb57bcabb53a3fd Gerrit-Change-Number: 38903 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: device/Kconfig: select linear framebuffer for Tianocore
by Matt DeVillier (Code Review) 24 Feb '20

24 Feb '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39048 ) Change subject: device/Kconfig: select linear framebuffer for Tianocore ...................................................................... device/Kconfig: select linear framebuffer for Tianocore Automatically select the linear framebuffer mode option if available when Tianocore selected as payload, since VGA text mode will not work properly with the default Tianocore payload. Change-Id: Ic36fd035526f3efd00ffa12ad613fbac304b18cf Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/device/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39048/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index 603c7eb..25123ea 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -413,6 +413,8 @@ prompt "Framebuffer mode" default VBE_LINEAR_FRAMEBUFFER if HAVE_VBE_LINEAR_FRAMEBUFFER && CHROMEOS default GENERIC_LINEAR_FRAMEBUFFER if HAVE_LINEAR_FRAMEBUFFER && CHROMEOS + default VBE_LINEAR_FRAMEBUFFER if HAVE_VBE_LINEAR_FRAMEBUFFER && PAYLOAD_TIANOCORE + default GENERIC_LINEAR_FRAMEBUFFER if HAVE_LINEAR_FRAMEBUFFER && PAYLOAD_TIANOCORE default VGA_TEXT_FRAMEBUFFER config VGA_TEXT_FRAMEBUFFER -- To view, visit https://review.coreboot.org/c/coreboot/+/39048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic36fd035526f3efd00ffa12ad613fbac304b18cf Gerrit-Change-Number: 39048 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: libpayload: cbgfx: Fix potential overflowing expression
by Yu-Ping Wu (Code Review) 24 Feb '20

24 Feb '20

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38987 ) Change subject: libpayload: cbgfx: Fix potential overflowing expression ...................................................................... libpayload: cbgfx: Fix potential overflowing expression BRANCH=none BUG=none TEST=none Change-Id: Icd37a6abc01d9fcbcf54525d47b15c9930a9b9fb Signed-off-by: Yu-Ping Wu <yupingso(a)google.com> --- M payloads/libpayload/drivers/video/graphics.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/38987/1 diff --git a/payloads/libpayload/drivers/video/graphics.c b/payloads/libpayload/drivers/video/graphics.c index 8cb984b8..9494de3 100644 --- a/payloads/libpayload/drivers/video/graphics.c +++ b/payloads/libpayload/drivers/video/graphics.c @@ -349,8 +349,8 @@ /* Use 64 bits to avoid overflow */ int32_t x, y; uint64_t yy; - const uint64_t rrx = r.x * r.x, rry = r.y * r.y; - const uint64_t ssx = s.x * s.x, ssy = s.y * s.y; + const uint64_t rrx = (uint64_t)r.x * r.x, rry = (uint64_t)r.y * r.y; + const uint64_t ssx = (uint64_t)s.x * s.x, ssy = (uint64_t)s.y * s.y; x_begin = 0; x_end = 0; for (y = r.y - 1; y >= 0; y--) { @@ -358,7 +358,7 @@ * The inequality is valid in the beginning of each iteration: * y^2 + x_end^2 < r^2 */ - yy = y * y; + yy = (uint64_t)y * y; /* Check yy/ssy + xx/ssx < 1 */ while (yy * ssx + x_begin * x_begin * ssy < ssx * ssy) x_begin++; -- To view, visit https://review.coreboot.org/c/coreboot/+/38987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd37a6abc01d9fcbcf54525d47b15c9930a9b9fb Gerrit-Change-Number: 38987 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/rockchip: Fix typos
by HAOUAS Elyes (Code Review) 24 Feb '20

24 Feb '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39028 ) Change subject: soc/rockchip: Fix typos ...................................................................... soc/rockchip: Fix typos Change-Id: I85ccb9e1458340bd5bc2a0eb9abed8d0eeb2fe65 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/rockchip/common/edp.c M src/soc/rockchip/rk3288/hdmi.c M src/soc/rockchip/rk3288/tsadc.c M src/soc/rockchip/rk3399/clock.c M src/soc/rockchip/rk3399/mipi.c M src/soc/rockchip/rk3399/tsadc.c 6 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/39028/1 diff --git a/src/soc/rockchip/common/edp.c b/src/soc/rockchip/common/edp.c index 18afc3a..060099c 100644 --- a/src/soc/rockchip/common/edp.c +++ b/src/soc/rockchip/common/edp.c @@ -135,7 +135,7 @@ static void rk_edp_init_aux(struct rk_edp *edp) { - /* Clear inerrupts related to AUX channel */ + /* Clear interrupts related to AUX channel */ write32(&edp->regs->dp_int_sta, AUX_FUNC_EN_N); /* Disable AUX channel module */ diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index cd9890b..3b8c77d 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -733,7 +733,7 @@ u32 trytime = 5; u32 n, j, val; - /* set ddc i2c clk which devided from ddc_clk to 100khz */ + /* set ddc i2c clk which divided from ddc_clk to 100kHz */ write32(&hdmi_regs->i2cm_ss_scl_hcnt_0_addr, 0x7a); write32(&hdmi_regs->i2cm_ss_scl_lcnt_0_addr, 0x8d); clrsetbits32(&hdmi_regs->i2cm_div, HDMI_I2CM_DIV_FAST_STD_MODE, diff --git a/src/soc/rockchip/rk3288/tsadc.c b/src/soc/rockchip/rk3288/tsadc.c index de3d058..7a1e34d 100644 --- a/src/soc/rockchip/rk3288/tsadc.c +++ b/src/soc/rockchip/rk3288/tsadc.c @@ -100,7 +100,7 @@ /* tsadc iomux must be set after the tshut polarity setting, - since the tshut polarity defalut low active, + since the tshut polarity default low active, so if you enable tsadc iomux,it will output high */ setbits32(&rk3288_pmu->iomux_tsadc_int, IOMUX_TSADC_INT); diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 4cd2839..d2f5b7c 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -304,7 +304,7 @@ u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; printk(BIOS_DEBUG, "PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, " - "postdiv2=%d, vco=%u khz, output=%u khz\n", + "postdiv2=%d, vco=%u kHz, output=%u kHz\n", pll_con, div->fbdiv, div->refdiv, div->postdiv1, div->postdiv2, vco_khz, output_khz); assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && @@ -485,7 +485,7 @@ /* some cru registers changed by bootrom, we'd better reset them to * reset/default values described in TRM to avoid confusion in kernel. - * Please consider these threee lines as a fix of bootrom bug. + * Please consider these three lines as a fix of bootrom bug. */ write32(&cru_ptr->clksel_con[12], 0xffff4101); write32(&cru_ptr->clksel_con[19], 0xffff033f); diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c index 751c8a5..5df5fdf 100644 --- a/src/soc/rockchip/rk3399/mipi.c +++ b/src/soc/rockchip/rk3399/mipi.c @@ -319,7 +319,7 @@ min_prediv = DIV_ROUND_UP(fref, 40 * MHz); max_prediv = fref / (5 * MHz); - /* constraint: 80MHz <= Fvco <= 1500Mhz */ + /* constraint: 80MHz <= Fvco <= 1500MHz */ fvco_min = 80 * MHz; fvco_max = 1500 * MHz; min_delta = 1500 * MHz; diff --git a/src/soc/rockchip/rk3399/tsadc.c b/src/soc/rockchip/rk3399/tsadc.c index 1cdb355..9f69915 100644 --- a/src/soc/rockchip/rk3399/tsadc.c +++ b/src/soc/rockchip/rk3399/tsadc.c @@ -112,7 +112,7 @@ /* setup the automatic mode: * AUTO_PERIOD: interleave between every two accessing of TSADC - * AUTO_DEBOUNCE: only generate interrupt or TSHUT when temprature + * AUTO_DEBOUNCE: only generate interrupt or TSHUT when temperature * is higher than COMP_INT for "debounce" times * AUTO_PERIOD_HT: the interleave between every two accessing after the * temperature is higher than COMP_SHUT or COMP_INT @@ -123,7 +123,7 @@ write32(&rk3399_tsadc->hight_int_debounce, AUTO_DEBOUNCE); write32(&rk3399_tsadc->auto_period_ht, AUTO_PERIOD_HT); write32(&rk3399_tsadc->hight_tshut_debounce, AUTO_DEBOUNCE_HT); - /* Enable the src0, negative temprature coefficient */ + /* Enable the src0, negative temperature coefficient */ setbits32(&rk3399_tsadc->auto_con, Q_SEL | SRC0_EN); udelay(100); setbits32(&rk3399_tsadc->auto_con, AUTO_EN); -- To view, visit https://review.coreboot.org/c/coreboot/+/39028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85ccb9e1458340bd5bc2a0eb9abed8d0eeb2fe65 Gerrit-Change-Number: 39028 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: src/commonlib: Fix typos
by HAOUAS Elyes (Code Review) 24 Feb '20

24 Feb '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38689 ) Change subject: src/commonlib: Fix typos ...................................................................... src/commonlib: Fix typos Change-Id: Ida1770c5e4b18c536e4943eb9cf862d69196c589 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/commonlib/cbfs.c M src/commonlib/storage/sd.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/38689/1 diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c index 5c9aacb..be0de9f 100644 --- a/src/commonlib/cbfs.c +++ b/src/commonlib/cbfs.c @@ -44,7 +44,7 @@ if (f == NULL) return 0; - /* The region_device objects store absolute offets over the whole + /* The region_device objects store absolute offsets over the whole * region. Therefore a relative offset needs to be calculated. */ offset = rdev_relative_offset(cbfs, &f->data); offset += region_device_sz(&f->data); diff --git a/src/commonlib/storage/sd.c b/src/commonlib/storage/sd.c index bdb0baa..30af810 100644 --- a/src/commonlib/storage/sd.c +++ b/src/commonlib/storage/sd.c @@ -220,7 +220,7 @@ if (!((ctrlr->caps & DRVR_CAP_HS52) && (ctrlr->caps & DRVR_CAP_HS))) goto out; - /* Give the card time to recover afer the switch operation. Wait for + /* Give the card time to recover after the switch operation. Wait for * 9 (>= 8) clock cycles receiving the switch status. */ delay = (9000000 + ctrlr->bus_hz - 1) / ctrlr->bus_hz; -- To view, visit https://review.coreboot.org/c/coreboot/+/38689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida1770c5e4b18c536e4943eb9cf862d69196c589 Gerrit-Change-Number: 38689 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/{samsung,sifive}: Fix typos
by HAOUAS Elyes (Code Review) 24 Feb '20

24 Feb '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39016 ) Change subject: soc/{samsung,sifive}: Fix typos ...................................................................... soc/{samsung,sifive}: Fix typos Change-Id: Ib370f04a63160e2a8a1b06620e659feb45c8f552 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/samsung/exynos5420/spi.c M src/soc/sifive/fu540/clock.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/39016/1 diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c index a98f51d..ec90023 100644 --- a/src/soc/samsung/exynos5420/spi.c +++ b/src/soc/samsung/exynos5420/spi.c @@ -101,7 +101,7 @@ // CPOL: Active high. clrbits32(&regs->ch_cfg, SPI_CH_CPOL_L); - // Clear rx and tx channel if set priveously. + // Clear rx and tx channel if set previously. clrbits32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); setbits32(&regs->swap_cfg, diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index a15e639..ad5e06b 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -104,7 +104,7 @@ * Set coreclk according to the SiFive FU540-C000 Manual * https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/ * - * Section 7.1 recommends a frequency of 1.0 GHz (up to 1.5 Ghz is possible) + * Section 7.1 recommends a frequency of 1.0 GHz (up to 1.5 GHz is possible) * * Section 7.4.2 provides the necessary values: * For example, to setup COREPLL for 1 GHz operation, program divr = 0 (x1), -- To view, visit https://review.coreboot.org/c/coreboot/+/39016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib370f04a63160e2a8a1b06620e659feb45c8f552 Gerrit-Change-Number: 39016 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/include/amdblocks: Fix typos
by HAOUAS Elyes (Code Review) 24 Feb '20

24 Feb '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38980 ) Change subject: soc/amd/common/block/include/amdblocks: Fix typos ...................................................................... soc/amd/common/block/include/amdblocks: Fix typos Change-Id: I8363816a51c342935668545a8b39acce96ce4b2c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/common/block/include/amdblocks/gpio_banks.h M src/soc/amd/common/block/include/amdblocks/lpc.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/38980/1 diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h index 2206e35..8600e64 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h @@ -303,7 +303,7 @@ void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size); /* Return the interrupt status and clear if set. */ int gpio_interrupt_status(gpio_t gpio); -/* Implemented by soc, provides table of avaialable GPIO mapping to Gevents */ +/* Implemented by soc, provides table of available GPIO mapping to Gevents */ void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items); /* May be implemented by soc to handle special cases */ void soc_gpio_hook(uint8_t gpio, uint8_t mux); diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 2874c18..2f8cd97 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -103,7 +103,7 @@ #define LPC_MEM_PORT0 0x60 /* Register 0x64 is 32-bit, composed by two 16-bit sub-registers. - For ease of access, each sub-register is declared separetely. */ + For ease of access, each sub-register is declared separately. */ #define LPC_WIDEIO_GENERIC_PORT 0x64 #define LPC_WIDEIO1_GENERIC_PORT 0x66 #define ROM_ADDRESS_RANGE1_START 0x68 -- To view, visit https://review.coreboot.org/c/coreboot/+/38980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8363816a51c342935668545a8b39acce96ce4b2c Gerrit-Change-Number: 38980 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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