coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

1 participants
1797 discussions

Change in coreboot[master]: mb/google/drallion: Set GPP_G4 and GPP_G6 to NC pin
by EricR Lai (Code Review) 24 Feb '20

24 Feb '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38999 ) Change subject: mb/google/drallion: Set GPP_G4 and GPP_G6 to NC pin ...................................................................... mb/google/drallion: Set GPP_G4 and GPP_G6 to NC pin Follow latest HW schematics to set GPP_G4 and GPP_G6 to NC pin. This can save 1mW power comsumption. BUG=b:149289256 TEST=NA Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ib3bf8b8f922a350d2b73ef5c9e9cf1b6e2c0f657 --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/38999/1 diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index 85de173..d26abdb 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -184,9 +184,9 @@ /* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */ /* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* SD_DATA2 */ PAD_NC(GPP_G3, NONE), -/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, PLTRST), /* CTLESS_DET# */ +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), /* CTLESS_DET# */ /* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, PLTRST), /* HOST_SD_WP# */ -/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* AUD_PWR_EN */ +/* SD_CLK */ PAD_NC(GPP_G6, NONE), /* AUD_PWR_EN */ /* SD_WP */ PAD_CFG_GPI(GPP_G7, NONE, PLTRST), /* SPK_DET# */ /* I2S2_SCLK */ PAD_NC(GPP_H0, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/38999 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3bf8b8f922a350d2b73ef5c9e9cf1b6e2c0f657 Gerrit-Change-Number: 38999 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/google/dedede: Add waddledoo variant
by Karthik Ramasubramanian (Code Review) 24 Feb '20

24 Feb '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38857 ) Change subject: mb/google/dedede: Add waddledoo variant ...................................................................... mb/google/dedede: Add waddledoo variant Add initial support for waddledoo board. BUG=None TEST=Build the mainboard and variant board. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I8ab4d52c97b1cfb5549d2fce4b931748a1b1ff1a --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/waddledoo/include/variant/ec.h A src/mainboard/google/dedede/variants/waddledoo/include/variant/gpio.h A src/mainboard/google/dedede/variants/waddledoo/overridetree.cb 5 files changed, 44 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/38857/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index a3d189d..3eddabc 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -44,12 +44,17 @@ config MAINBOARD_PART_NUMBER string - default "dedede" if BOARD_GOOGLE_DEDEDE + default "Dedede" if BOARD_GOOGLE_DEDEDE + default "Waddledoo" if BOARD_GOOGLE_WADDLEDOO config MAX_CPUS int default 4 +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_DEDEDE + config TPM_TIS_ACPI_INTERRUPT int default 4 # GPE0_DW0_4 (GPP_B4) @@ -61,5 +66,6 @@ config VARIANT_DIR string default "dedede" if BOARD_GOOGLE_DEDEDE + default "waddledoo" if BOARD_GOOGLE_WADDLEDOO endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 4bf440d..ae5df66 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -3,3 +3,9 @@ select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP select BOARD_ROMSIZE_KB_32768 + +config BOARD_GOOGLE_WADDLEDOO + bool "Waddledoo" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP + select BOARD_ROMSIZE_KB_32768 diff --git a/src/mainboard/google/dedede/variants/waddledoo/include/variant/ec.h b/src/mainboard/google/dedede/variants/waddledoo/include/variant/ec.h new file mode 100644 index 0000000..cc897dc --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledoo/include/variant/ec.h @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/dedede/variants/waddledoo/include/variant/gpio.h b/src/mainboard/google/dedede/variants/waddledoo/include/variant/gpio.h new file mode 100644 index 0000000..bf23f6e --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledoo/include/variant/gpio.h @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb new file mode 100644 index 0000000..ac9d576 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -0,0 +1,3 @@ +chip soc/intel/tigerlake + device domain 0 on end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/38857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ab4d52c97b1cfb5549d2fce4b931748a1b1ff1a Gerrit-Change-Number: 38857 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/dedede: Add EMMC configuration
by Karthik Ramasubramanian (Code Review) 24 Feb '20

24 Feb '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38856 ) Change subject: mb/google/dedede: Add EMMC configuration ...................................................................... mb/google/dedede: Add EMMC configuration Turn on EMMC device and leave the HS400 mode disabled. Configure the GPIOs associated with EMMC. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: Ic27c68f4622eec5b2930dc38186b82d895d3f67c --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c 2 files changed, 29 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/38856/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 9dfd6b7..95205cd 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -69,6 +69,9 @@ [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" + # Disable EMMC HS400 mode + register "ScsEmmcHs400Enabled" = "0" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -129,7 +132,7 @@ device pci 19.0 on end # I2C 4 device pci 19.1 off end # I2C 5 device pci 19.2 on end # UART 2 - device pci 1a.0 off end # eMMC + device pci 1a.0 on end # eMMC device pci 1c.0 off end # PCI Express Root Port 1 device pci 1c.1 off end # PCI Express Root Port 2 device pci 1c.2 off end # PCI Express Root Port 3 diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 9ee4dfc..e69dd27 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -58,6 +58,31 @@ /* C23 : UART2_CTS_N */ PAD_NC(GPP_C23, DN_20K), + /* F7 : EMMC_CMD */ + PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), + /* F8 : EMMC_DATA0 */ + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), + /* F9 : EMMC_DATA1 */ + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), + /* F10 : EMMC_DATA2 */ + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), + /* F11 : EMMC_DATA3 */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA4 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA5 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA6 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA7 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_RCLK */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_CLK */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_RESET_N */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* H4 : AP_I2C_TS_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* H5 : AP_I2C_TS_SCL */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic27c68f4622eec5b2930dc38186b82d895d3f67c Gerrit-Change-Number: 38856 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: mb/google/dedede: Add USB configuration
by Karthik Ramasubramanian (Code Review) 24 Feb '20

24 Feb '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38855 ) Change subject: mb/google/dedede: Add USB configuration ...................................................................... mb/google/dedede: Add USB configuration Add USB port configuration in devicetree. Configure USB Over-Current (OC) GPIOs. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I19f7563013c7d702d52b7f34a207a34abe308621 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c 2 files changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/38855/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 2d57a14..9dfd6b7 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -19,6 +19,23 @@ register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_H" + # USB Port Configuration + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C0 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Not Used + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Not Used + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Not Used + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A0 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A1 + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Not Used + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Not Used + register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -95,7 +112,7 @@ device pci 05.0 off end # IPU device pci 09.0 off end # Intel Trace Hub device pci 12.6 off end # GSPI 2 - device pci 14.0 off end # USB xHCI + device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM device pci 14.3 off end # CNVi wifi diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 8e4200a..9ee4dfc 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -21,6 +21,14 @@ /* A4 : ESPI_CS# */ /* A5 : ESPI_CLK */ /* A6 : ESPI_RESET_L */ + /* A12 : USB_OC1_N */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : USB_OC2_N */ + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + /* A14 : USB_OC3_N */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A18 : USB_OC0_N */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* B4 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), -- To view, visit https://review.coreboot.org/c/coreboot/+/38855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19f7563013c7d702d52b7f34a207a34abe308621 Gerrit-Change-Number: 38855 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

5 17

Change in coreboot[master]: mb/google/drallion: Remove MAC address pass through
by Dtrain Hsu (Code Review) 24 Feb '20

24 Feb '20

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39020 ) Change subject: mb/google/drallion: Remove MAC address pass through ...................................................................... mb/google/drallion: Remove MAC address pass through Remove MAC address pass through because when MAC address pass through setting change to "Use dock built-in MAC address", the MAC address always keeps the VPD value. BUG=b:147994020 TEST=tested on drallion and the result as below. (Option) (Result) - Use pre-assigned MAC address : Pass - Use Chromebook built-in address : Pass - Use dock built-in MAC address : Pass Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I1f58e98187feb4e428ca75f7e82c464567528526 --- M src/mainboard/google/drallion/dsdt.asl 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/39020/1 diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index ee63d6e..33ede7a 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -48,8 +48,6 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* VPD support */ #include <vendorcode/google/chromeos/acpi/vpd.asl> - /* MAC address passthru */ - #include <vendorcode/google/chromeos/acpi/amac.asl> #endif #include <southbridge/intel/common/acpi/sleepstates.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/39020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f58e98187feb4e428ca75f7e82c464567528526 Gerrit-Change-Number: 39020 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

4 3

Change in SerialTest[master]: Add rough approximation of SerialTest scaffold
by Patrick Georgi (Code Review) 24 Feb '20

24 Feb '20

Patrick Georgi has removed Ron Minnich from this change. ( https://review.coreboot.org/c/SerialTest/+/39083 ) Change subject: Add rough approximation of SerialTest scaffold ...................................................................... Removed reviewer Ron Minnich. -- To view, visit https://review.coreboot.org/c/SerialTest/+/39083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: SerialTest Gerrit-Branch: master Gerrit-Change-Id: Iab8d507dee6087bf32280ad6845fdd2d7715bf5c Gerrit-Change-Number: 39083 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: deleteReviewer

1 0

Change in coreboot[master]: superio/aspeed/ast2400: rename SWAK to SWC to match the datasheet
by Paul Menzel (Code Review) 24 Feb '20

24 Feb '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39095 ) Change subject: superio/aspeed/ast2400: rename SWAK to SWC to match the datasheet ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/39095/1/src/superio/aspeed/ast2400… File src/superio/aspeed/ast2400/ast2400.h: https://review.coreboot.org/c/coreboot/+/39095/1/src/superio/aspeed/ast2400… PS1, Line 9: #define AST2400_SWC 0x4 /* System Wake-Up control */ Keep SWAK in the comment? -- To view, visit https://review.coreboot.org/c/coreboot/+/39095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b3a14946e37f805d1c4e3df343dfcd7f67f6dc8 Gerrit-Change-Number: 39095 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 24 Feb 2020 11:23:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/cnl: Rename hfsts into me_hfsts
by Sridhar Siricilla (Code Review) 24 Feb '20

24 Feb '20

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39009 ) Change subject: soc/intel/cnl: Rename hfsts into me_hfsts ...................................................................... soc/intel/cnl: Rename hfsts into me_hfsts Remove me_hfs3 union from cnl/me.c since it's already defined in soc/me.h. Rename below union tags for consistency: hfsts2 -> me_hfsts2 hfsts3 -> me_hfsts3 hfsts4 -> me_hfsts4 hfsts5 -> me_hfsts5 hfsts6 -> me_hfsts6 TEST=Verified on hatch Change-Id: If81edbad0322425ee3e96c55a9c84a5087604308 Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/cannonlake/me.c 1 file changed, 11 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/39009/1 diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c index 0414470..3d3fcb8 100644 --- a/src/soc/intel/cannonlake/me.c +++ b/src/soc/intel/cannonlake/me.c @@ -32,7 +32,7 @@ }; /* Host Firmware Status Register 2 */ -union hfsts2 { +union me_hfsts2 { uint32_t raw; struct { uint32_t nftp_load_failure : 1; @@ -55,13 +55,8 @@ } __packed fields; }; -/* Host Firmware Status Register 3 */ -union hfsts3 { - uint32_t raw; -}; - /* Host Firmware Status Register 4 */ -union hfsts4 { +union me_hfsts4 { uint32_t raw; struct { uint32_t rsvd0 : 9; @@ -77,7 +72,7 @@ }; /* Host Firmware Status Register 5 */ -union hfsts5 { +union me_hfsts5 { uint32_t raw; struct { uint32_t acm_active : 1; @@ -96,7 +91,7 @@ }; /* Host Firmware Status Register 6 */ -union hfsts6 { +union me_hfsts6 { uint32_t raw; struct { uint32_t force_boot_guard_acm : 1; @@ -193,18 +188,18 @@ void dump_me_status(void *unused) { union me_hfsts1 hfsts1; - union hfsts2 hfsts2; - union hfsts3 hfsts3; - union hfsts4 hfsts4; - union hfsts5 hfsts5; - union hfsts6 hfsts6; + union me_hfsts2 hfsts2; + union me_hfsts3 hfsts3; + union me_hfsts4 hfsts4; + union me_hfsts5 hfsts5; + union me_hfsts6 hfsts6; if (!is_cse_enabled()) return; hfsts1.data = me_read_config32(PCI_ME_HFSTS1); hfsts2.raw = me_read_config32(PCI_ME_HFSTS2); - hfsts3.raw = me_read_config32(PCI_ME_HFSTS3); + hfsts3.data = me_read_config32(PCI_ME_HFSTS3); hfsts4.raw = me_read_config32(PCI_ME_HFSTS4); hfsts5.raw = me_read_config32(PCI_ME_HFSTS5); hfsts6.raw = me_read_config32(PCI_ME_HFSTS6); @@ -214,7 +209,7 @@ printk(BIOS_DEBUG, "ME: HFSTS2 : 0x%08X\n", hfsts2.raw); printk(BIOS_DEBUG, "ME: HFSTS3 : 0x%08X\n", - hfsts3.raw); + hfsts3.data); printk(BIOS_DEBUG, "ME: HFSTS4 : 0x%08X\n", hfsts4.raw); printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/39009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If81edbad0322425ee3e96c55a9c84a5087604308 Gerrit-Change-Number: 39009 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: soc/intel/skylake/elog: fix BUG: pch_log_rp_wake_source requests hidden
by Nico Huber (Code Review) 24 Feb '20

24 Feb '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39089 ) Change subject: soc/intel/skylake/elog: fix BUG: pch_log_rp_wake_source requests hidden ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/c/coreboot/+/39089/1/src/soc/intel/skylake/elog… File src/soc/intel/skylake/elog.c: https://review.coreboot.org/c/coreboot/+/39089/1/src/soc/intel/skylake/elog… PS1, Line 52: pci_devfn_t dev) > yup, in pch_log_pme_internal_wake_source I meant the parameter `dev` in this particular line. https://review.coreboot.org/c/coreboot/+/39089/2/src/soc/intel/skylake/elog… File src/soc/intel/skylake/elog.c: https://review.coreboot.org/c/coreboot/+/39089/2/src/soc/intel/skylake/elog… PS2, Line 86: !val || What? not that it matters, but we don't have to check it explicitly. https://review.coreboot.org/c/coreboot/+/39089/2/src/soc/intel/skylake/elog… PS2, Line 146: if (!dev) : continue; this too -- To view, visit https://review.coreboot.org/c/coreboot/+/39089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id126e2c51aec84a4af9354b39754ee74687cefc8 Gerrit-Change-Number: 39089 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 24 Feb 2020 09:18:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/supermicro/x11-lga1151-series: devicetree: fix iLPC2AHB irq
by Patrick Rudolph (Code Review) 24 Feb '20

24 Feb '20

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39092 ) Change subject: mb/supermicro/x11-lga1151-series: devicetree: fix iLPC2AHB irq ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/39092/1/src/mainboard/supermicro/x… File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb: https://review.coreboot.org/c/coreboot/+/39092/1/src/mainboard/supermicro/x… PS1, Line 109: irq 0x70 = 0x0 > not GPIO but Mailbox I couldn't find a reference in the Aspeed datasheet that "0" means disable and INT0 is assigned to the system timer. -- To view, visit https://review.coreboot.org/c/coreboot/+/39092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc1cd04e995d68f4c779e9aa9c09bb7bf9f26363 Gerrit-Change-Number: 39092 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Mon, 24 Feb 2020 09:13:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2020