coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/block: Move smihandler common functions into common ...
by Subrata Banik (Code Review) 23 Feb '20

23 Feb '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26138 ) Change subject: soc/intel/common/block: Move smihandler common functions into common code ...................................................................... Patch Set 42: (3 comments) https://review.coreboot.org/c/coreboot/+/26138/41/src/soc/intel/common/bloc… File src/soc/intel/common/block/smm/smihandler.c: https://review.coreboot.org/c/coreboot/+/26138/41/src/soc/intel/common/bloc… PS41, Line 67: __weak > Why is this still kept weak? None of the SoCs provide their own implementation after this change. Done https://review.coreboot.org/c/coreboot/+/26138/41/src/soc/intel/common/bloc… PS41, Line 70: tco_sts > looks same to me. […] @Furquan, let me know if you have some further opens marking resolved based on register details been shared https://review.coreboot.org/c/coreboot/+/26138/41/src/soc/intel/common/bloc… PS41, Line 499: > isn't this fixed at latest patch set ? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/26138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03 Gerrit-Change-Number: 26138 Gerrit-PatchSet: 42 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 23 Feb 2020 13:49:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake/elog: fix BUG: pch_log_rp_wake_source requests hidden
by Michael Niewöhner (Code Review) 23 Feb '20

23 Feb '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39089 ) Change subject: soc/intel/skylake/elog: fix BUG: pch_log_rp_wake_source requests hidden ...................................................................... Patch Set 1: oops... there's cb:38750 already -- To view, visit https://review.coreboot.org/c/coreboot/+/39089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id126e2c51aec84a4af9354b39754ee74687cefc8 Gerrit-Change-Number: 39089 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 23 Feb 2020 12:34:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake/elog: fix BUG: pch_log_rp_wake_source requests hidden
by Michael Niewöhner (Code Review) 23 Feb '20

23 Feb '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39089 ) Change subject: soc/intel/skylake/elog: fix BUG: pch_log_rp_wake_source requests hidden ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/39089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id126e2c51aec84a4af9354b39754ee74687cefc8 Gerrit-Change-Number: 39089 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 23 Feb 2020 12:28:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cbfs: allow uncompressed payloads
by ron minnich (Code Review) 23 Feb '20

23 Feb '20

ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39051 ) Change subject: cbfs: allow uncompressed payloads ...................................................................... cbfs: allow uncompressed payloads Change-Id: I8261bc28e5bc9aa32db1dccef7035486995c9873 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- M payloads/Kconfig 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/39051/1 diff --git a/payloads/Kconfig b/payloads/Kconfig index 4e86c21..99a4391 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -60,7 +60,12 @@ depends on !PAYLOAD_NONE && !PAYLOAD_LINUX && !PAYLOAD_LINUXBOOT && !PAYLOAD_FIT help Choose the compression algorithm for the chosen payloads. - You can choose between LZMA and LZ4. + You can choose between None, LZMA, or LZ4. + +config COMPRESSED_PAYLOAD_NONE + bool "Use no compression for payloads" + help + Do not compress the payload. config COMPRESSED_PAYLOAD_LZMA bool "Use LZMA compression for payloads" -- To view, visit https://review.coreboot.org/c/coreboot/+/39051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8261bc28e5bc9aa32db1dccef7035486995c9873 Gerrit-Change-Number: 39051 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block: Move smihandler common functions into common ...
by Subrata Banik (Code Review) 22 Feb '20

22 Feb '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26138 ) Change subject: soc/intel/common/block: Move smihandler common functions into common code ...................................................................... Patch Set 42: (1 comment) https://review.coreboot.org/c/coreboot/+/26138/41/src/soc/intel/common/bloc… File src/soc/intel/common/block/smm/smihandler.c: https://review.coreboot.org/c/coreboot/+/26138/41/src/soc/intel/common/bloc… PS41, Line 70: tco_sts > Is this different for APL v/s GLK? looks same to me. may be EDS has discrepancy between those 2 but register details is same, i have verified. -- To view, visit https://review.coreboot.org/c/coreboot/+/26138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03 Gerrit-Change-Number: 26138 Gerrit-PatchSet: 42 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 22 Feb 2020 03:43:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by Wonkyu Kim (Code Review) 22 Feb '20

22 Feb '20

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38998 ) Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support ...................................................................... Patch Set 13: (1 comment) https://review.coreboot.org/c/coreboot/+/38998/13/src/mainboard/intel/tglrv… File src/mainboard/intel/tglrvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/38998/13/src/mainboard/intel/tglrv… PS13, Line 51: Can we add Windows EC case which doesn't report DDR4? if (CONFIG(BOARD_DDR4)) spd_index = SPD_ADDR_TABLE; -- To view, visit https://review.coreboot.org/c/coreboot/+/38998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Gerrit-Change-Number: 38998 Gerrit-PatchSet: 13 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 22 Feb 2020 01:31:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by Srinidhi N Kaushik (Code Review) 22 Feb '20

22 Feb '20

Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38998 ) Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support ...................................................................... Patch Set 13: (1 comment) https://review.coreboot.org/c/coreboot/+/38998/5/src/soc/intel/tigerlake/in… File src/soc/intel/tigerlake/include/soc/meminit_tgl.h: https://review.coreboot.org/c/coreboot/+/38998/5/src/soc/intel/tigerlake/in… PS5, Line 64: : /* Rcomp configuration information */ : struct rcomp_cfg { : /* Rcomp Resistor */ : uint16_t rcomp_resistor; : : /* Rcomp Target */ : uint16_t rcomp_target[NUM_RCOMP_TARGETS]; : : }; : > Rcomp values are not required for LPDDR4 but it is needed for DDR4 memory type. […] I have refactored the code for DDR4 initialization. -- To view, visit https://review.coreboot.org/c/coreboot/+/38998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Gerrit-Change-Number: 38998 Gerrit-PatchSet: 13 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 22 Feb 2020 01:04:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by Srinidhi N Kaushik (Code Review) 22 Feb '20

22 Feb '20

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Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by Srinidhi N Kaushik (Code Review) 22 Feb '20

22 Feb '20

Hello Raj Astekar, Patrick Rudolph, Subrata Banik, Nick Vaccaro, Wonkyu Kim, Ravishankar Sarawadi, build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38998 to look at the new patch set (#12). Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support ...................................................................... mb/intel/tglrvp: add Tiger Lake memory initialization support Update memory parameters based on memory type supported by Tiger lake RVP 1. Update dq/dqs mappings and rcomp data 2. Update spd data for Tiger lake LPDDR4 SAMSUNG/MICRON memory 3. Add SPD data bin files for supported memory types 4. Update other FSPM Upds as part of memory initialization BUG=none BRANCH=none TEST= build tglrvp flash and boot to kernel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e --- M src/mainboard/intel/tglrvp/board_id.h M src/mainboard/intel/tglrvp/romstage_fsp_params.c A src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex M src/mainboard/intel/tglrvp/spd/Makefile.inc A src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex A src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex M src/mainboard/intel/tglrvp/spd/spd.h M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc A src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c 10 files changed, 282 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/38998/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/38998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Gerrit-Change-Number: 38998 Gerrit-PatchSet: 12 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by Srinidhi N Kaushik (Code Review) 22 Feb '20

22 Feb '20

Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38998 ) Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support ...................................................................... Patch Set 11: (3 comments) https://review.coreboot.org/c/coreboot/+/38998/9/src/mainboard/intel/tglrvp… File src/mainboard/intel/tglrvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/38998/9/src/mainboard/intel/tglrvp… PS9, Line 84: mem_cfg->SpdAddressTable[0] = 0x0; > I believe this UPD already defaults to 0. […] Ack https://review.coreboot.org/c/coreboot/+/38998/9/src/mainboard/intel/tglrvp… PS9, Line 84: mem_cfg->SpdAddressTable[0] = 0x0; : mem_cfg->SpdAddressTable[1] = 0x0; : mem_cfg->SpdAddressTable[2] = 0x0; : mem_cfg->SpdAddressTable[3] = 0x0; > Based on the comment in the Fspm header file we are setting it to 0 when MemorySpdPtr is used. Done https://review.coreboot.org/c/coreboot/+/38998/5/src/soc/intel/tigerlake/in… File src/soc/intel/tigerlake/include/soc/meminit_tgl.h: PS5: > Done Done -- To view, visit https://review.coreboot.org/c/coreboot/+/38998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Gerrit-Change-Number: 38998 Gerrit-PatchSet: 11 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 22 Feb 2020 00:50:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit February 2020