coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/block: Move smihandler common functions into common ...
by Furquan Shaikh (Code Review) 21 Feb '20

21 Feb '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26138 ) Change subject: soc/intel/common/block: Move smihandler common functions into common code ...................................................................... Patch Set 42: (1 comment) https://review.coreboot.org/c/coreboot/+/26138/41/src/soc/intel/common/bloc… File src/soc/intel/common/block/smm/smihandler.c: https://review.coreboot.org/c/coreboot/+/26138/41/src/soc/intel/common/bloc… PS41, Line 70: tco_sts > doc number: 571696 GLK EDS vol 2 rev 2.0 chapter 10. […] Is this different for APL v/s GLK? -- To view, visit https://review.coreboot.org/c/coreboot/+/26138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03 Gerrit-Change-Number: 26138 Gerrit-PatchSet: 42 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Feb 2020 15:22:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block: Move smihandler common functions into common ...
by Subrata Banik (Code Review) 21 Feb '20

21 Feb '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26138 ) Change subject: soc/intel/common/block: Move smihandler common functions into common code ...................................................................... Patch Set 42: (1 comment) https://review.coreboot.org/c/coreboot/+/26138/41/src/soc/intel/common/bloc… File src/soc/intel/common/block/smm/smihandler.c: https://review.coreboot.org/c/coreboot/+/26138/41/src/soc/intel/common/bloc… PS41, Line 70: tco_sts > > i don't think this big is RO. its RW/1C ... […] doc number: 571696 GLK EDS vol 2 rev 2.0 chapter 10.42 -- To view, visit https://review.coreboot.org/c/coreboot/+/26138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03 Gerrit-Change-Number: 26138 Gerrit-PatchSet: 42 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Feb 2020 14:52:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/kontron/mal10: add options for carrier board selection
by Maxim Polyakov (Code Review) 21 Feb '20

21 Feb '20

Maxim Polyakov has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39044 ) Change subject: mb/kontron/mal10: add options for carrier board selection ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/39044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdb67f15cbafc36adc5c67deca068cfeed559e78 Gerrit-Change-Number: 39044 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: cpu/x86/smm: Make BIOS all upper case
by Name of user not set (Code Review) 21 Feb '20

21 Feb '20

cedarhouse1(a)comcast.net has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38854 ) Change subject: cpu/x86/smm: Make BIOS all upper case ...................................................................... cpu/x86/smm: Make BIOS all upper case In an CL:38821 a reviewer noted that BIOS is upper case. This patch fixes that. Signed-off-by: Eugene D. Myers <edmyers(a)tycho.nsa.gov> Change-Id: I85d78b5e08a7643c3d87e3daf353d6b3ba8d306b --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/38854/1 diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 66a40c4..856ca78 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -396,7 +396,7 @@ /* Does the required amount of memory exceed the SMRAM region size? */ total_size = total_stack_size + handler_size; total_size += fxsave_size + SMM_DEFAULT_SIZE; - // account for the bios resource list + /* Account for the BIOS resource list */ if (CONFIG(STM)) total_size += CONFIG_BIOS_RESOURCE_LIST_SIZE; -- To view, visit https://review.coreboot.org/c/coreboot/+/38854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85d78b5e08a7643c3d87e3daf353d6b3ba8d306b Gerrit-Change-Number: 38854 Gerrit-PatchSet: 1 Gerrit-Owner: cedarhouse1(a)comcast.net Gerrit-MessageType: newchange

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Change in coreboot[master]: security/intel/stm: Use depends on ENABLE_VMX
by Name of user not set (Code Review) 21 Feb '20

21 Feb '20

cedarhouse1(a)comcast.net has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38852 ) Change subject: security/intel/stm: Use depends on ENABLE_VMX ...................................................................... security/intel/stm: Use depends on ENABLE_VMX The STM is a part of the core VTx and using ENABLE_VMX will make the STM option available for any configuration that has an Intel processor that supports VTx. Signed-off-by: Eugene D. Myers <edmyers(a)tycho.nsa.gov> Change-Id: I57ff82754e6c692c8722d41f812e35940346888a --- M src/security/intel/stm/Kconfig M src/soc/intel/skylake/Kconfig 2 files changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/38852/1 diff --git a/src/security/intel/stm/Kconfig b/src/security/intel/stm/Kconfig index 144deed..9f5f763 100644 --- a/src/security/intel/stm/Kconfig +++ b/src/security/intel/stm/Kconfig @@ -1,12 +1,7 @@ - -config PLATFORM_SUPPORTS_STM - bool - depends on SMM_TSEG - config STM bool "Enable STM" default n - depends on PLATFORM_SUPPORTS_STM + depends on ENABLE_VMX select USE_BLOBS help diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index ae60a63..6277cea 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -44,7 +44,6 @@ select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PARALLEL_MP_AP_WORK - select PLATFORM_SUPPORTS_STM select PLATFORM_USES_FSP2_0 select REG_SCRIPT select SA_ENABLE_DPR -- To view, visit https://review.coreboot.org/c/coreboot/+/38852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57ff82754e6c692c8722d41f812e35940346888a Gerrit-Change-Number: 38852 Gerrit-PatchSet: 1 Gerrit-Owner: cedarhouse1(a)comcast.net Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/snb: Add PCI routing table for PEG root ports
by James (Code Review) 21 Feb '20

21 Feb '20

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39021 ) Change subject: nb/intel/snb: Add PCI routing table for PEG root ports ...................................................................... nb/intel/snb: Add PCI routing table for PEG root ports Previously the PRTs were defined in southbridge code (#13612), but this was lost when southbridge PRTs became autogenerated. Add the proper PRTs for the PCI express for graphics root ports. This (again) fixes warnings issued by Linux for interrupts on secondary functions of devices on the PEG ports, such as the HDMI audio controller on graphics cards. > pcieport 0000:00:01.0: can't derive routing for PCI INT B > snd_hda_intel 0000:01:00.1: PCI INT B: no GSI Tested with GIGABYTE P67A-UD3R (#31363) with Radeon HD 5670. Change-Id: Ic429ec2fdeadb9dab1c03916974e173004d6cd16 Signed-off-by: James Ye <jye836(a)gmail.com> --- M src/northbridge/intel/sandybridge/acpi/peg.asl 1 file changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39021/1 diff --git a/src/northbridge/intel/sandybridge/acpi/peg.asl b/src/northbridge/intel/sandybridge/acpi/peg.asl index fcec00e..b7881ea 100644 --- a/src/northbridge/intel/sandybridge/acpi/peg.asl +++ b/src/northbridge/intel/sandybridge/acpi/peg.asl @@ -27,6 +27,25 @@ { Name(_ADR, 0x00000000) } + + Method (_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 16 }, + Package() { 0x0000ffff, 1, 0, 17 }, + Package() { 0x0000ffff, 2, 0, 18 }, + Package() { 0x0000ffff, 3, 0, 19 } + }) + } Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } + }) + } + } } Device (PEG1) @@ -42,6 +61,25 @@ { Name(_ADR, 0x00000000) } + + Method (_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 17 }, + Package() { 0x0000ffff, 1, 0, 18 }, + Package() { 0x0000ffff, 2, 0, 19 }, + Package() { 0x0000ffff, 3, 0, 16 } + }) + } Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } + }) + } + } } Device (PEG2) @@ -57,6 +95,25 @@ { Name(_ADR, 0x00000000) } + + Method (_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 18 }, + Package() { 0x0000ffff, 1, 0, 19 }, + Package() { 0x0000ffff, 2, 0, 16 }, + Package() { 0x0000ffff, 3, 0, 17 } + }) + } Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } + }) + } + } } Device (PEG6) @@ -72,4 +129,23 @@ { Name(_ADR, 0x00000000) } + + Method (_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 16 }, + Package() { 0x0000ffff, 1, 0, 17 }, + Package() { 0x0000ffff, 2, 0, 18 }, + Package() { 0x0000ffff, 3, 0, 19 } + }) + } Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } + }) + } + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/39021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic429ec2fdeadb9dab1c03916974e173004d6cd16 Gerrit-Change-Number: 39021 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/intel/stm: Check for processor STM support
by Name of user not set (Code Review) 21 Feb '20

21 Feb '20

cedarhouse1(a)comcast.net has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38836 ) Change subject: security/intel/stm: Check for processor STM support ...................................................................... security/intel/stm: Check for processor STM support This check ensures that the current processor supports a STM. Normally, any Intel x86 processor that has VTX also supports an STM and this check should fail only in the rare case that STM support has been disabled for a processor. Signed-off-by: Eugene D. Myers <edmyers(a)tycho.nsa.gov> Change-Id: I518bb2aa1bdec94b5b6d5e991d7575257f3dc6e9 --- M src/include/cpu/x86/msr.h M src/security/intel/stm/StmPlatformSmm.c 2 files changed, 19 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/38836/1 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 49abd41..c3764b2 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -74,6 +74,7 @@ #define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH) #define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0) #define IA32_VMX_BASIC_MSR 0x480 +#define DUAL_MONITOR_TREATMENT_HI (1 << 17) #define IA32_VMX_MISC_MSR 0x485 #define MC0_ADDR 0x402 #define MC0_MISC 0x403 diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c index d7064b0..69cbcae 100644 --- a/src/security/intel/stm/StmPlatformSmm.c +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -157,11 +157,22 @@ void stm_setup(uintptr_t mseg, int cpu, int num_cpus, uintptr_t smbase, uintptr_t base_smbase, uint32_t offset32) { - msr_t InitMseg; - msr_t MsegChk; + msr_t init_mseg; + msr_t mseg_chk; + msr_t stm_chk; + uintptr_t addr_calc; // used to calculate the stm resource heap area printk(BIOS_DEBUG, "STM: set up for cpu %d/%d\n", cpu, num_cpus); + + stm_chk = rdmsr(IA32_VMX_BASIC_MSR); + + // Does this processor support an STM? + if ((stm_chk.hi & DUAL_MONITOR_TREATMENT_HI) != DUAL_MONITOR_TREATMENT_HI) { + printk(BIOS_DEBUG, "STM: not supported on cpu: %d\n", cpu); + return; + } + if (cpu == 0) { // need to create the BIOS resource list once @@ -183,15 +194,15 @@ if (stm_load_status == 0) { // enable STM for this cpu - InitMseg.lo = mseg | IA32_SMM_MONITOR_VALID; - InitMseg.hi = 0; + init_mseg.lo = mseg | IA32_SMM_MONITOR_VALID; + init_mseg.hi = 0; - wrmsr(IA32_SMM_MONITOR_CTL_MSR, InitMseg); + wrmsr(IA32_SMM_MONITOR_CTL_MSR, init_mseg); - MsegChk = rdmsr(IA32_SMM_MONITOR_CTL_MSR); + mseg_chk = rdmsr(IA32_SMM_MONITOR_CTL_MSR); printk(BIOS_DEBUG, "STM: MSEG Initialized (%d) 0x%08x 0x%08x\n", - cpu, MsegChk.hi, MsegChk.lo); + cpu, mseg_chk.hi, mseg_chk.lo); // setup the descriptor for this cpu setup_smm_descriptor((void *)smbase, (void *) base_smbase, -- To view, visit https://review.coreboot.org/c/coreboot/+/38836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I518bb2aa1bdec94b5b6d5e991d7575257f3dc6e9 Gerrit-Change-Number: 38836 Gerrit-PatchSet: 1 Gerrit-Owner: cedarhouse1(a)comcast.net Gerrit-MessageType: newchange

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Change in libhwbase[master]: time: Add T_First constant
by Adrian-Ken Rueegsegger (Code Review) 21 Feb '20

21 Feb '20

Adrian-Ken Rueegsegger has uploaded this change for review. ( https://review.coreboot.org/c/libhwbase/+/38983 ) Change subject: time: Add T_First constant ...................................................................... time: Add T_First constant The constant can be used to initialize variables of type HW.Time.T. Change-Id: I65246d6776d464bfa8648075b48e7de61cd82902 Signed-off-by: Adrian-Ken Rueegsegger <ken(a)codelabs.ch> --- M common/hw-time.ads 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/libhwbase refs/changes/83/38983/1 diff --git a/common/hw-time.ads b/common/hw-time.ads index aeda5ec..5cfa963 100644 --- a/common/hw-time.ads +++ b/common/hw-time.ads @@ -18,6 +18,8 @@ type T is private; + T_First : constant T; + function Now return T with Volatile_Function, @@ -71,6 +73,8 @@ type T is new Word64; + T_First : constant T := T'First; + end HW.Time; -- vim: set ts=8 sts=3 sw=3 et: -- To view, visit https://review.coreboot.org/c/libhwbase/+/38983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libhwbase Gerrit-Branch: master Gerrit-Change-Id: I65246d6776d464bfa8648075b48e7de61cd82902 Gerrit-Change-Number: 38983 Gerrit-PatchSet: 1 Gerrit-Owner: Adrian-Ken Rueegsegger <ken(a)codelabs.ch> Gerrit-MessageType: newchange

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Change in libhwbase[master]: mutime: Make Sinfo an imported constant
by Adrian-Ken Rueegsegger (Code Review) 21 Feb '20

21 Feb '20

Adrian-Ken Rueegsegger has uploaded this change for review. ( https://review.coreboot.org/c/libhwbase/+/38982 ) Change subject: mutime: Make Sinfo an imported constant ...................................................................... mutime: Make Sinfo an imported constant The subject info data structure is static and is not changed during runtime. Make Sinfo an imported constant and adjust refinement of abstract timer state and global contract of Hz function accordingly. They are no longer volatile. Change-Id: I5729bc7f2d77c5c51a6cab2edc7953e95c9e4d29 Signed-off-by: Adrian-Ken Rueegsegger <ken(a)codelabs.ch> --- M common/hw-time-timer.ads M common/mutime/hw-time-timer.adb 2 files changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/libhwbase refs/changes/82/38982/1 diff --git a/common/hw-time-timer.ads b/common/hw-time-timer.ads index 90978df..2bec99b 100644 --- a/common/hw-time-timer.ads +++ b/common/hw-time-timer.ads @@ -15,8 +15,7 @@ private package HW.Time.Timer with Abstract_State => ((Timer_State with - Part_Of => HW.Time.State, - External => Async_Writers), + Part_Of => HW.Time.State), (Abstract_Time with Part_Of => HW.Time.State, External => Async_Writers)) @@ -38,7 +37,6 @@ function Hz return T with - Volatile_Function, Global => (Input => Timer_State); end HW.Time.Timer; diff --git a/common/mutime/hw-time-timer.adb b/common/mutime/hw-time-timer.adb index c683d6f..8e9b497 100644 --- a/common/mutime/hw-time-timer.adb +++ b/common/mutime/hw-time-timer.adb @@ -25,10 +25,9 @@ := ((Musinfo.Subject_Info_Type_Size + (16#1000# - 1)) / 16#1000#) * 16#1000#; - Sinfo : Musinfo.Subject_Info_Type + Sinfo : constant Musinfo.Subject_Info_Type with - Volatile, - Async_Writers, + Import, Address => System'To_Address (Sinfo_Base_Address); Sched_Info : Muschedinfo.Scheduling_Info_Type -- To view, visit https://review.coreboot.org/c/libhwbase/+/38982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libhwbase Gerrit-Branch: master Gerrit-Change-Id: I5729bc7f2d77c5c51a6cab2edc7953e95c9e4d29 Gerrit-Change-Number: 38982 Gerrit-PatchSet: 1 Gerrit-Owner: Adrian-Ken Rueegsegger <ken(a)codelabs.ch> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by Furquan Shaikh (Code Review) 21 Feb '20

21 Feb '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38998 ) Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/38998/9/src/mainboard/intel/tglrvp… File src/mainboard/intel/tglrvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/38998/9/src/mainboard/intel/tglrvp… PS9, Line 84: mem_cfg->SpdAddressTable[0] = 0x0; > Based on the comment in the Fspm header file we are setting it to 0 when MemorySpdPtr is used. I believe this UPD already defaults to 0. If you still want to ensure that this doesn't change going forward, you can add this in meminit_lpddr4x_dimm0() itself so that all mainboards can take advantage of that. -- To view, visit https://review.coreboot.org/c/coreboot/+/38998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Gerrit-Change-Number: 38998 Gerrit-PatchSet: 10 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 21 Feb 2020 06:48:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit February 2020