coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/block: Move smihandler common functions into common ...
by Subrata Banik (Code Review) 21 Feb '20

21 Feb '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26138 ) Change subject: soc/intel/common/block: Move smihandler common functions into common code ...................................................................... Patch Set 42: (2 comments) https://review.coreboot.org/c/coreboot/+/26138/41/src/soc/intel/common/bloc… File src/soc/intel/common/block/smm/smihandler.c: https://review.coreboot.org/c/coreboot/+/26138/41/src/soc/intel/common/bloc… PS41, Line 70: tco_sts > So, there is a slight change in behavior now for APL. Previously, this function would do nothing, but now: > a) It checks bit 8 in tco_sts, but that bit is marked reserved. As per EDS, it is RO and reads as 0, so I am guessing this has no side-effects? i don't think this big is RO. its RW/1C, As per EDS BIOSWR_STS: Intel PCH sets this bit to 1 and generates an SMI# to indicate an illegal attempt to write to the BIOS located in the FWH that is accessed over the LPC. This occurs when either: a) The BIOSWP bit is changed from 0 to 1 and the LE bit is also set, or b) Any write is attempted to the BIOS and the BIOSWP bit is also set. This bit doesn’t get set to 1 when: 1) a or b above occurs on eSPI controller. 2) a or b above occurs on SPI Flash controller. Note: On write cycles attempted to the 4MB lower alias to the BIOS space, the BIOSWR_STS bit will not be set. > b) But, CONFIG(SPI_FLASH_SMM) could be true and so now this would always end up calling fast_spi_enable_wp(). Are you changing this intentionally? i don't think this function is getting called unconditionally for APL/GLK, i can double confirm the same https://review.coreboot.org/c/coreboot/+/26138/41/src/soc/intel/common/bloc… PS41, Line 499: > nit: extra blank line not required. isn't this fixed at latest patch set ? -- To view, visit https://review.coreboot.org/c/coreboot/+/26138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03 Gerrit-Change-Number: 26138 Gerrit-PatchSet: 42 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Feb 2020 02:42:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by Wonkyu Kim (Code Review) 21 Feb '20

21 Feb '20

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38998 ) Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/38998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Gerrit-Change-Number: 38998 Gerrit-PatchSet: 7 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 21 Feb 2020 01:39:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by Srinidhi N Kaushik (Code Review) 21 Feb '20

21 Feb '20

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Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by Srinidhi N Kaushik (Code Review) 21 Feb '20

21 Feb '20

Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38998 ) Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support ...................................................................... Patch Set 7: (3 comments) https://review.coreboot.org/c/coreboot/+/38998/4/src/mainboard/intel/tglrvp… File src/mainboard/intel/tglrvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/38998/4/src/mainboard/intel/tglrvp… PS4, Line 21: #include "board_id.h" > Ack Done https://review.coreboot.org/c/coreboot/+/38998/4/src/mainboard/intel/tglrvp… PS4, Line 91: if (spd_index > 0 && spd_index != 2) { : : mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; : spd_ptr = mainboard_get_spd_data(); : : mem_cfg->MemorySpdPtr00 = spd_ptr; : mem_cfg->MemorySpdPtr02 = spd_ptr; : mem_cfg->MemorySpdPtr04 = spd_ptr; : mem_cfg->MemorySpdPtr06 = spd_ptr; : mem_cfg->MemorySpdPtr08 = spd_ptr; : mem_cfg->MemorySpdPtr10 = spd_ptr; : mem_cfg->MemorySpdPtr12 = spd_ptr; : mem_cfg->MemorySpdPtr14 = spd_ptr; : : mem_cfg->SpdAddressTable[0] = 0x0; : mem_cfg->SpdAddressTable[1] = 0x0; : mem_cfg->SpdAddressTable[2] = 0x0; : mem_cfg->SpdAddressTable[3] = 0x0; : : } else { : mem_cfg->MemorySpdPtr00 = 0; : mem_cfg->MemorySpdPtr01 = 0; : mem_cfg->MemorySpdPtr10 = 0; : mem_cfg->MemorySpdPtr11 = 0; : : mem_cfg->SpdAddressTable[0] = 0xA0; : mem_cfg->SpdAddressTable[1] = 0xA2; : mem_cfg->SpdAddressTable[2] = 0xA4; : mem_cfg->SpdAddressTable[3] = 0xA6; : : mem_cfg->RcompResistor = mem_params.rcomp_resistor; : memcpy(&mem_cfg->RcompTarget, mem_params.rcomp_target, mem_params.rcomp_target_size); : } : : memcpy(&mem_cfg->DqMapCpu2DramCh0, mem_params.dq_map, mem_params.dq_map_size); : memcpy(&mem_cfg->DqsMapCpu2DramCh0, mem_params.dqs_map, mem_params.dqs_map_size); : : mem_cfg->DqPinsInterleaved = 0; : mem_cfg->MrcSafeConfig = 0x1; : : /* Early Command Training */ : mem_cfg->ECT = 1; > Agree Furquan, I have refactored the code to use common code in soc. Will push the change soon. Done https://review.coreboot.org/c/coreboot/+/38998/4/src/mainboard/intel/tglrvp… File src/mainboard/intel/tglrvp/spd/Makefile.inc: https://review.coreboot.org/c/coreboot/+/38998/4/src/mainboard/intel/tglrvp… PS4, Line 18: += > Ack Done -- To view, visit https://review.coreboot.org/c/coreboot/+/38998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Gerrit-Change-Number: 38998 Gerrit-PatchSet: 7 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 21 Feb 2020 01:00:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by Srinidhi N Kaushik (Code Review) 21 Feb '20

21 Feb '20

Hello Raj Astekar, Patrick Rudolph, Nick Vaccaro, Wonkyu Kim, Ravishankar Sarawadi, build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38998 to look at the new patch set (#7). Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support ...................................................................... mb/intel/tglrvp: add Tiger Lake memory initialization support Update memory parameters based on memory type supported by Tiger lake RVP 1. Update dq/dqs mappings and rcomp data 2. Update spd data for Tiger lake LPDDR4 SAMSUNG/MICRON memory 3. Add SPD data bin files for supported memory types 4. Update other FSPM Upds as part of memory initialization BUG=none BRANCH=none TEST= build tglrvp flash and boot to kernel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e --- M src/mainboard/intel/tglrvp/board_id.h M src/mainboard/intel/tglrvp/romstage_fsp_params.c A src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex M src/mainboard/intel/tglrvp/spd/Makefile.inc A src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex A src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex M src/mainboard/intel/tglrvp/spd/spd.h M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc A src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c M src/soc/intel/tigerlake/include/soc/meminit_tgl.h 11 files changed, 313 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/38998/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/38998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Gerrit-Change-Number: 38998 Gerrit-PatchSet: 7 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by Srinidhi N Kaushik (Code Review) 21 Feb '20

21 Feb '20

Hello Raj Astekar, Patrick Rudolph, Nick Vaccaro, Wonkyu Kim, Ravishankar Sarawadi, build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38998 to look at the new patch set (#6). Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support ...................................................................... mb/intel/tglrvp: add Tiger Lake memory initialization support Update memory parameters based on memory type supported by Tiger lake RVP 1. Update dq/dqs mappings and rcomp data 2. Update spd data for Tiger lake LPDDR4 SAMSUNG/MICRON memory 3. Add SPD data bin files for supported memory types 4. Update other FSPM Upds as part of memory initialization BUG=none BRANCH=none TEST= build tglrvp flash and boot to kernel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e --- M src/mainboard/intel/tglrvp/board_id.h M src/mainboard/intel/tglrvp/romstage_fsp_params.c A src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex M src/mainboard/intel/tglrvp/spd/Makefile.inc A src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex A src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex M src/mainboard/intel/tglrvp/spd/spd.h M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc A src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c M src/soc/intel/tigerlake/include/soc/meminit_tgl.h 11 files changed, 313 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/38998/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/38998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Gerrit-Change-Number: 38998 Gerrit-PatchSet: 6 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by build bot (Jenkins) (Code Review) 21 Feb '20

21 Feb '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38998 ) Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support ...................................................................... Patch Set 5: (59 comments) https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… File src/mainboard/intel/tglrvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 70: memcpy(mem_cfg->RcompTarget, rcomp_data->rcomp_target, sizeof(rcomp_data->rcomp_target)); line over 96 characters https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… File src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex: https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 1: 23 11 11 0E 1B 21 F9 08 00 40 00 00 0A 01 00 00 DOS line endings https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 2: 00 00 05 0F 92 54 01 00 8A 00 90 A8 90 C0 08 60 DOS line endings https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 3: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings 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https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 28: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 29: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 31: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 32: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… File src/mainboard/intel/tglrvp/spd/spd.h: https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 25: #define SPD_ADDR_TABLE 0xFF please, no space before tabs https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… File src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h: https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 32: const void *dq_map; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 32: const void *dq_map; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 33: size_t dq_map_size; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 33: size_t dq_map_size; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 34: const void *dqs_map; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 34: const void *dqs_map; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 35: size_t dqs_map_size; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 35: size_t dqs_map_size; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 36: u16 rcomp_resistor; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 36: u16 rcomp_resistor; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 37: const void *rcomp_target; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 37: const void *rcomp_target; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 38: size_t rcomp_target_size; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 38: size_t rcomp_target_size; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… File src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c: https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 22: return 0; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 22: return 0; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 29: { 0, 1, 6, 7, 3, 2, 5, 4 , /* Byte 0 */ space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 31: { 11, 12, 8, 15, 9, 14, 10, 13 , /* Byte 2 */ space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 33: { 4, 5, 3, 2, 7, 1, 0, 6 , /* Byte 4 */ space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 35: { 12, 11, 8, 13, 14, 15, 9, 10 , /* Byte 6 */ space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 38: { 11, 10, 9, 8, 12, 13, 15, 14 , /* Byte 0 */ space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 40: { 0, 7, 1, 6, 3, 5, 2, 4 , /* Byte 2 */ space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 42: { 4, 5, 6, 1, 3, 2, 7, 0 , /* Byte 4 */ space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 44: { 10, 12, 9, 15, 8, 11, 13, 14 , /* Byte 6 */ space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/c/coreboot/+/38998/5/src/mainboard/intel/tglrvp… PS5, Line 66: const struct rcomp_cfg * get_rcomp_data(void) "foo * bar" should be "foo *bar" -- To view, visit https://review.coreboot.org/c/coreboot/+/38998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Gerrit-Change-Number: 38998 Gerrit-PatchSet: 5 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 20 Feb 2020 23:49:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by Srinidhi N Kaushik (Code Review) 21 Feb '20

21 Feb '20

Hello Raj Astekar, Nick Vaccaro, Wonkyu Kim, Ravishankar Sarawadi, Shaunak Saha, Furquan Shaikh, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38998 to look at the new patch set (#5). Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support ...................................................................... mb/intel/tglrvp: add Tiger Lake memory initialization support Update memory parameters based on memory type supported by Tiger lake RVP 1. Update dq/dqs mappings and rcomp data 2. Update spd data for Tiger lake LPDDR4 SAMSUNG/MICRON memory 3. Add SPD data bin files for supported memory types 4. Update other FSPM Upds as part of memory initialization BUG=none BRANCH=none TEST= build tglrvp flash and boot to kernel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e --- M src/mainboard/intel/tglrvp/board_id.h M src/mainboard/intel/tglrvp/romstage_fsp_params.c A src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex M src/mainboard/intel/tglrvp/spd/Makefile.inc A src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex A src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex M src/mainboard/intel/tglrvp/spd/spd.h M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc A src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c M src/soc/intel/tigerlake/include/soc/meminit_tgl.h 11 files changed, 312 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/38998/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/38998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Gerrit-Change-Number: 38998 Gerrit-PatchSet: 5 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by Srinidhi N Kaushik (Code Review) 21 Feb '20

21 Feb '20

Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38998 ) Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support ...................................................................... Patch Set 4: (3 comments) > Patch Set 4: > > (1 comment) https://review.coreboot.org/c/coreboot/+/38998/4/src/mainboard/intel/tglrvp… File src/mainboard/intel/tglrvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/38998/4/src/mainboard/intel/tglrvp… PS4, Line 21: #include "board_id.h" > nit - please move local double-quoted includes to bottom of includes list Ack https://review.coreboot.org/c/coreboot/+/38998/4/src/mainboard/intel/tglrvp… PS4, Line 91: if (spd_index > 0 && spd_index != 2) { : : mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; : spd_ptr = mainboard_get_spd_data(); : : mem_cfg->MemorySpdPtr00 = spd_ptr; : mem_cfg->MemorySpdPtr02 = spd_ptr; : mem_cfg->MemorySpdPtr04 = spd_ptr; : mem_cfg->MemorySpdPtr06 = spd_ptr; : mem_cfg->MemorySpdPtr08 = spd_ptr; : mem_cfg->MemorySpdPtr10 = spd_ptr; : mem_cfg->MemorySpdPtr12 = spd_ptr; : mem_cfg->MemorySpdPtr14 = spd_ptr; : : mem_cfg->SpdAddressTable[0] = 0x0; : mem_cfg->SpdAddressTable[1] = 0x0; : mem_cfg->SpdAddressTable[2] = 0x0; : mem_cfg->SpdAddressTable[3] = 0x0; : : } else { : mem_cfg->MemorySpdPtr00 = 0; : mem_cfg->MemorySpdPtr01 = 0; : mem_cfg->MemorySpdPtr10 = 0; : mem_cfg->MemorySpdPtr11 = 0; : : mem_cfg->SpdAddressTable[0] = 0xA0; : mem_cfg->SpdAddressTable[1] = 0xA2; : mem_cfg->SpdAddressTable[2] = 0xA4; : mem_cfg->SpdAddressTable[3] = 0xA6; : : mem_cfg->RcompResistor = mem_params.rcomp_resistor; : memcpy(&mem_cfg->RcompTarget, mem_params.rcomp_target, mem_params.rcomp_target_size); : } : : memcpy(&mem_cfg->DqMapCpu2DramCh0, mem_params.dq_map, mem_params.dq_map_size); : memcpy(&mem_cfg->DqsMapCpu2DramCh0, mem_params.dqs_map, mem_params.dqs_map_size); : : mem_cfg->DqPinsInterleaved = 0; : mem_cfg->MrcSafeConfig = 0x1; : : /* Early Command Training */ : mem_cfg->ECT = 1; > Any reason why this cannot use meminit_lpddr4x_dimm0() as provided by SoC code: https://review. […] Agree Furquan, I have refactored the code to use common code in soc. Will push the change soon. https://review.coreboot.org/c/coreboot/+/38998/4/src/mainboard/intel/tglrvp… File src/mainboard/intel/tglrvp/spd/Makefile.inc: https://review.coreboot.org/c/coreboot/+/38998/4/src/mainboard/intel/tglrvp… PS4, Line 18: += > first setting of SPD_SOURCES should use "=" Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/38998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Gerrit-Change-Number: 38998 Gerrit-PatchSet: 4 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 20 Feb 2020 23:45:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP]sandybridge/optimus: Incomplete Optimus port
by Patrick Rudolph (Code Review) 20 Feb '20

20 Feb '20

Patrick Rudolph has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/23041 ) Change subject: [WIP]sandybridge/optimus: Incomplete Optimus port ...................................................................... Abandoned Replaced by CB:28380 -- To view, visit https://review.coreboot.org/c/coreboot/+/23041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1d46e063d1856db2fe7d71bc2219e3aded1f935 Gerrit-Change-Number: 23041 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Nico Rikken <nico(a)nicorikken.eu> Gerrit-Reviewer: Pablo Moyano <42.pablo.ms(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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