coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: sc7180: Add UART support
by Julius Werner (Code Review) 20 Feb '20

20 Feb '20

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35500 ) Change subject: sc7180: Add UART support ...................................................................... Patch Set 39: (2 comments) https://review.coreboot.org/c/coreboot/+/35500/39/src/soc/qualcomm/sc7180/q… File src/soc/qualcomm/sc7180/qupv3_uart.c: https://review.coreboot.org/c/coreboot/+/35500/39/src/soc/qualcomm/sc7180/q… PS39, Line 157: #ifndef __PRE_RAM__ This macro has been removed, so this #ifndef does nothing anymore. Just remove it. https://review.coreboot.org/c/coreboot/+/35500/39/src/soc/qualcomm/sc7180/q… PS39, Line 165: serial.regwidth = 4; Should add a serial.input_hertz = QUP_UART_SRC_HZ; here (QUP_UART_SRC_HZ being 7372800, see comment on other CL). -- To view, visit https://review.coreboot.org/c/coreboot/+/35500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6494daa108197c030577ac86dab71f9ca6c21bdb Gerrit-Change-Number: 35500 Gerrit-PatchSet: 39 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-CC: Satya Priya Kakitapalli <c_skakit(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Thu, 20 Feb 2020 03:51:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7180: Add QUPv3 FW load & config
by Julius Werner (Code Review) 20 Feb '20

20 Feb '20

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35499 ) Change subject: sc7180: Add QUPv3 FW load & config ...................................................................... Patch Set 39: (3 comments) https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/q… File src/soc/qualcomm/sc7180/qupv3_config.c: https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/q… PS39, Line 52: clock_configure_dfsr(bus); If the non-UART QUPs initialize their base clock here, I think it would make sense to do that for the UART as well. So you should do something like if (protocol == SE_PROTOCOL_UART) { clock_configure_qup(bus, QUP_UART_SRC_HZ); } else { ...clock_configure_dfsr... } here. (QUP_UART_SRC_HZ should be #defined to 7372800 and be used everywhere that appears in clock.c and qupv3_uart.c.) https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/q… PS39, Line 89: if (mode == GSI) { > Where is this set? I just see you set 'mode = MIXED' at the top and then never change it again. […] In earlier versions the UARTs used 'mode = FIFO', but with this patch they'll also be MIXED. Does that still work? I think it might be clearer if you just get rid of the 'mode' distinction and branch based on SE_PROTOCOL_UART where necessary. https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/q… PS39, Line 174: qup_load_se_firmware This is doing more than loading firmware (e.g. it initializes clocks), so it should have a more generic name, maybe just qupv3_init() or something. (Same goes for the name init_and_load_se_firmware()... in fact, I'm not sure if that really needs to be a separate function.) -- To view, visit https://review.coreboot.org/c/coreboot/+/35499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d91dd10488931247f81a87b0bdcc598f4bceb31 Gerrit-Change-Number: 35499 Gerrit-PatchSet: 39 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Doug Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-CC: Satya Priya Kakitapalli <c_skakit(a)qualcomm.corp-partner.google.com> Gerrit-CC: Stephen Boyd <swboyd(a)chromium.org> Gerrit-Comment-Date: Thu, 20 Feb 2020 03:47:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: sc7180: Add QUPv3 FW load & config
by Julius Werner (Code Review) 20 Feb '20

20 Feb '20

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35499 ) Change subject: sc7180: Add QUPv3 FW load & config ...................................................................... Patch Set 39: (5 comments) https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/M… File src/soc/qualcomm/sc7180/Makefile.inc: https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/M… PS39, Line 14: bootblock-y += qcom_qup_se.c Should add these to verstage and romstage as well, even if current platforms don't need it, it's nice to have the general driver toolkit available in all stages. https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/b… File src/soc/qualcomm/sc7180/bootblock.c: https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/b… PS39, Line 20: #include <soc/qi2s.h> > src/soc/qualcomm/sc7180/bootblock.c:20:10: fatal error: soc/qi2s.h: No such file or directory This is the first patch in the train, so if Jenkins gives you a -1 on it that means there's definitely still something wrong with it. https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/i… File src/soc/qualcomm/sc7180/include/soc/addressmap.h: https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/i… PS39, Line 32: 0x8C0000 Please write all 8 digits (e.g. 0x008C0000) for readability (and ideally we should sort everything in here by address, too). https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/i… File src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h: https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/i… PS39, Line 326: union proto_rx_trans_len rx_trans_len; nit: I think these would look better if you wrote them with an inline unnamed union, actually... e.g. just put union { u32 uart_tx_trans_len; u32 spi_rx_trans_len; u32 i2c_rx_trans_len; }; right in here (and same for the other two). That way you don't have to scroll up when reading this to know which fields are really merged into this slot, and you don't have to write a lengthy regs->tx_trans_len.spi_tx_trans_len everywhere (it just becomes regs->spi_tx_trans_len). https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/q… File src/soc/qualcomm/sc7180/qupv3_config.c: https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/q… PS39, Line 89: if (mode == GSI) { Where is this set? I just see you set 'mode = MIXED' at the top and then never change it again. How can we end up in any of these cases? -- To view, visit https://review.coreboot.org/c/coreboot/+/35499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d91dd10488931247f81a87b0bdcc598f4bceb31 Gerrit-Change-Number: 35499 Gerrit-PatchSet: 39 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Doug Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-CC: Satya Priya Kakitapalli <c_skakit(a)qualcomm.corp-partner.google.com> Gerrit-CC: Stephen Boyd <swboyd(a)chromium.org> Gerrit-Comment-Date: Thu, 20 Feb 2020 02:33:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu: Add initial xeonsp support boilerplate
by build bot (Jenkins) (Code Review) 19 Feb '20

19 Feb '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38838 ) Change subject: cpu: Add initial xeonsp support boilerplate ...................................................................... Patch Set 9: (2 comments) https://review.coreboot.org/c/coreboot/+/38838/9/src/cpu/intel/xeonsp/bootb… File src/cpu/intel/xeonsp/bootblock.c: https://review.coreboot.org/c/coreboot/+/38838/9/src/cpu/intel/xeonsp/bootb… PS9, Line 52: if (CONFIG(BOOTBLOCK_CONSOLE)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/c/coreboot/+/38838/9/src/cpu/intel/xeonsp/postc… File src/cpu/intel/xeonsp/postcar.c: https://review.coreboot.org/c/coreboot/+/38838/9/src/cpu/intel/xeonsp/postc… PS9, Line 20: void fill_postcar_frame(struct postcar_frame *pcf) { open brace '{' following function definitions go on the next line -- To view, visit https://review.coreboot.org/c/coreboot/+/38838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24346b8a5c30342419db23b5f1adf27d4d0ebc5f Gerrit-Change-Number: 38838 Gerrit-PatchSet: 9 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 19 Feb 2020 22:46:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard: Add OCP Tioga Pass board
by build bot (Jenkins) (Code Review) 19 Feb '20

19 Feb '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38840 ) Change subject: mainboard: Add OCP Tioga Pass board ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/38840/11/src/mainboard/ocp/tiogapa… File src/mainboard/ocp/tiogapass/bootblock.c: https://review.coreboot.org/c/coreboot/+/38840/11/src/mainboard/ocp/tiogapa… PS11, Line 46: if (CONFIG(BOOTBLOCK_CONSOLE)) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/38840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6c5da3c3856b035af5f2b3b80f0894f6fb81696 Gerrit-Change-Number: 38840 Gerrit-PatchSet: 11 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 19 Feb 2020 22:46:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard: Add OCP Tioga Pass board
by Andrey Petrov (Code Review) 19 Feb '20

19 Feb '20

Hello Jonathan Zhang, David Hendricks, Stefan Reinauer, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38840 to look at the new patch set (#11). Change subject: mainboard: Add OCP Tioga Pass board ...................................................................... mainboard: Add OCP Tioga Pass board This adds mainboard skeleton file set. Change-Id: Ic6c5da3c3856b035af5f2b3b80f0894f6fb81696 Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> --- A src/mainboard/ocp/Kconfig A src/mainboard/ocp/Kconfig.name A src/mainboard/ocp/tiogapass/Kconfig A src/mainboard/ocp/tiogapass/Kconfig.name A src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/acpi_tables.c A src/mainboard/ocp/tiogapass/board.fmd A src/mainboard/ocp/tiogapass/board_info.txt A src/mainboard/ocp/tiogapass/bootblock.c A src/mainboard/ocp/tiogapass/devicetree.cb A src/mainboard/ocp/tiogapass/dsdt.asl A src/mainboard/ocp/tiogapass/romstage.c 12 files changed, 242 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/38840/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/38840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6c5da3c3856b035af5f2b3b80f0894f6fb81696 Gerrit-Change-Number: 38840 Gerrit-PatchSet: 11 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu: Add initial xeonsp support boilerplate
by Andrey Petrov (Code Review) 19 Feb '20

19 Feb '20

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38838 to look at the new patch set (#9). Change subject: cpu: Add initial xeonsp support boilerplate ...................................................................... cpu: Add initial xeonsp support boilerplate This adds boilerplate code that is common across several Xeon SP processors. The idea is that common xeonsp code should go into cpu/intel/xeonsp/ and CPU-specific files and overrides should go into a subfolder. Change-Id: I24346b8a5c30342419db23b5f1adf27d4d0ebc5f Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> --- M src/cpu/intel/Kconfig M src/cpu/intel/Makefile.inc A src/cpu/intel/xeonsp/Kconfig A src/cpu/intel/xeonsp/Makefile.inc A src/cpu/intel/xeonsp/bootblock.c A src/cpu/intel/xeonsp/include/soc/cpu.h A src/cpu/intel/xeonsp/include/soc/gpe.h A src/cpu/intel/xeonsp/include/soc/gpio.h A src/cpu/intel/xeonsp/include/soc/iomap.h A src/cpu/intel/xeonsp/include/soc/pm.h A src/cpu/intel/xeonsp/include/soc/pmc.h A src/cpu/intel/xeonsp/include/soc/smbus.h A src/cpu/intel/xeonsp/include/soc/systemagent.h A src/cpu/intel/xeonsp/lpc.c A src/cpu/intel/xeonsp/model_xeonsp_init.c A src/cpu/intel/xeonsp/postcar.c A src/cpu/intel/xeonsp/ramstage.c A src/cpu/intel/xeonsp/romstage.c 18 files changed, 485 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/38838/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/38838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24346b8a5c30342419db23b5f1adf27d4d0ebc5f Gerrit-Change-Number: 38838 Gerrit-PatchSet: 9 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by Furquan Shaikh (Code Review) 19 Feb '20

19 Feb '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38998 ) Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/38998/4/src/mainboard/intel/tglrvp… File src/mainboard/intel/tglrvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/38998/4/src/mainboard/intel/tglrvp… PS4, Line 91: if (spd_index > 0 && spd_index != 2) { : : mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; : spd_ptr = mainboard_get_spd_data(); : : mem_cfg->MemorySpdPtr00 = spd_ptr; : mem_cfg->MemorySpdPtr02 = spd_ptr; : mem_cfg->MemorySpdPtr04 = spd_ptr; : mem_cfg->MemorySpdPtr06 = spd_ptr; : mem_cfg->MemorySpdPtr08 = spd_ptr; : mem_cfg->MemorySpdPtr10 = spd_ptr; : mem_cfg->MemorySpdPtr12 = spd_ptr; : mem_cfg->MemorySpdPtr14 = spd_ptr; : : mem_cfg->SpdAddressTable[0] = 0x0; : mem_cfg->SpdAddressTable[1] = 0x0; : mem_cfg->SpdAddressTable[2] = 0x0; : mem_cfg->SpdAddressTable[3] = 0x0; : : } else { : mem_cfg->MemorySpdPtr00 = 0; : mem_cfg->MemorySpdPtr01 = 0; : mem_cfg->MemorySpdPtr10 = 0; : mem_cfg->MemorySpdPtr11 = 0; : : mem_cfg->SpdAddressTable[0] = 0xA0; : mem_cfg->SpdAddressTable[1] = 0xA2; : mem_cfg->SpdAddressTable[2] = 0xA4; : mem_cfg->SpdAddressTable[3] = 0xA6; : : mem_cfg->RcompResistor = mem_params.rcomp_resistor; : memcpy(&mem_cfg->RcompTarget, mem_params.rcomp_target, mem_params.rcomp_target_size); : } : : memcpy(&mem_cfg->DqMapCpu2DramCh0, mem_params.dq_map, mem_params.dq_map_size); : memcpy(&mem_cfg->DqsMapCpu2DramCh0, mem_params.dqs_map, mem_params.dqs_map_size); : : mem_cfg->DqPinsInterleaved = 0; : mem_cfg->MrcSafeConfig = 0x1; : : /* Early Command Training */ : mem_cfg->ECT = 1; Any reason why this cannot use meminit_lpddr4x_dimm0() as provided by SoC code: https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/tigerlake/… You might have to extent it if you want to support reading SPD from DIMM: https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/tigerlake/…, but I think that should still save a lot of code/logic duplication here. -- To view, visit https://review.coreboot.org/c/coreboot/+/38998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Gerrit-Change-Number: 38998 Gerrit-PatchSet: 4 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Comment-Date: Wed, 19 Feb 2020 21:46:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by Wonkyu Kim (Code Review) 19 Feb '20

19 Feb '20

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38998 ) Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/38998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Gerrit-Change-Number: 38998 Gerrit-PatchSet: 4 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Comment-Date: Wed, 19 Feb 2020 21:41:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vboot: use vb2api_get_recovery_reason function
by Joel Kitching (Code Review) 19 Feb '20

19 Feb '20

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38886 ) Change subject: vboot: use vb2api_get_recovery_reason function ...................................................................... vboot: use vb2api_get_recovery_reason function Use vb2api_get_recovery_reason() API function rather than accessing vb2_shared_data internals. Of all the vanilla verified boot code in coreboot, this is the last remaining use of vboot's internal data structures in coreboot. There remains only one sole instance in Eltan's code. BUG=b:124141368, chromium:957880 TEST=make clean && make test-abuild BRANCH=none Change-Id: I845c9b14ffa830bc7de28e9a38188f7066871803 Signed-off-by: Joel Kitching <kitching(a)google.com> Cq-Depend: chromium:2055662 --- M src/security/vboot/bootmode.c 1 file changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/38886/1 diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 50b3cc3..2363bf9 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ -#define NEED_VB20_INTERNALS /* Peeking into vb2_shared_data */ - #include <assert.h> #include <bootmode.h> #include <bootstate.h> @@ -31,8 +29,7 @@ int vboot_check_recovery_request(void) { - /* TODO: Expose vb2api_recovery_reason() and vb2api_need_train_and_reboot(). */ - return vb2_get_sd(vboot_get_context())->recovery_reason; + return vb2api_get_recovery_reason(vboot_get_context()); } int vboot_recovery_mode_enabled(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/38886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I845c9b14ffa830bc7de28e9a38188f7066871803 Gerrit-Change-Number: 38886 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2020