Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38640 )
Change subject: cpu: Allow to configure microcode at pre-defined address
......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38640/6//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/38640/6//COMMIT_MSG@7
PS6, Line 7: c
> ah, now I understand what you meant. Sorry for being so tone-deaf. I believe it may be a good approach (having assembly code load ucode). I do not think it is really necessary to load ucode specifically with assembly before CAR is set up. I'd guess the only reason why would want to do it is that microcode fix is required for CAR to function properly.
It's actually pretty common to require microcode updates for CAR to function properly.
> Anyway, for now we have to use FSP-T but like I said we are planning on changing that.
Sounds like a better plan than to hack around FSP-T requirements.
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38824 )
Change subject: soc/intel/apollolake: Display platform information
......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38824/6/src/soc/intel/apollolake/r…
File src/soc/intel/apollolake/report_platform.c:
https://review.coreboot.org/c/coreboot/+/38824/6/src/soc/intel/apollolake/r…
PS6, Line 106: aes_supported = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
> The value 0 or 1 is being used as an array index into mode[], so do not want to use boolean represen […]
Sorry, I did not check. Why not use the two strings `NOT supported` and `supported`, assign variables to it, and then do
"CPU: AES %s, TXT %s, VT %s\n, aes_supported ? a : b, txt_supported ? a : b, vt_supported ? a : b
`a` and `b` should be renamed.
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Hello Patrick Rudolph, Aaron Durbin, Angel Pons, Aamir Bohra, Wonkyu Kim, Maulik V Vaghela, Duncan Laurie, Paul Menzel, build bot (Jenkins), Hannah Williams, Furquan Shaikh, Patrick Georgi, Pratikkumar V Prajapati, V Sowmya, Lance Zhao, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/26133
to look at the new patch set (#38).
Change subject: soc/intel/common/block: Move cse common functions into block/cse
......................................................................
soc/intel/common/block: Move cse common functions into block/cse
This patch cleans soc/intel/{cnl, icl, tgl} by moving common
soc code into common/block/cse.
Supported SoC can select existing HECI_DISABLE_USING_SMM option to
select common cse code block to make heci function disable using
sideband interface during SMM mode at preboot envionment.
BUG=b:78109109
TEST=Build and boot CNL, ICL and TGL platform.
Change-Id: I22a4cc05d3967c7653d2abe2c829b4876516d179
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
---
M src/soc/intel/cannonlake/smihandler.c
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/Makefile.inc
A src/soc/intel/common/block/cse/disable_heci.c
M src/soc/intel/common/block/include/intelblocks/cse.h
M src/soc/intel/icelake/smihandler.c
M src/soc/intel/tigerlake/smihandler.c
7 files changed, 76 insertions(+), 117 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/26133/38
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Gerrit-MessageType: newpatchset
Hello Aaron Durbin, Patrick Rudolph, Angel Pons, Aamir Bohra, Wonkyu Kim, Maulik V Vaghela, Jeremy Soller, Duncan Laurie, Paul Menzel, Shelley Chen, build bot (Jenkins), Hannah Williams, Furquan Shaikh, Patrick Georgi, Pratikkumar V Prajapati, V Sowmya, Lance Zhao, Krzysztof M Sywula, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/26138
to look at the new patch set (#40).
Change subject: soc/intel/common/block: Move smihandler common functions into common code
......................................................................
soc/intel/common/block: Move smihandler common functions into common code
This patch cleans soc/intel/{apl/cnl/skl/icl/tgl} by moving common soc
code into common/block/smihandler.c
BUG=b:78109109
TEST=Build and boot KBL/CNL/APL/ICL/TGL platform.
Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/soc/intel/apollolake/include/soc/pm.h
M src/soc/intel/apollolake/pmutil.c
M src/soc/intel/apollolake/smihandler.c
M src/soc/intel/cannonlake/smihandler.c
M src/soc/intel/common/block/include/intelblocks/smihandler.h
M src/soc/intel/common/block/smm/smihandler.c
M src/soc/intel/icelake/smihandler.c
M src/soc/intel/skylake/smihandler.c
M src/soc/intel/tigerlake/smihandler.c
9 files changed, 78 insertions(+), 211 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/26138/40
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Hello Aaron Durbin, Patrick Rudolph, Angel Pons, Aamir Bohra, Wonkyu Kim, Maulik V Vaghela, Jeremy Soller, Duncan Laurie, Paul Menzel, Shelley Chen, build bot (Jenkins), Hannah Williams, Furquan Shaikh, Patrick Georgi, Pratikkumar V Prajapati, V Sowmya, Lance Zhao, Krzysztof M Sywula, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/26138
to look at the new patch set (#39).
Change subject: soc/intel/common/block: Move smihandler common functions into common code
......................................................................
soc/intel/common/block: Move smihandler common functions into common code
This patch cleans soc/intel/{apl/cnl/skl/icl/tgl} by moving common soc
code into common/block/smihandler.c
BUG=b:78109109
TEST=Build and boot KBL/CNL/APL/ICL/TGL platform.
Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/soc/intel/apollolake/include/soc/pm.h
M src/soc/intel/apollolake/pmutil.c
M src/soc/intel/apollolake/smihandler.c
M src/soc/intel/cannonlake/smihandler.c
M src/soc/intel/common/block/include/intelblocks/smihandler.h
M src/soc/intel/common/block/smm/smihandler.c
M src/soc/intel/icelake/smihandler.c
M src/soc/intel/skylake/smihandler.c
M src/soc/intel/tigerlake/smihandler.c
9 files changed, 78 insertions(+), 214 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/26138/39
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26138 )
Change subject: soc/intel/common/{block, pch}: Move smihandler common functions into common code
......................................................................
Patch Set 38:
(1 comment)
https://review.coreboot.org/c/coreboot/+/26138/38/src/soc/intel/common/pch/…
File src/soc/intel/common/pch/smm/smihandler.c:
PS38:
> > get_smm_save_state_ops function returns "em64t100_smm_ops" for APL/GLK and cores are using em64t101_smm_ops
>
> Can a weak implementation of get_smm_save_state_ops() be provided in soc/intel/common/block/smm/smihandler.c that returns &em64t101_smm_ops by default and APL/GLK can provide their override?
Done
>
> > for APL/GLK below macro names are not same with cores SLP_SMI_STS, APM_SMI_STS. All small cores are using consistent macro name <something>_STS in pm.h
>
> Can all the APL/GLK *_STS bit definitions be updated to match what core does?
Done
>
> > Was thinking why we need to rename macros in APL/GLK to align with core platform. hence this file exist to maintain common core platform functions rather moving into common/block
>
> This file is adding more confusion in my opinion. This file is like common for core but not really for atom.
True, this is more like core common code based on PCH
> Wouldn't it be better to align core and atom if this code really has to be moved into soc/intel/common? and just have one single place for all smihandler routines?
moved
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Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38824 )
Change subject: soc/intel/apollolake: Display platform information
......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38824/4/src/soc/intel/apollolake/r…
File src/soc/intel/apollolake/report_platform.c:
https://review.coreboot.org/c/coreboot/+/38824/4/src/soc/intel/apollolake/r…
PS4, Line 79: u32 i
> This was missed. I’d make all counting variables `unsigned int`.
Yes i have made all the counting variables `unsigned int`in the new patch set
https://review.coreboot.org/c/coreboot/+/38824/6/src/soc/intel/apollolake/r…
File src/soc/intel/apollolake/report_platform.c:
https://review.coreboot.org/c/coreboot/+/38824/6/src/soc/intel/apollolake/r…
PS6, Line 106: aes_supported = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
> Use true and false? Do you need a ternary operator?
The value 0 or 1 is being used as an array index into mode[], so do not want to use boolean representation here. Hence would like to make vt_supported, txt_supported, aes_supported as int itself.
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38839 )
Change subject: xeonsp: Initial Skylake-SP support
......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38839/8//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/38839/8//COMMIT_MSG@7
PS8, Line 7: Initial Skylake-SP support
cpu/intel/xeonsp: Add initial Skylake-SP support
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38824 )
Change subject: soc/intel/apollolake: Display platform information
......................................................................
Patch Set 6:
(4 comments)
https://review.coreboot.org/c/coreboot/+/38824/4/src/soc/intel/apollolake/r…
File src/soc/intel/apollolake/report_platform.c:
https://review.coreboot.org/c/coreboot/+/38824/4/src/soc/intel/apollolake/r…
PS4, Line 79: u32 i
> Done
This was missed. I’d make all counting variables `unsigned int`.
https://review.coreboot.org/c/coreboot/+/38824/6/src/soc/intel/apollolake/r…
File src/soc/intel/apollolake/report_platform.c:
https://review.coreboot.org/c/coreboot/+/38824/6/src/soc/intel/apollolake/r…
PS6, Line 4: * Copyright (C) 2020 Intel Corporation.
Remove the dot at the end.
https://review.coreboot.org/c/coreboot/+/38824/6/src/soc/intel/apollolake/r…
PS6, Line 103: cpu_id, cpu_type, microcode_ver.hi);
Fits on one line?
https://review.coreboot.org/c/coreboot/+/38824/6/src/soc/intel/apollolake/r…
PS6, Line 106: aes_supported = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
Use true and false? Do you need a ternary operator?
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26138 )
Change subject: soc/intel/common/{block, pch}: Move smihandler common functions into common code
......................................................................
Patch Set 38:
(1 comment)
https://review.coreboot.org/c/coreboot/+/26138/38/src/soc/intel/common/pch/…
File src/soc/intel/common/pch/smm/smihandler.c:
PS38:
> get_smm_save_state_ops function returns "em64t100_smm_ops" for APL/GLK and cores are using em64t101_smm_ops
Can a weak implementation of get_smm_save_state_ops() be provided in soc/intel/common/block/smm/smihandler.c that returns &em64t101_smm_ops by default and APL/GLK can provide their override?
> for APL/GLK below macro names are not same with cores SLP_SMI_STS, APM_SMI_STS. All small cores are using consistent macro name <something>_STS in pm.h
Can all the APL/GLK *_STS bit definitions be updated to match what core does?
> Was thinking why we need to rename macros in APL/GLK to align with core platform. hence this file exist to maintain common core platform functions rather moving into common/block
This file is adding more confusion in my opinion. This file is like common for core but not really for atom. Wouldn't it be better to align core and atom if this code really has to be moved into soc/intel/common? and just have one single place for all smihandler routines?
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