coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

1 participants
1797 discussions

Change in coreboot[master]: util/lint: Allow non-option carrying named choices
by Nico Huber (Code Review) 19 Feb '20

19 Feb '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29813 ) Change subject: util/lint: Allow non-option carrying named choices ...................................................................... Patch Set 4: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/29813/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/29813/1//COMMIT_MSG@23 PS1, Line 23: endif > It's usually the other way around: 1. the board predefines the option with […] I'd guess it could work as long as the board code is the first to specify a default. -- To view, visit https://review.coreboot.org/c/coreboot/+/29813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6662e19685f6ab0b84c78b30aedc266c0e176039 Gerrit-Change-Number: 29813 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 19 Feb 2020 13:10:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/apollolake: use a named choice for power settings
by Patrick Georgi (Code Review) 19 Feb '20

19 Feb '20

Hello Werner Zeh, Patrick Rudolph, Mario Scheithauer, Paul Menzel, Stefan Reinauer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29814 to look at the new patch set (#4). Change subject: soc/intel/apollolake: use a named choice for power settings ...................................................................... soc/intel/apollolake: use a named choice for power settings This prevents illegal configurations. Change-Id: I88598c5e32fc48d04f7c1e987a0b2549a87da8f2 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig M src/soc/intel/apollolake/Kconfig 6 files changed, 38 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/29814/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88598c5e32fc48d04f7c1e987a0b2549a87da8f2 Gerrit-Change-Number: 29814 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/common/block/lpc: Drop unnecessary helper function
by Subrata Banik (Code Review) 19 Feb '20

19 Feb '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38952 ) Change subject: soc/intel/common/block/lpc: Drop unnecessary helper function ...................................................................... soc/intel/common/block/lpc: Drop unnecessary helper function This patch removes unnecessary helper function pch_lpc_interrupt_init() and directly making use of soc_pch_pirq_init() function to avoid redundent device NULL check. TEST=Able to build and boot CML platform. Change-Id: I3d11afb7e98f9b7f84beb2fdf308bbffeb3bbff7 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/lpc/lpc_lib.c 1 file changed, 1 insertion(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/38952/1 diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 3ad2176..5b30a81 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -270,17 +270,6 @@ gen_io_dec[i]); } -static void pch_lpc_interrupt_init(void) -{ - const struct device *dev; - - dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0); - if (!dev) - return; - - soc_pch_pirq_init(dev); -} - void pch_enable_lpc(void) { /* Lookup device tree in romstage */ @@ -295,7 +284,7 @@ lpc_set_gen_decode_range(gen_io_dec); soc_setup_dmi_pcr_io_dec(gen_io_dec); if (ENV_PAYLOAD_LOADER) - pch_lpc_interrupt_init(); + soc_pch_pirq_init(dev); } void lpc_enable_pci_clk_cntl(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/38952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d11afb7e98f9b7f84beb2fdf308bbffeb3bbff7 Gerrit-Change-Number: 38952 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

7 11

Change in coreboot[master]: soc/tigerlake: Add IRQ header and ACPI support for JSP
by Meera Ravindranath (Code Review) 19 Feb '20

19 Feb '20

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38861 ) Change subject: soc/tigerlake: Add IRQ header and ACPI support for JSP ...................................................................... soc/tigerlake: Add IRQ header and ACPI support for JSP Tigerlake irq.h and pci_irqs.asl have differences compared to Jasperlake. Hence renaming irq.h as irq_tgl.h and pci_irqs.asl as pci_irqs_tgl.asl Also adding a new file irq_jsl.h and pci_irqs_jsl.asl for Jasperlake SoC and allowing irq.h and pci_irqs.asl to choose the correct file based on SoC selected. BUG=None BRANCH=None TEST=Compilation for Jasperlake board is working Change-Id: Ia8e88f92929fe40d7be1c28947e005cb0d862fcb Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/soc/intel/tigerlake/acpi/pci_irqs.asl A src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl A src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl M src/soc/intel/tigerlake/include/soc/irq.h A src/soc/intel/tigerlake/include/soc/irq_jsl.h A src/soc/intel/tigerlake/include/soc/irq_tgl.h 6 files changed, 466 insertions(+), 216 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/38861/1 diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl index 8aadf8d..d3230b4 100644 --- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl +++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl @@ -14,155 +14,8 @@ * GNU General Public License for more details. */ -#include <soc/irq.h> - -Name (PICP, Package () { - /* D31:HSA, SMBUS, TraceHUB */ - Package(){0x001FFFFF, 3, 0, HDA_IRQ }, - Package(){0x001FFFFF, 4, 0, SMBUS_IRQ }, - Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ }, - /* D30: UART0, UART1, SPI0, SPI1 */ - Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, - Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, - Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, - Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, - /* D29: RP9 ~ RP12 */ - Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ }, - Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ }, - Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ }, - Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ }, - /* D28: RP1 ~ RP8 */ - Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, - Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, - Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, - Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, - Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ }, - Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ }, - Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ }, - Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ }, - /* D25: I2C4, I2C5, UART2 */ - Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, - Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, - Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, - /* D23: SATA */ - Package(){0x0017FFFF, 0, 0, SATA_IRQ }, - /* D22: CSME */ - Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, - Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, - Package(){0x0016FFFF, 4, 0, HECI_3_IRQ }, - Package(){0x0016FFFF, 5, 0, HECI_4_IRQ }, - /* D21: I2C0 ~ I2C3 */ - Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, - Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, - Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, - Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, - /* D20: xHCI, xDCI, SRAM, CNVI_WIFI */ - Package(){0x0014FFFF, 0, 0, xHCI_IRQ }, - Package(){0x0014FFFF, 1, 0, xDCI_IRQ }, - Package(){0x0014FFFF, 3, 0, CNVI_WIFI_IRQ }, - /* D19: SPI3 */ - Package(){0x0013FFFF, 0, 0, LPSS_SPI3_IRQ }, - /* D18: ISH, SPI2 */ - Package(){0x0012FFFF, 0, 0, ISH_IRQ }, - Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ }, - /* D16: CNVI_BT, TCH0, TCH1 */ - Package(){0x0010FFFF, 2, 0, CNVI_BT_IRQ }, - Package(){0x0010FFFF, 6, 0, THC0_IRQ }, - Package(){0x0010FFFF, 7, 0, THC1_IRQ }, - /* D13: xHCI, xDCI */ - Package(){0x000DFFFF, 0, 0, xHCI_IRQ }, - Package(){0x000DFFFF, 1, 0, xDCI_IRQ }, - /* D8: GNA */ - Package(){0x0008FFFF, 0, 0, GNA_IRQ }, - /* D7: TBT PCIe */ - Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ }, - Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ }, - Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ }, - Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ }, - /* D6: PEG60 */ - Package(){0x0006FFFF, 0, 0, PEG_IRQ }, - /* D5: IPU Device */ - Package(){0x0005FFFF, 0, 0, IPU_IRQ }, - /* D4: Thermal Device */ - Package(){0x0004FFFF, 0, 0, THERMAL_IRQ }, - /* D2: IGFX */ - Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, -}) - -Name (PICN, Package () { - /* D31:HSA, SMBUS, TraceHUB*/ - Package () { 0x001FFFFF, 3, 0, 11 }, - Package () { 0x001FFFFF, 4, 0, 11 }, - Package () { 0x001FFFFF, 7, 0, 11 }, - /* D30: UART0, UART1, SPI0, SPI1 */ - Package () { 0x001EFFFF, 0, 0, 11 }, - Package () { 0x001EFFFF, 1, 0, 10 }, - Package () { 0x001EFFFF, 2, 0, 11 }, - Package () { 0x001EFFFF, 3, 0, 11 }, - /* D29: RP9 ~ RP12 */ - Package () { 0x001DFFFF, 0, 0, 11 }, - Package () { 0x001DFFFF, 1, 0, 10 }, - Package () { 0x001DFFFF, 2, 0, 11 }, - Package () { 0x001DFFFF, 3, 0, 11 }, - /* D28: RP1 ~ RP8 */ - Package () { 0x001CFFFF, 0, 0, 11 }, - Package () { 0x001CFFFF, 1, 0, 10 }, - Package () { 0x001CFFFF, 2, 0, 11 }, - Package () { 0x001CFFFF, 3, 0, 11 }, - Package () { 0x001CFFFF, 4, 0, 11 }, - Package () { 0x001CFFFF, 5, 0, 10 }, - Package () { 0x001CFFFF, 6, 0, 11 }, - Package () { 0x001CFFFF, 7, 0, 11 }, - /* D25: I2C4, I2C5, UART2 */ - Package(){0x0019FFFF, 0, 0, 11 }, - Package(){0x0019FFFF, 1, 0, 10 }, - Package(){0x0019FFFF, 2, 0, 11 }, - /* D23: SATA */ - Package () { 0x0017FFFF, 0, 0, 11 }, - /* D22: CSME */ - Package(){0x0016FFFF, 0, 0, 11 }, - Package(){0x0016FFFF, 1, 0, 10 }, - Package(){0x0016FFFF, 4, 0, 11 }, - Package(){0x0016FFFF, 5, 0, 11 }, - /* D21: I2C0 ~ I2C3 */ - Package(){0x0015FFFF, 0, 0, 11 }, - Package(){0x0015FFFF, 1, 0, 10 }, - Package(){0x0015FFFF, 2, 0, 11 }, - Package(){0x0015FFFF, 3, 0, 11 }, - /* D19: SPI3 */ - Package(){0x0013FFFF, 0, 0, 11 }, - /* D18: ISH, SPI2 */ - Package(){0x0012FFFF, 0, 0, 11 }, - Package(){0x0012FFFF, 6, 0, 11 },, - /* D16: CNVI_BT, TCH0, TCH1 */ - Package(){0x0010FFFF, 2, 0, 11 }, - Package(){0x0010FFFF, 6, 0, 11 }, - Package(){0x0010FFFF, 7, 0, 10 }, - /* D13: xHCI, xDCI */ - Package(){0x000DFFFF, 0, 0, 11 }, - Package(){0x000DFFFF, 1, 0, 10 }, - /* D8: GNA */ - Package(){0x0008FFFF, 0, 0, 11 }, - /* D7: TBT PCIe */ - Package(){0x0007FFFF, 0, 0, 11 }, - Package(){0x0007FFFF, 1, 0, 10 }, - Package(){0x0007FFFF, 2, 0, 11 }, - Package(){0x0007FFFF, 3, 0, 11 }, - /* D6: PEG60 */ - Package(){0x0006FFFF, 0, 0, 11 }, - /* D5: IPU Device */ - Package(){0x0005FFFF, 0, 0, 11 }, - /* D4: Thermal Device */ - Package(){0x0004FFFF, 0, 0, 11 }, - /* D2: IGFX */ - Package(){0x0002FFFF, 0, 0, 11 }, -}) - -Method (_PRT) -{ - If (PICM) { - Return (^PICP) - } Else { - Return (^PICN) - } -} +#if CONFIG(SOC_INTEL_TIGERLAKE) + #include "pci_irqs_tgl.asl" +#else + #include "pci_irqs_jsl.asl" +#endif diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl b/src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl new file mode 100644 index 0000000..5e28c61 --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl @@ -0,0 +1,118 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/irq.h> + +Name (PICP, Package () { + /* cAVS, SMBus, GbE, Nothpeak */ + Package(){0x001FFFFF, 3, 0, cAVS_INTA_IRQ }, + Package(){0x001FFFFF, 4, 0, SMBUS_INTB_IRQ }, + Package(){0x001FFFFF, 6, 0, GbE_INTC_IRQ }, + Package(){0x001FFFFF, 7, 0, TRACE_HUB_INTD_IRQ }, + /* SerialIo and SCS */ + Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, + Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, + Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, + Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, + /* PCI Express Port 1-8 */ + Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, + Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, + Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, + Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, + Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ }, + Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ }, + Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ }, + Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ }, + /* eMMC */ + Package(){0x001AFFFF, 0, 0, eMMC_IRQ }, + /* SerialIo */ + Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, + Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, + Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, + /* SATA controller */ + Package(){0x0017FFFF, 0, 0, SATA_IRQ }, + /* CSME (HECI, IDE-R, Keyboard and Text redirection */ + Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, + Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, + Package(){0x0016FFFF, 2, 0, IDER_IRQ }, + Package(){0x0016FFFF, 3, 0, KT_IRQ }, + Package(){0x0016FFFF, 4, 0, HECI_3_IRQ }, + /* SerialIo */ + Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, + Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, + Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, + Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, + /* D20: xHCI, OTG, SRAM, CNVi WiFi */ + Package(){0x0014FFFF, 0, 0, XHCI_IRQ }, + Package(){0x0014FFFF, 1, 0, OTG_IRQ }, + Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ }, + Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ }, + Package(){0x0014FFFF, 5, 0, SD_IRQ }, + /* SA IGFX Device */ + Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, + /* SA Thermal Device */ + Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ }, + /* SA IPU Device */ + Package(){0x0005FFFF, 0, 0, IPU_IRQ }, + /* SA GNA Device */ + Package(){0x0008FFFF, 0, 0, GNA_IRQ }, +}) + +Name (PICN, Package () { + /* D31: cAVS, SMBus, GbE, Nothpeak */ + Package () { 0x001FFFFF, 3, 0, 11 }, + Package () { 0x001FFFFF, 4, 0, 10 }, + Package () { 0x001FFFFF, 6, 0, 11 }, + Package () { 0x001FFFFF, 7, 0, 11 }, + /* D28: PCI Express Port 1-8 */ + Package () { 0x001CFFFF, 0, 0, 11 }, + Package () { 0x001CFFFF, 1, 0, 10 }, + Package () { 0x001CFFFF, 2, 0, 11 }, + Package () { 0x001CFFFF, 3, 0, 11 }, + Package () { 0x001CFFFF, 4, 0, 11 }, + Package () { 0x001CFFFF, 5, 0, 10 }, + Package () { 0x001CFFFF, 6, 0, 11 }, + Package () { 0x001CFFFF, 7, 0, 11 }, + /* D23: SATA controller */ + Package () { 0x0017FFFF, 0, 0, 11 }, + /* D22: CSME (HECI, IDE-R, KT redirection */ + Package () { 0x0016FFFF, 0, 0, 11 }, + Package () { 0x0016FFFF, 1, 0, 10 }, + Package () { 0x0016FFFF, 2, 0, 11 }, + Package () { 0x0016FFFF, 3, 0, 11 }, + Package () { 0x0016FFFF, 4, 0, 11 }, + /* D20: xHCI, OTG, SRAM, CNVi WiFi */ + Package () { 0x0014FFFF, 0, 0, 11 }, + Package () { 0x0014FFFF, 1, 0, 10 }, + Package () { 0x0014FFFF, 2, 0, 11 }, + Package () { 0x0014FFFF, 3, 0, 11 }, + Package () { 0x0014FFFF, 5, 0, 11 }, + /* SA Thermal Device */ + Package () { 0x0004FFFF, 0, 0, 11 }, + /* SA IPU Device */ + Package () { 0x0005FFFF, 0, 0, 11 }, + /* SA GNA Device */ + Package () { 0x0008FFFF, 0, 0, 11 }, +}) + +Method (_PRT) +{ + If (PICM) { + Return (^PICP) + } Else { + Return (^PICN) + } +} diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl b/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl new file mode 100644 index 0000000..8aadf8d --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl @@ -0,0 +1,168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/irq.h> + +Name (PICP, Package () { + /* D31:HSA, SMBUS, TraceHUB */ + Package(){0x001FFFFF, 3, 0, HDA_IRQ }, + Package(){0x001FFFFF, 4, 0, SMBUS_IRQ }, + Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ }, + /* D30: UART0, UART1, SPI0, SPI1 */ + Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, + Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, + Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, + Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, + /* D29: RP9 ~ RP12 */ + Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ }, + Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ }, + Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ }, + Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ }, + /* D28: RP1 ~ RP8 */ + Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, + Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, + Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, + Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, + Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ }, + Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ }, + Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ }, + Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ }, + /* D25: I2C4, I2C5, UART2 */ + Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, + Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, + Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, + /* D23: SATA */ + Package(){0x0017FFFF, 0, 0, SATA_IRQ }, + /* D22: CSME */ + Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, + Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, + Package(){0x0016FFFF, 4, 0, HECI_3_IRQ }, + Package(){0x0016FFFF, 5, 0, HECI_4_IRQ }, + /* D21: I2C0 ~ I2C3 */ + Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, + Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, + Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, + Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, + /* D20: xHCI, xDCI, SRAM, CNVI_WIFI */ + Package(){0x0014FFFF, 0, 0, xHCI_IRQ }, + Package(){0x0014FFFF, 1, 0, xDCI_IRQ }, + Package(){0x0014FFFF, 3, 0, CNVI_WIFI_IRQ }, + /* D19: SPI3 */ + Package(){0x0013FFFF, 0, 0, LPSS_SPI3_IRQ }, + /* D18: ISH, SPI2 */ + Package(){0x0012FFFF, 0, 0, ISH_IRQ }, + Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ }, + /* D16: CNVI_BT, TCH0, TCH1 */ + Package(){0x0010FFFF, 2, 0, CNVI_BT_IRQ }, + Package(){0x0010FFFF, 6, 0, THC0_IRQ }, + Package(){0x0010FFFF, 7, 0, THC1_IRQ }, + /* D13: xHCI, xDCI */ + Package(){0x000DFFFF, 0, 0, xHCI_IRQ }, + Package(){0x000DFFFF, 1, 0, xDCI_IRQ }, + /* D8: GNA */ + Package(){0x0008FFFF, 0, 0, GNA_IRQ }, + /* D7: TBT PCIe */ + Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ }, + Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ }, + Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ }, + Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ }, + /* D6: PEG60 */ + Package(){0x0006FFFF, 0, 0, PEG_IRQ }, + /* D5: IPU Device */ + Package(){0x0005FFFF, 0, 0, IPU_IRQ }, + /* D4: Thermal Device */ + Package(){0x0004FFFF, 0, 0, THERMAL_IRQ }, + /* D2: IGFX */ + Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, +}) + +Name (PICN, Package () { + /* D31:HSA, SMBUS, TraceHUB*/ + Package () { 0x001FFFFF, 3, 0, 11 }, + Package () { 0x001FFFFF, 4, 0, 11 }, + Package () { 0x001FFFFF, 7, 0, 11 }, + /* D30: UART0, UART1, SPI0, SPI1 */ + Package () { 0x001EFFFF, 0, 0, 11 }, + Package () { 0x001EFFFF, 1, 0, 10 }, + Package () { 0x001EFFFF, 2, 0, 11 }, + Package () { 0x001EFFFF, 3, 0, 11 }, + /* D29: RP9 ~ RP12 */ + Package () { 0x001DFFFF, 0, 0, 11 }, + Package () { 0x001DFFFF, 1, 0, 10 }, + Package () { 0x001DFFFF, 2, 0, 11 }, + Package () { 0x001DFFFF, 3, 0, 11 }, + /* D28: RP1 ~ RP8 */ + Package () { 0x001CFFFF, 0, 0, 11 }, + Package () { 0x001CFFFF, 1, 0, 10 }, + Package () { 0x001CFFFF, 2, 0, 11 }, + Package () { 0x001CFFFF, 3, 0, 11 }, + Package () { 0x001CFFFF, 4, 0, 11 }, + Package () { 0x001CFFFF, 5, 0, 10 }, + Package () { 0x001CFFFF, 6, 0, 11 }, + Package () { 0x001CFFFF, 7, 0, 11 }, + /* D25: I2C4, I2C5, UART2 */ + Package(){0x0019FFFF, 0, 0, 11 }, + Package(){0x0019FFFF, 1, 0, 10 }, + Package(){0x0019FFFF, 2, 0, 11 }, + /* D23: SATA */ + Package () { 0x0017FFFF, 0, 0, 11 }, + /* D22: CSME */ + Package(){0x0016FFFF, 0, 0, 11 }, + Package(){0x0016FFFF, 1, 0, 10 }, + Package(){0x0016FFFF, 4, 0, 11 }, + Package(){0x0016FFFF, 5, 0, 11 }, + /* D21: I2C0 ~ I2C3 */ + Package(){0x0015FFFF, 0, 0, 11 }, + Package(){0x0015FFFF, 1, 0, 10 }, + Package(){0x0015FFFF, 2, 0, 11 }, + Package(){0x0015FFFF, 3, 0, 11 }, + /* D19: SPI3 */ + Package(){0x0013FFFF, 0, 0, 11 }, + /* D18: ISH, SPI2 */ + Package(){0x0012FFFF, 0, 0, 11 }, + Package(){0x0012FFFF, 6, 0, 11 },, + /* D16: CNVI_BT, TCH0, TCH1 */ + Package(){0x0010FFFF, 2, 0, 11 }, + Package(){0x0010FFFF, 6, 0, 11 }, + Package(){0x0010FFFF, 7, 0, 10 }, + /* D13: xHCI, xDCI */ + Package(){0x000DFFFF, 0, 0, 11 }, + Package(){0x000DFFFF, 1, 0, 10 }, + /* D8: GNA */ + Package(){0x0008FFFF, 0, 0, 11 }, + /* D7: TBT PCIe */ + Package(){0x0007FFFF, 0, 0, 11 }, + Package(){0x0007FFFF, 1, 0, 10 }, + Package(){0x0007FFFF, 2, 0, 11 }, + Package(){0x0007FFFF, 3, 0, 11 }, + /* D6: PEG60 */ + Package(){0x0006FFFF, 0, 0, 11 }, + /* D5: IPU Device */ + Package(){0x0005FFFF, 0, 0, 11 }, + /* D4: Thermal Device */ + Package(){0x0004FFFF, 0, 0, 11 }, + /* D2: IGFX */ + Package(){0x0002FFFF, 0, 0, 11 }, +}) + +Method (_PRT) +{ + If (PICM) { + Return (^PICP) + } Else { + Return (^PICN) + } +} diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h index 4d6318f..dec8376 100644 --- a/src/soc/intel/tigerlake/include/soc/irq.h +++ b/src/soc/intel/tigerlake/include/soc/irq.h @@ -16,69 +16,10 @@ #ifndef _SOC_IRQ_H_ #define _SOC_IRQ_H_ -#define GPIO_IRQ14 14 -#define GPIO_IRQ15 15 +#if CONFIG(SOC_INTEL_TIGERLAKE) + #include "irq_tgl.h" +#else + #include "irq_jsl.h" +#endif /* CONFIG_SOC_INTEL_TIGERLAKE */ -#define PCH_IRQ10 10 -#define PCH_IRQ11 11 - -#define LPSS_I2C0_IRQ 27 -#define LPSS_I2C1_IRQ 28 -#define LPSS_I2C2_IRQ 29 -#define LPSS_I2C3_IRQ 30 -#define LPSS_I2C4_IRQ 31 -#define LPSS_I2C5_IRQ 32 -#define LPSS_SPI0_IRQ 36 -#define LPSS_SPI1_IRQ 37 -#define LPSS_SPI2_IRQ 18 -#define LPSS_SPI3_IRQ 23 -#define LPSS_UART0_IRQ 34 -#define LPSS_UART1_IRQ 35 -#define LPSS_UART2_IRQ 33 - -#define HDA_IRQ 16 -#define SMBUS_IRQ 16 -#define TRACEHUB_IRQ 16 - -#define PCIE_1_IRQ 16 -#define PCIE_2_IRQ 17 -#define PCIE_3_IRQ 18 -#define PCIE_4_IRQ 19 -#define PCIE_5_IRQ 16 -#define PCIE_6_IRQ 17 -#define PCIE_7_IRQ 18 -#define PCIE_8_IRQ 19 -#define PCIE_9_IRQ 16 -#define PCIE_10_IRQ 17 -#define PCIE_11_IRQ 18 -#define PCIE_12_IRQ 19 - -#define SATA_IRQ 16 - -#define xHCI_IRQ 16 -#define xDCI_IRQ 17 -#define CNVI_WIFI_IRQ 16 - -#define CNVI_BT_IRQ 18 - -#define THC0_IRQ 16 -#define THC1_IRQ 17 - -#define ISH_IRQ 16 - -#define TBT_PCIe0_IRQ 16 -#define TBT_PCIe1_IRQ 17 -#define TBT_PCIe2_IRQ 18 -#define TBT_PCIe3_IRQ 19 - -#define HECI_1_IRQ 16 -#define HECI_2_IRQ 17 -#define HECI_3_IRQ 16 -#define HECI_4_IRQ 19 - -#define PEG_IRQ 16 -#define IGFX_IRQ 16 -#define THERMAL_IRQ 16 -#define IPU_IRQ 16 -#define GNA_IRQ 16 #endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/irq_jsl.h b/src/soc/intel/tigerlake/include/soc/irq_jsl.h new file mode 100644 index 0000000..e95b87a --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/irq_jsl.h @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_JSL_IRQ_H_ +#define _SOC_JSL_IRQ_H_ + +#define GPIO_IRQ14 14 +#define GPIO_IRQ15 15 + +#define PCH_IRQ10 10 +#define PCH_IRQ11 11 + +/* LPSS Devices */ +#define LPSS_I2C0_IRQ 16 +#define LPSS_I2C1_IRQ 17 +#define LPSS_I2C2_IRQ 18 +#define LPSS_I2C3_IRQ 19 +#define LPSS_I2C4_IRQ 32 +#define LPSS_I2C5_IRQ 33 +#define LPSS_SPI0_IRQ 22 +#define LPSS_SPI1_IRQ 23 +#define LPSS_SPI2_IRQ 24 +#define LPSS_UART0_IRQ 20 +#define LPSS_UART1_IRQ 21 +#define LPSS_UART2_IRQ 34 + +/* PCI D:31 F:x */ +#define cAVS_INTA_IRQ 16 +#define SMBUS_INTA_IRQ 16 +#define SMBUS_INTB_IRQ 17 +#define GbE_INTA_IRQ 16 +#define GbE_INTC_IRQ 18 +#define TRACE_HUB_INTA_IRQ 16 +#define TRACE_HUB_INTD_IRQ 19 + +/* PCI D:28 F:x */ +#define PCIE_1_IRQ 16 +#define PCIE_2_IRQ 17 +#define PCIE_3_IRQ 18 +#define PCIE_4_IRQ 19 +#define PCIE_5_IRQ 16 +#define PCIE_6_IRQ 17 +#define PCIE_7_IRQ 18 +#define PCIE_8_IRQ 19 + +/* PCI D:26 F:x */ +#define eMMC_IRQ 16 + +/* PCI D:23 F:x */ +#define SATA_IRQ 16 + +/* PCI D:22 F:x */ +#define HECI_1_IRQ 16 +#define HECI_2_IRQ 17 +#define HECI_3_IRQ 16 +#define IDER_IRQ 18 +#define KT_IRQ 19 + +/* PCI D:20 F:x */ +#define XHCI_IRQ 16 +#define OTG_IRQ 17 +#define CNViWIFI_IRQ 16 +#define SD_IRQ 19 +#define PMC_SRAM_IRQ 18 + +/* PCI D:18 F:x */ +#define UFS_IRQ 16 + +#define IGFX_IRQ 16 +#define SA_THERMAL_IRQ 16 +#define IPU_IRQ 16 +#define GNA_IRQ 16 + +#endif /* _JSL_IRQ_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/irq_tgl.h b/src/soc/intel/tigerlake/include/soc/irq_tgl.h new file mode 100644 index 0000000..0ea6053 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/irq_tgl.h @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TGL_IRQ_H_ +#define _SOC_TGL_IRQ_H_ + +#define GPIO_IRQ14 14 +#define GPIO_IRQ15 15 + +#define PCH_IRQ10 10 +#define PCH_IRQ11 11 + +#define LPSS_I2C0_IRQ 27 +#define LPSS_I2C1_IRQ 28 +#define LPSS_I2C2_IRQ 29 +#define LPSS_I2C3_IRQ 30 +#define LPSS_I2C4_IRQ 31 +#define LPSS_I2C5_IRQ 32 +#define LPSS_SPI0_IRQ 36 +#define LPSS_SPI1_IRQ 37 +#define LPSS_SPI2_IRQ 18 +#define LPSS_SPI3_IRQ 23 +#define LPSS_UART0_IRQ 34 +#define LPSS_UART1_IRQ 35 +#define LPSS_UART2_IRQ 33 + +#define HDA_IRQ 16 +#define SMBUS_IRQ 16 +#define TRACEHUB_IRQ 16 + +#define PCIE_1_IRQ 16 +#define PCIE_2_IRQ 17 +#define PCIE_3_IRQ 18 +#define PCIE_4_IRQ 19 +#define PCIE_5_IRQ 16 +#define PCIE_6_IRQ 17 +#define PCIE_7_IRQ 18 +#define PCIE_8_IRQ 19 +#define PCIE_9_IRQ 16 +#define PCIE_10_IRQ 17 +#define PCIE_11_IRQ 18 +#define PCIE_12_IRQ 19 + +#define SATA_IRQ 16 + +#define xHCI_IRQ 16 +#define xDCI_IRQ 17 +#define CNVI_WIFI_IRQ 16 + +#define CNVI_BT_IRQ 18 + +#define THC0_IRQ 16 +#define THC1_IRQ 17 + +#define ISH_IRQ 16 + +#define TBT_PCIe0_IRQ 16 +#define TBT_PCIe1_IRQ 17 +#define TBT_PCIe2_IRQ 18 +#define TBT_PCIe3_IRQ 19 + +#define HECI_1_IRQ 16 +#define HECI_2_IRQ 17 +#define HECI_3_IRQ 16 +#define HECI_4_IRQ 19 + +#define PEG_IRQ 16 +#define IGFX_IRQ 16 +#define THERMAL_IRQ 16 +#define IPU_IRQ 16 +#define GNA_IRQ 16 +#endif /* _TGL_IRQ_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8e88f92929fe40d7be1c28947e005cb0d862fcb Gerrit-Change-Number: 38861 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: Documentation: soc/amd/psp: Use real table markup
by Evgeny Zinoviev (Code Review) 19 Feb '20

19 Feb '20

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38956 ) Change subject: Documentation: soc/amd/psp: Use real table markup ...................................................................... Documentation: soc/amd/psp: Use real table markup Currently, tables on this page are formatted as code blocks with ASCII tables. Make it real beautiful tables. Change-Id: I3c46477352b8151f3b0fb0616f909531a0a15c34 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M Documentation/soc/amd/psp_integration.md 1 file changed, 136 insertions(+), 129 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/38956/1 diff --git a/Documentation/soc/amd/psp_integration.md b/Documentation/soc/amd/psp_integration.md index 5f53a39..9c7b1be 100755 --- a/Documentation/soc/amd/psp_integration.md +++ b/Documentation/soc/amd/psp_integration.md @@ -37,38 +37,40 @@ structure (for all families combined). Individual features supported vary by family and model. - +--------------+---------------+------------------+----------------------------+ - | Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose | - +--------------+---------------+------------------+----------------------------+ - | Signature | 0x00 | 4 | 0x55aa55aa | - |--------------|---------------|------------------|----------------------------| - | IMC FW | 0x04 | 4 | Integrated Micro | - | | | | Controller: unsupported | - | | | | but functional in some | - | | | | systems | - |--------------|---------------|------------------|----------------------------| - | GbE FW | 0x08 | 4 | Gigabit Ethernet | - |--------------|---------------|------------------|----------------------------| - | xHCI FW | 0x0c | 4 | xHCI firmware | - |--------------|---------------|------------------|----------------------------| - | PSP Dir Tbl | 0x10 | 4 | Pointer to PSP Directory | - | | | | Table (early devices) | - |--------------|---------------|------------------|----------------------------| - | PSP Dir Tbl | 0x14 | 4 | Pointer to PSP Directory | - | | | | Table (later devices and | - | | | | is combo capable) | - |--------------|---------------|------------------|----------------------------| - | BIOS Dir Tbl | 0x18 | 4 | Pointer to BIOS Directory | - | | | | Table for models n* | - |--------------|---------------|------------------|----------------------------| - | BIOS Dir Tbl | 0x1c | 4 | Pointer to BIOS Directory | - | | | | Table for models nn | - |--------------|---------------|------------------|----------------------------| - | BIOS Dir Tbl | 0x20 | 4 | Pointer to BIOS Directory | - | | | | Table for models nnn | - |--------------|---------------|------------------|----------------------------| - | … | | | ... | - +--------------+---------------+------------------+----------------------------+ +```eval_rst ++--------------+---------------+------------------+----------------------------+ +| Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose | ++==============+===============+==================+============================+ +| Signature | 0x00 | 4 | 0x55aa55aa | ++--------------+---------------+------------------+----------------------------+ +| IMC FW | 0x04 | 4 | Integrated Micro | +| | | | Controller: unsupported | +| | | | but functional in some | +| | | | systems | ++--------------+---------------+------------------+----------------------------+ +| GbE FW | 0x08 | 4 | Gigabit Ethernet | ++--------------+---------------+------------------+----------------------------+ +| xHCI FW | 0x0c | 4 | xHCI firmware | ++--------------+---------------+------------------+----------------------------+ +| PSP Dir Tbl | 0x10 | 4 | Pointer to PSP Directory | +| | | | Table (early devices) | ++--------------+---------------+------------------+----------------------------+ +| PSP Dir Tbl | 0x14 | 4 | Pointer to PSP Directory | +| | | | Table (later devices and | +| | | | is combo capable) | ++--------------+---------------+------------------+----------------------------+ +| BIOS Dir Tbl | 0x18 | 4 | Pointer to BIOS Directory | +| | | | Table for models n* | ++--------------+---------------+------------------+----------------------------+ +| BIOS Dir Tbl | 0x1c | 4 | Pointer to BIOS Directory | +| | | | Table for models nn | ++--------------+---------------+------------------+----------------------------+ +| BIOS Dir Tbl | 0x20 | 4 | Pointer to BIOS Directory | +| | | | Table for models nnn | ++--------------+---------------+------------------+----------------------------+ +| … | | | ... | ++--------------+---------------+------------------+----------------------------+ +``` * The Embedded Firmware Structure may support pointers to multiple generations of devices, e.g. Family 17h Models 00h-0Fh, Family 17h Models 10h-1Fh, etc. @@ -83,46 +85,47 @@ implementations currently use combo tables. ### PSP Directory Table Header - - +--------------+---------------+------------------+----------------------------+ - | Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose | - +--------------+---------------+------------------+----------------------------+ - | PSP Cookie | 0x00 | 4 | PSP cookie "$PSP" to | - | | | | recognize the header. | - | | | | Cookie “$PL2” for level 2 | - |--------------|---------------|------------------|----------------------------| - | Checksum | 0x04 | 4 | 32-bit CRC value of header | - | | | | below this field and | - | | | | including all entries | - |--------------|---------------|------------------|----------------------------| - | Total Entries| 0x08 | 4 | Number of PSP Directory | - | | | | entries in the table | - |--------------|---------------|------------------|----------------------------| - | Reserved | 0x0C | 4 | Reserved - Set to zero | - +--------------+---------------+------------------+----------------------------+ +```eval_rst ++--------------+---------------+------------------+----------------------------+ +| Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose | ++==============+===============+==================+============================+ +| PSP Cookie | 0x00 | 4 | PSP cookie "$PSP" to | +| | | | recognize the header. | +| | | | Cookie “$PL2” for level 2 | ++--------------+---------------+------------------+----------------------------+ +| Checksum | 0x04 | 4 | 32-bit CRC value of header | +| | | | below this field and | +| | | | including all entries | ++--------------+---------------+------------------+----------------------------+ +| Total Entries| 0x08 | 4 | Number of PSP Directory | +| | | | entries in the table | ++--------------+---------------+------------------+----------------------------+ +| Reserved | 0x0C | 4 | Reserved - Set to zero | ++--------------+---------------+------------------+----------------------------+ +``` ### PSP Directory Table Entries - - +--------------+---------------+------------------+----------------------------+ - | Field Name | Offset (Hex) | Size (In Bits) | Description/Purpose | - +--------------+---------------+------------------+----------------------------+ - | Type | 0x00 | 8 | Entry type (see below) | - |--------------|---------------|------------------|----------------------------| - | Sub Program | 0x01 | 8 | Specifies sub program | - |--------------|---------------|------------------|----------------------------| - | Reserved | 0x02 | 16 | Reserved - set to 0 | - |--------------|---------------|------------------|----------------------------| - | Size | 0x04 | 32 | Size of PSP entry in bytes | - |--------------|---------------|------------------|----------------------------| - | Location / | 0x08 | 64 | Location: Physical Address | - | Value | | | of SPIROM location where | - | | | | corresponding PSP entry | - | | | | located. | - | | | | | - | | | | Value: 64-bit value for the| - | | | | PSP Entry | - +--------------+---------------+------------------+----------------------------+ - +```eval_rst ++--------------+---------------+------------------+----------------------------+ +| Field Name | Offset (Hex) | Size (In Bits) | Description/Purpose | ++==============+===============+==================+============================+ +| Type | 0x00 | 8 | Entry type (see below) | ++--------------+---------------+------------------+----------------------------+ +| Sub Program | 0x01 | 8 | Specifies sub program | ++--------------+---------------+------------------+----------------------------+ +| Reserved | 0x02 | 16 | Reserved - set to 0 | ++--------------+---------------+------------------+----------------------------+ +| Size | 0x04 | 32 | Size of PSP entry in bytes | ++--------------+---------------+------------------+----------------------------+ +| Location / | 0x08 | 64 | Location: Physical Address | +| Value | | | of SPIROM location where | +| | | | corresponding PSP entry | +| | | | located. | +| | | | | +| | | | Value: 64-bit value for the| +| | | | PSP Entry | ++--------------+---------------+------------------+----------------------------+ +``` ### PSP Directory Table Types **0x00**: AMD public key @@ -248,68 +251,72 @@ ### BIOS Directory Table Header - +--------------+---------------+------------------+----------------------------+ - | Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose | - +--------------+---------------+------------------+----------------------------+ - | BIOS Cookie | 0x00 | 4 | BIOS cookie "$BHD" to | - | | | | recognize the header. | - | | | | Cookie “$BL2” for level 2 | - |--------------|---------------|------------------|----------------------------| - | Checksum | 0x04 | 4 | 32 bit CRC value of header | - | | | | below this field and | - | | | | including all entries | - |--------------|---------------|------------------|----------------------------| - | Total Entries| 0x08 | 4 | Number of BIOS Directory | - | | | | entries in the table | - |--------------|---------------|------------------|----------------------------| - | Reserved | 0x0C | 4 | Reserved - Set to zero | - +--------------+---------------+------------------+----------------------------+ +```eval_rst ++--------------+---------------+------------------+----------------------------+ +| Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose | ++==============+===============+==================+============================+ +| BIOS Cookie | 0x00 | 4 | BIOS cookie "$BHD" to | +| | | | recognize the header. | +| | | | Cookie “$BL2” for level 2 | ++--------------+---------------+------------------+----------------------------+ +| Checksum | 0x04 | 4 | 32 bit CRC value of header | +| | | | below this field and | +| | | | including all entries | ++--------------+---------------+------------------+----------------------------+ +| Total Entries| 0x08 | 4 | Number of BIOS Directory | +| | | | entries in the table | ++--------------+---------------+------------------+----------------------------+ +| Reserved | 0x0C | 4 | Reserved - Set to zero | ++--------------+---------------+------------------+----------------------------+ +``` ### BIOS Directory Table Entries - +--------------+---------------+------------------+----------------------------+ - | Field Name | Offset (Hex) | Size (In Bits) | Description/Purpose | - +--------------+---------------+------------------+----------------------------+ - | Type | 0x00 | 8 | Entry type (see below) | - |--------------|---------------|------------------|----------------------------| - | Region Type | 0x01 | 8 | Setup the memory region's | - | | | | security attribute for the | - | | | | BIOS entry | - |--------------|---------------|------------------|----------------------------| - | Reset Image | 0x02[0] | 1 | Boolean value to define the| - | | | | BIOS entry is a reset | - | | | | binary image | - |--------------|---------------|------------------|----------------------------| - | Copy Image | 0x02[1] | 1 | Define the binary image of | - | | | | the BIOS entry is for | - | | | | copying over to the memory | - | | | | region | - |--------------|---------------|------------------|----------------------------| - | Read Only | 0x02[2] | 1 | Setup the memory region for| - | | | | the BIOS entry to read only| - |--------------|---------------|------------------|----------------------------| - | Compressed | 0x02[3] | 1 | Compressed using zlib | - | | | | | - |--------------|---------------|------------------|----------------------------| - | Instance | 0x02[7:4] | 4 | Specify the Instance of an | - | | | | entry | - |--------------|---------------|------------------|----------------------------| - | SubProgram | 0x03[2:0] | 3 | Specify the SubProgram | - |--------------|---------------|------------------|----------------------------| - | Reserved | 0x03[7:3] | 5 | Reserved - Set to zero | - |--------------|---------------|------------------|----------------------------| - | Size | 0x04 | 32 | Memory Region Size | - |--------------|---------------|------------------|----------------------------| - | Source | 0x08 | 64 | Physical Address of SPIROM | - | Address | | | location where the data for| - | | | | the corresponding entry is | - | | | | located | - |--------------|---------------|------------------|----------------------------| - | Destination | 0x10 | 64 | Destination Address of | - | Address | | | memory location where the | - | | | | data for the corresponding | - | | | | BIOS Entry is copied | - +--------------+---------------+------------------+----------------------------+ +```eval_rst ++--------------+---------------+------------------+----------------------------+ +| Field Name | Offset (Hex) | Size (In Bits) | Description/Purpose | ++==============+===============+==================+============================+ +| Type | 0x00 | 8 | Entry type (see below) | ++--------------+---------------+------------------+----------------------------+ +| Region Type | 0x01 | 8 | Setup the memory region's | +| | | | security attribute for the | +| | | | BIOS entry | ++--------------+---------------+------------------+----------------------------+ +| Reset Image | 0x02[0] | 1 | Boolean value to define the| +| | | | BIOS entry is a reset | +| | | | binary image | ++--------------+---------------+------------------+----------------------------+ +| Copy Image | 0x02[1] | 1 | Define the binary image of | +| | | | the BIOS entry is for | +| | | | copying over to the memory | +| | | | region | ++--------------+---------------+------------------+----------------------------+ +| Read Only | 0x02[2] | 1 | Setup the memory region for| +| | | | the BIOS entry to read only| ++--------------+---------------+------------------+----------------------------+ +| Compressed | 0x02[3] | 1 | Compressed using zlib | +| | | | | ++--------------+---------------+------------------+----------------------------+ +| Instance | 0x02[7:4] | 4 | Specify the Instance of an | +| | | | entry | ++--------------+---------------+------------------+----------------------------+ +| SubProgram | 0x03[2:0] | 3 | Specify the SubProgram | ++--------------+---------------+------------------+----------------------------+ +| Reserved | 0x03[7:3] | 5 | Reserved - Set to zero | ++--------------+---------------+------------------+----------------------------+ +| Size | 0x04 | 32 | Memory Region Size | ++--------------+---------------+------------------+----------------------------+ +| Source | 0x08 | 64 | Physical Address of SPIROM | +| Address | | | location where the data for| +| | | | the corresponding entry is | +| | | | located | ++--------------+---------------+------------------+----------------------------+ +| Destination | 0x10 | 64 | Destination Address of | +| Address | | | memory location where the | +| | | | data for the corresponding | +| | | | BIOS Entry is copied | ++--------------+---------------+------------------+----------------------------+ +``` ### BIOS Directory Table Entry Types -- To view, visit https://review.coreboot.org/c/coreboot/+/38956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c46477352b8151f3b0fb0616f909531a0a15c34 Gerrit-Change-Number: 38956 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: Documentation: Use inline code block for kernel parameter
by Evgeny Zinoviev (Code Review) 19 Feb '20

19 Feb '20

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38955 ) Change subject: Documentation: Use inline code block for kernel parameter ...................................................................... Documentation: Use inline code block for kernel parameter Change-Id: I41649d4d0ee0abf9335f6cb3d7b19888c0c62382 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M Documentation/flash_tutorial/int_flashrom.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/38955/1 diff --git a/Documentation/flash_tutorial/int_flashrom.md b/Documentation/flash_tutorial/int_flashrom.md index 28b534b..982aca2 100644 --- a/Documentation/flash_tutorial/int_flashrom.md +++ b/Documentation/flash_tutorial/int_flashrom.md @@ -5,7 +5,7 @@ ## Using flashrom This method does only work on Linux, if it isn't locked down. -You may also need to boot with 'iomem=relaxed' in the kernel command +You may also need to boot with `iomem=relaxed` in the kernel command line if CONFIG_IO_STRICT_DEVMEM is set. -- To view, visit https://review.coreboot.org/c/coreboot/+/38955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41649d4d0ee0abf9335f6cb3d7b19888c0c62382 Gerrit-Change-Number: 38955 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: soc/intel/p2sb: Drop unnecessary P2SB_GET_DEV
by Nico Huber (Code Review) 19 Feb '20

19 Feb '20

Hello Subrata Banik, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38946 to review the following change. Change subject: soc/intel/p2sb: Drop unnecessary P2SB_GET_DEV ...................................................................... soc/intel/p2sb: Drop unnecessary P2SB_GET_DEV PCH_DEV_P2SB already covers both __SIMPLE_DEVICE__ cases. The values are only used for PCI-config access functions, which also check for NULL when necessary. The PCI_DEV_INVALID case can't occur by definition, and if we wanted to check, we could do so at compile time using _Static_assert(). Change-Id: I400fc20133809aaa0fd0519531a62ec9b8812ef1 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/common/block/p2sb/p2sb.c 1 file changed, 12 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/38946/1 diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 34b6e06..c968409 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -29,40 +29,14 @@ #define HIDE_BIT (1 << 0) -#if defined(__SIMPLE_DEVICE__) -static pci_devfn_t p2sb_get_device(void) -{ - int devfn = PCH_DEVFN_P2SB; - pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); - - if (dev == PCI_DEV_INVALID) - die_with_post_code(POST_HW_INIT_FAILURE, - "PCH_DEV_P2SB not found!\n"); - - return dev; -} -#else -static struct device *p2sb_get_device(void) -{ - struct device *dev = PCH_DEV_P2SB; - if (!dev) - die_with_post_code(POST_HW_INIT_FAILURE, - "PCH_DEV_P2SB not found!\n"); - - return dev; -} -#endif - -#define P2SB_GET_DEV p2sb_get_device() - void p2sb_enable_bar(void) { /* Enable PCR Base address in PCH */ - pci_write_config32(P2SB_GET_DEV, PCI_BASE_ADDRESS_0, P2SB_BAR); - pci_write_config32(P2SB_GET_DEV, PCI_BASE_ADDRESS_1, 0); + pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, P2SB_BAR); + pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0); /* Enable P2SB MSE */ - pci_write_config8(P2SB_GET_DEV, PCI_COMMAND, + pci_write_config8(PCH_DEV_P2SB, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } @@ -79,7 +53,7 @@ * the High Performance Timer memory address range * selected by bits 1:0 */ - pci_write_config8(P2SB_GET_DEV, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT); + pci_write_config8(PCH_DEV_P2SB, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT); } static void p2sb_set_hide_bit(int hide) @@ -88,18 +62,18 @@ const uint8_t mask = HIDE_BIT; uint8_t val; - val = pci_read_config8(P2SB_GET_DEV, reg); + val = pci_read_config8(PCH_DEV_P2SB, reg); val &= ~mask; if (hide) val |= mask; - pci_write_config8(P2SB_GET_DEV, reg, val); + pci_write_config8(PCH_DEV_P2SB, reg, val); } void p2sb_unhide(void) { p2sb_set_hide_bit(0); - if (pci_read_config16(P2SB_GET_DEV, PCI_VENDOR_ID) != + if (pci_read_config16(PCH_DEV_P2SB, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL) die_with_post_code(POST_HW_INIT_FAILURE, "Unable to unhide PCH_DEV_P2SB device !\n"); @@ -109,7 +83,7 @@ { p2sb_set_hide_bit(1); - if (pci_read_config16(P2SB_GET_DEV, PCI_VENDOR_ID) != + if (pci_read_config16(PCH_DEV_P2SB, PCI_VENDOR_ID) != 0xFFFF) die_with_post_code(POST_HW_INIT_FAILURE, "Unable to hide PCH_DEV_P2SB device !\n"); @@ -119,8 +93,8 @@ { uint32_t reg32; - reg32 = pci_read_config32(P2SB_GET_DEV, PCH_P2SB_EPMASK(epmask_id)); - pci_write_config32(P2SB_GET_DEV, PCH_P2SB_EPMASK(epmask_id), + reg32 = pci_read_config32(PCH_DEV_P2SB, PCH_P2SB_EPMASK(epmask_id)); + pci_write_config32(PCH_DEV_P2SB, PCH_P2SB_EPMASK(epmask_id), reg32 | mask); } @@ -129,8 +103,8 @@ uint8_t reg8; /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */ - reg8 = pci_read_config8(P2SB_GET_DEV, PCH_P2SB_E0 + 2); - pci_write_config8(P2SB_GET_DEV, PCH_P2SB_E0 + 2, + reg8 = pci_read_config8(PCH_DEV_P2SB, PCH_P2SB_E0 + 2); + pci_write_config8(PCH_DEV_P2SB, PCH_P2SB_E0 + 2, reg8 | P2SB_E0_MASKLOCK); } -- To view, visit https://review.coreboot.org/c/coreboot/+/38946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I400fc20133809aaa0fd0519531a62ec9b8812ef1 Gerrit-Change-Number: 38946 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[4.11_branch]: Makefile.inc: Adapt $(spc) definition
by Patrick Georgi (Code Review) 19 Feb '20

19 Feb '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38958 ) Change subject: Makefile.inc: Adapt $(spc) definition ...................................................................... Makefile.inc: Adapt $(spc) definition GNU Make 4.3 is more picky about the $(spc) definition. It seems, the variable ends up empty. The old definition worked for nearly 8 years, RIP. Tested with GNU Make 4.2.1 and 4.3. Change-Id: I7981e0066b550251ae4a98d7b50e83049fc5586a Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38790 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> (cherry picked from commit 0f6f70c3942c152c512b1aa51b6f6079a05e003b) Reviewed-on: https://review.coreboot.org/c/coreboot/+/38958 --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/Makefile.inc b/Makefile.inc index 66144cd..f26fead 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -159,7 +159,7 @@ ####################################################################### # Helper functions for ramstage postprocess spc := -spc += +spc := $(spc) $(spc) comma := , # Returns all files and dirs below `dir` (recursively). -- To view, visit https://review.coreboot.org/c/coreboot/+/38958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I7981e0066b550251ae4a98d7b50e83049fc5586a Gerrit-Change-Number: 38958 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: vboot: remove use of NEED_VB20_INTERNALS switch
by Joel Kitching (Code Review) 19 Feb '20

19 Feb '20

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38887 ) Change subject: vboot: remove use of NEED_VB20_INTERNALS switch ...................................................................... vboot: remove use of NEED_VB20_INTERNALS switch The NEED_VB20_INTERNALS switch is being deprecated. Use the header file vb2_internals_please_do_not_use.h instead. BUG=b:124141368, chromium:957880 TEST=make clean && make test-abuild BRANCH=none Change-Id: Ie35644876178b806fab4f0ce8089a556227312db Signed-off-by: Joel Kitching <kitching(a)google.com> Cq-Depend: chromium:2055600 --- M src/vendorcode/eltan/security/verified_boot/vboot_check.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/38887/1 diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index 2edd8f9..9d99e02 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -14,13 +14,12 @@ * GNU General Public License for more details. */ -#define NEED_VB20_INTERNALS - #include <boot_device.h> #include <bootmem.h> #include <cbfs.h> #include <vboot_check.h> #include <vboot_common.h> +#include <vb2_internals_please_do_not_use.h> #define RSA_PUBLICKEY_FILE_NAME "vboot_public_key.bin" -- To view, visit https://review.coreboot.org/c/coreboot/+/38887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie35644876178b806fab4f0ce8089a556227312db Gerrit-Change-Number: 38887 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: Update vboot submodule to upstream master
by Joel Kitching (Code Review) 19 Feb '20

19 Feb '20

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38953 ) Change subject: Update vboot submodule to upstream master ...................................................................... Update vboot submodule to upstream master Updating from commit id 0e97e25e: 2020-01-28 02:32:08 +0000 - (2lib: Fix struct vb2_hash the way it was meant to be) to commit id 8b9732f5: 2020-02-18 05:55:01 +0000 - (vboot: do not call vb2_commit_data at end of VBSLK) This brings in 36 new commits. Change-Id: Icb0ab2c82c3264185171a32357944949afd2edce Signed-off-by: Joel Kitching <kitching(a)google.com> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/38953/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index 0e97e25..8b9732f 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 0e97e25e85f0499e23b09a31a2c7116759f191d5 +Subproject commit 8b9732f5fcccc1c568e821f144b7ccd94708b45d -- To view, visit https://review.coreboot.org/c/coreboot/+/38953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb0ab2c82c3264185171a32357944949afd2edce Gerrit-Change-Number: 38953 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

3 4

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2020