coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/apollolake: Display platform information
by Usha P (Code Review) 19 Feb '20

19 Feb '20

Hello Werner Zeh, Patrick Rudolph, Subrata Banik, Aamir Bohra, Rizwan Qureshi, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38824 to look at the new patch set (#6). Change subject: soc/intel/apollolake: Display platform information ...................................................................... soc/intel/apollolake: Display platform information This patch includes the change required to display Apollo Lake platform information which reports CPU, MCH, PCH and IGD information in romstage. BUG=None TEST= 1. Boot to OS on Bobba board. 2. Verified below info from CPU Console log in romstage CPU: Intel(R) Celeron(R) N4000 CPU @ 1.10GHz CPU: ID 706a1, Geminilake B0, ucode: 00000031 CPU: AES supported, TXT NOT supported, VT supported MCH: device id 31f0 (rev 03) is Geminilake PCH: device id 3197 (rev 03) is Geminilake IGD: device id 3185 (rev 03) is Geminilake EU12 Change-Id: Id4edfeae7faee9f5f80698cf34b31fdcb066a813 Signed-off-by: Usha P <usha.p(a)intel.com> --- M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/include/soc/romstage.h A src/soc/intel/apollolake/report_platform.c M src/soc/intel/apollolake/romstage.c 4 files changed, 176 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38824/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/38824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4edfeae7faee9f5f80698cf34b31fdcb066a813 Gerrit-Change-Number: 38824 Gerrit-PatchSet: 6 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/apollolake: Display platform information
by Usha P (Code Review) 19 Feb '20

19 Feb '20

Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38824 ) Change subject: soc/intel/apollolake: Display platform information ...................................................................... Patch Set 5: (7 comments) https://review.coreboot.org/c/coreboot/+/38824/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38824/4//COMMIT_MSG@7 PS4, Line 7: apollolake > Not needed, as it’s in the prefix. Done https://review.coreboot.org/c/coreboot/+/38824/4//COMMIT_MSG@9 PS4, Line 9: apollolake > Apollo Lake Done https://review.coreboot.org/c/coreboot/+/38824/4//COMMIT_MSG@19 PS4, Line 19: Geminilake > It’s the successor of Apollo Lake. Yes it is. https://review.coreboot.org/c/coreboot/+/38824/4/src/soc/intel/apollolake/r… File src/soc/intel/apollolake/report_platform.c: https://review.coreboot.org/c/coreboot/+/38824/4/src/soc/intel/apollolake/r… PS4, Line 79: u32 i > The counting variable should be just `unsigned int i`. Done https://review.coreboot.org/c/coreboot/+/38824/4/src/soc/intel/apollolake/r… PS4, Line 81: int vt, txt, aes; > Why not boolean type? Also, rename to `vt_supported`, and so on. Done https://review.coreboot.org/c/coreboot/+/38824/4/src/soc/intel/apollolake/r… PS4, Line 102: BIOS_DEBUG > I’d make that BIOS_INFO. […] Done https://review.coreboot.org/c/coreboot/+/38824/4/src/soc/intel/apollolake/r… PS4, Line 117: int > unsigned int Done -- To view, visit https://review.coreboot.org/c/coreboot/+/38824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4edfeae7faee9f5f80698cf34b31fdcb066a813 Gerrit-Change-Number: 38824 Gerrit-PatchSet: 5 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 19 Feb 2020 06:39:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/apollolake: Display platform information
by Usha P (Code Review) 19 Feb '20

19 Feb '20

Hello Werner Zeh, Patrick Rudolph, Subrata Banik, Aamir Bohra, Rizwan Qureshi, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38824 to look at the new patch set (#5). Change subject: soc/intel/apollolake: Display platform information ...................................................................... soc/intel/apollolake: Display platform information This patch includes the change required to display Apollo Lake platform information which reports CPU, MCH, PCH and IGD information in romstage. BUG=None TEST= 1. Boot to OS on Bobba board. 2. Verified below info from CPU Console log in romstage CPU: Intel(R) Celeron(R) N4000 CPU @ 1.10GHz CPU: ID 706a1, Geminilake B0, ucode: 00000031 CPU: AES supported, TXT NOT supported, VT supported MCH: device id 31f0 (rev 03) is Geminilake PCH: device id 3197 (rev 03) is Geminilake IGD: device id 3185 (rev 03) is Geminilake EU12 Change-Id: Id4edfeae7faee9f5f80698cf34b31fdcb066a813 Signed-off-by: Usha P <usha.p(a)intel.com> --- M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/include/soc/romstage.h A src/soc/intel/apollolake/report_platform.c M src/soc/intel/apollolake/romstage.c 4 files changed, 177 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38824/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/38824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4edfeae7faee9f5f80698cf34b31fdcb066a813 Gerrit-Change-Number: 38824 Gerrit-PatchSet: 5 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboard: Add OCP Tioga Pass board
by build bot (Jenkins) (Code Review) 19 Feb '20

19 Feb '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38840 ) Change subject: mainboard: Add OCP Tioga Pass board ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/38840/10/src/mainboard/ocp/tiogapa… File src/mainboard/ocp/tiogapass/bootblock.c: https://review.coreboot.org/c/coreboot/+/38840/10/src/mainboard/ocp/tiogapa… PS10, Line 46: if (CONFIG(BOOTBLOCK_CONSOLE)) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/38840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6c5da3c3856b035af5f2b3b80f0894f6fb81696 Gerrit-Change-Number: 38840 Gerrit-PatchSet: 10 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 19 Feb 2020 06:14:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard: Add OCP Tioga Pass board
by Andrey Petrov (Code Review) 19 Feb '20

19 Feb '20

Hello Jonathan Zhang, David Hendricks, Stefan Reinauer, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38840 to look at the new patch set (#10). Change subject: mainboard: Add OCP Tioga Pass board ...................................................................... mainboard: Add OCP Tioga Pass board This adds mainboard skeleton file set. Change-Id: Ic6c5da3c3856b035af5f2b3b80f0894f6fb81696 Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> --- A src/mainboard/ocp/Kconfig A src/mainboard/ocp/Kconfig.name A src/mainboard/ocp/tiogapass/Kconfig A src/mainboard/ocp/tiogapass/Kconfig.name A src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/acpi_tables.c A src/mainboard/ocp/tiogapass/board.fmd A src/mainboard/ocp/tiogapass/board_info.txt A src/mainboard/ocp/tiogapass/bootblock.c A src/mainboard/ocp/tiogapass/devicetree.cb A src/mainboard/ocp/tiogapass/dsdt.asl A src/mainboard/ocp/tiogapass/romstage.c 12 files changed, 210 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/38840/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/38840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6c5da3c3856b035af5f2b3b80f0894f6fb81696 Gerrit-Change-Number: 38840 Gerrit-PatchSet: 10 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu: Add initial xeonsp support boilerplate
by build bot (Jenkins) (Code Review) 19 Feb '20

19 Feb '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38838 ) Change subject: cpu: Add initial xeonsp support boilerplate ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/c/coreboot/+/38838/8/src/cpu/intel/xeonsp/bootb… File src/cpu/intel/xeonsp/bootblock.c: https://review.coreboot.org/c/coreboot/+/38838/8/src/cpu/intel/xeonsp/bootb… PS8, Line 52: if (CONFIG(BOOTBLOCK_CONSOLE)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/c/coreboot/+/38838/8/src/cpu/intel/xeonsp/postc… File src/cpu/intel/xeonsp/postcar.c: https://review.coreboot.org/c/coreboot/+/38838/8/src/cpu/intel/xeonsp/postc… PS8, Line 20: void fill_postcar_frame(struct postcar_frame *pcf) { open brace '{' following function definitions go on the next line -- To view, visit https://review.coreboot.org/c/coreboot/+/38838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24346b8a5c30342419db23b5f1adf27d4d0ebc5f Gerrit-Change-Number: 38838 Gerrit-PatchSet: 8 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 19 Feb 2020 06:00:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard: Add OCP Tioga Pass board
by build bot (Jenkins) (Code Review) 19 Feb '20

19 Feb '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38840 ) Change subject: mainboard: Add OCP Tioga Pass board ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/38840/9/src/mainboard/ocp/tiogapas… File src/mainboard/ocp/tiogapass/bootblock.c: https://review.coreboot.org/c/coreboot/+/38840/9/src/mainboard/ocp/tiogapas… PS9, Line 46: if (CONFIG(BOOTBLOCK_CONSOLE)) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/38840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6c5da3c3856b035af5f2b3b80f0894f6fb81696 Gerrit-Change-Number: 38840 Gerrit-PatchSet: 9 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 19 Feb 2020 06:00:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu: Add initial xeonsp support boilerplate
by Andrey Petrov (Code Review) 19 Feb '20

19 Feb '20

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38838 to look at the new patch set (#8). Change subject: cpu: Add initial xeonsp support boilerplate ...................................................................... cpu: Add initial xeonsp support boilerplate This adds boilerplate code that is common across several Xeon SP processors. The idea is that common xeonsp code should go into cpu/intel/xeonsp/ and CPU-specific files and overrides should go into a subfolder. Change-Id: I24346b8a5c30342419db23b5f1adf27d4d0ebc5f Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> --- M src/cpu/intel/Kconfig M src/cpu/intel/Makefile.inc A src/cpu/intel/xeonsp/Kconfig A src/cpu/intel/xeonsp/Makefile.inc A src/cpu/intel/xeonsp/bootblock.c A src/cpu/intel/xeonsp/include/soc/cpu.h A src/cpu/intel/xeonsp/include/soc/gpe.h A src/cpu/intel/xeonsp/include/soc/gpio.h A src/cpu/intel/xeonsp/include/soc/iomap.h A src/cpu/intel/xeonsp/include/soc/pm.h A src/cpu/intel/xeonsp/include/soc/pmc.h A src/cpu/intel/xeonsp/include/soc/smbus.h A src/cpu/intel/xeonsp/include/soc/systemagent.h A src/cpu/intel/xeonsp/lpc.c A src/cpu/intel/xeonsp/model_xeonsp_init.c A src/cpu/intel/xeonsp/postcar.c A src/cpu/intel/xeonsp/ramstage.c A src/cpu/intel/xeonsp/romstage.c 18 files changed, 480 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/38838/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/38838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24346b8a5c30342419db23b5f1adf27d4d0ebc5f Gerrit-Change-Number: 38838 Gerrit-PatchSet: 8 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu: Add initial xeonsp support boilerplate
by build bot (Jenkins) (Code Review) 19 Feb '20

19 Feb '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38838 ) Change subject: cpu: Add initial xeonsp support boilerplate ...................................................................... Patch Set 7: (3 comments) https://review.coreboot.org/c/coreboot/+/38838/7/src/cpu/intel/xeonsp/bootb… File src/cpu/intel/xeonsp/bootblock.c: https://review.coreboot.org/c/coreboot/+/38838/7/src/cpu/intel/xeonsp/bootb… PS7, Line 52: if (CONFIG(BOOTBLOCK_CONSOLE)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/c/coreboot/+/38838/7/src/cpu/intel/xeonsp/inclu… File src/cpu/intel/xeonsp/include/soc/gpio.h: https://review.coreboot.org/c/coreboot/+/38838/7/src/cpu/intel/xeonsp/inclu… PS7, Line 17: #define NUM_GPI_STATUS_REGS 0 adding a line without newline at end of file https://review.coreboot.org/c/coreboot/+/38838/7/src/cpu/intel/xeonsp/postc… File src/cpu/intel/xeonsp/postcar.c: https://review.coreboot.org/c/coreboot/+/38838/7/src/cpu/intel/xeonsp/postc… PS7, Line 20: void fill_postcar_frame(struct postcar_frame *pcf) { open brace '{' following function definitions go on the next line -- To view, visit https://review.coreboot.org/c/coreboot/+/38838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24346b8a5c30342419db23b5f1adf27d4d0ebc5f Gerrit-Change-Number: 38838 Gerrit-PatchSet: 7 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 19 Feb 2020 05:57:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard: Add OCP Tioga Pass board
by build bot (Jenkins) (Code Review) 19 Feb '20

19 Feb '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38840 ) Change subject: mainboard: Add OCP Tioga Pass board ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/38840/8/src/mainboard/ocp/tiogapas… File src/mainboard/ocp/tiogapass/bootblock.c: https://review.coreboot.org/c/coreboot/+/38840/8/src/mainboard/ocp/tiogapas… PS8, Line 46: if (CONFIG(BOOTBLOCK_CONSOLE)) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/38840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6c5da3c3856b035af5f2b3b80f0894f6fb81696 Gerrit-Change-Number: 38840 Gerrit-PatchSet: 8 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 19 Feb 2020 05:57:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2020