coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/hatch: set wifi sar for Akemi
by Peichao Li (Code Review) 19 Feb '20

19 Feb '20

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38937 ) Change subject: mb/google/hatch: set wifi sar for Akemi ...................................................................... mb/google/hatch: set wifi sar for Akemi Enable wifi sar feature and set wifi sar name for Akemi BUG=b:146260789 TEST=emerge-hatch coreboot chromeos-bootimage check wifi_sar-akemi.hex in /cbfs-rw-raw/akemi Signed-off-by: Peichao Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: I549e00c800985ecf8702220b276885385d928cd1 --- M src/mainboard/google/hatch/variants/akemi/variant.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/38937/1 diff --git a/src/mainboard/google/hatch/variants/akemi/variant.c b/src/mainboard/google/hatch/variants/akemi/variant.c index 8440b5c..e62f3a7 100644 --- a/src/mainboard/google/hatch/variants/akemi/variant.c +++ b/src/mainboard/google/hatch/variants/akemi/variant.c @@ -17,6 +17,7 @@ #include <chip.h> #include <soc/pci_devs.h> #include <ec/google/chromeec/ec.h> +#include <sar.h> void variant_devtree_update(void) { @@ -48,3 +49,11 @@ cfg->satapwroptimize = 0; } } + +const char *get_wifi_sar_cbfs_filename(void) +{ + const char *filename = NULL; + filename = "wifi_sar-akemi.hex"; + + return filename; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/38937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I549e00c800985ecf8702220b276885385d928cd1 Gerrit-Change-Number: 38937 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard: Add OCP Tioga Pass board
by build bot (Jenkins) (Code Review) 19 Feb '20

19 Feb '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38840 ) Change subject: mainboard: Add OCP Tioga Pass board ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/38840/5/src/mainboard/ocp/tiogapas… File src/mainboard/ocp/tiogapass/bootblock.c: https://review.coreboot.org/c/coreboot/+/38840/5/src/mainboard/ocp/tiogapas… PS5, Line 29: if (CONFIG(BOOTBLOCK_CONSOLE)) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/38840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6c5da3c3856b035af5f2b3b80f0894f6fb81696 Gerrit-Change-Number: 38840 Gerrit-PatchSet: 5 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 19 Feb 2020 00:53:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu: Add initial xeonsp support boilerplate
by build bot (Jenkins) (Code Review) 19 Feb '20

19 Feb '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38838 ) Change subject: cpu: Add initial xeonsp support boilerplate ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/c/coreboot/+/38838/4/src/cpu/intel/xeonsp/inclu… File src/cpu/intel/xeonsp/include/soc/gpio.h: https://review.coreboot.org/c/coreboot/+/38838/4/src/cpu/intel/xeonsp/inclu… PS4, Line 17: #define NUM_GPI_STATUS_REGS 0 adding a line without newline at end of file https://review.coreboot.org/c/coreboot/+/38838/4/src/cpu/intel/xeonsp/postc… File src/cpu/intel/xeonsp/postcar.c: https://review.coreboot.org/c/coreboot/+/38838/4/src/cpu/intel/xeonsp/postc… PS4, Line 20: void fill_postcar_frame(struct postcar_frame *pcf) { open brace '{' following function definitions go on the next line -- To view, visit https://review.coreboot.org/c/coreboot/+/38838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24346b8a5c30342419db23b5f1adf27d4d0ebc5f Gerrit-Change-Number: 38838 Gerrit-PatchSet: 4 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 19 Feb 2020 00:53:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard: Add OCP Tioga Pass board
by Andrey Petrov (Code Review) 19 Feb '20

19 Feb '20

Hello Jonathan Zhang, David Hendricks, Stefan Reinauer, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38840 to look at the new patch set (#5). Change subject: mainboard: Add OCP Tioga Pass board ...................................................................... mainboard: Add OCP Tioga Pass board This adds mainboard skeleton file set. Change-Id: Ic6c5da3c3856b035af5f2b3b80f0894f6fb81696 Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> --- A src/mainboard/ocp/Kconfig A src/mainboard/ocp/Kconfig.name A src/mainboard/ocp/tiogapass/Kconfig A src/mainboard/ocp/tiogapass/Kconfig.name A src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/acpi_tables.c A src/mainboard/ocp/tiogapass/board.fmd A src/mainboard/ocp/tiogapass/board_info.txt A src/mainboard/ocp/tiogapass/bootblock.c A src/mainboard/ocp/tiogapass/devicetree.cb A src/mainboard/ocp/tiogapass/dsdt.asl A src/mainboard/ocp/tiogapass/romstage.c 12 files changed, 194 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/38840/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/38840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6c5da3c3856b035af5f2b3b80f0894f6fb81696 Gerrit-Change-Number: 38840 Gerrit-PatchSet: 5 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: xeonsp: Initial Skylake-SP support
by Andrey Petrov (Code Review) 19 Feb '20

19 Feb '20

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38839 to look at the new patch set (#4). Change subject: xeonsp: Initial Skylake-SP support ...................................................................... xeonsp: Initial Skylake-SP support This adds very basic Skylake-SP support. TEST=bootblock works and prints on serial on OCP TiogaPass Change-Id: Iaccd8e0034abd5954e3169bf7e585b5f59fe1ead Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> --- M src/cpu/intel/xeonsp/Makefile.inc A src/cpu/intel/xeonsp/cpu/skylake-sp/Kconfig A src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc A src/cpu/intel/xeonsp/cpu/skylake-sp/chip.h A src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/pci_devs.h A src/cpu/intel/xeonsp/cpu/skylake-sp/romstage.c 6 files changed, 113 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/38839/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/38839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaccd8e0034abd5954e3169bf7e585b5f59fe1ead Gerrit-Change-Number: 38839 Gerrit-PatchSet: 4 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu: Add initial xeonsp support boilerplate
by Andrey Petrov (Code Review) 19 Feb '20

19 Feb '20

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38838 to look at the new patch set (#4). Change subject: cpu: Add initial xeonsp support boilerplate ...................................................................... cpu: Add initial xeonsp support boilerplate This adds boilerplate code that is common across several Xeon SP processors. The idea is that common xeonsp code should go into cpu/intel/xeonsp/ and CPU-specific files and overrides should go into a subfolder. Change-Id: I24346b8a5c30342419db23b5f1adf27d4d0ebc5f Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> --- M src/cpu/intel/Kconfig M src/cpu/intel/Makefile.inc A src/cpu/intel/xeonsp/Kconfig A src/cpu/intel/xeonsp/Makefile.inc A src/cpu/intel/xeonsp/bootblock.c A src/cpu/intel/xeonsp/include/soc/cpu.h A src/cpu/intel/xeonsp/include/soc/gpe.h A src/cpu/intel/xeonsp/include/soc/gpio.h A src/cpu/intel/xeonsp/include/soc/iomap.h A src/cpu/intel/xeonsp/include/soc/pm.h A src/cpu/intel/xeonsp/include/soc/pmc.h A src/cpu/intel/xeonsp/include/soc/smbus.h A src/cpu/intel/xeonsp/include/soc/systemagent.h A src/cpu/intel/xeonsp/lpc.c A src/cpu/intel/xeonsp/model_xeonsp_init.c A src/cpu/intel/xeonsp/postcar.c A src/cpu/intel/xeonsp/ramstage.c A src/cpu/intel/xeonsp/romstage.c 18 files changed, 474 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/38838/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/38838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24346b8a5c30342419db23b5f1adf27d4d0ebc5f Gerrit-Change-Number: 38838 Gerrit-PatchSet: 4 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: HACK trogdor: optimize coreboot.rom for T32 flash script HACK
by mturney mturney (Code Review) 18 Feb '20

18 Feb '20

Hello Aaron Durbin, Ravi kumar, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36278 to look at the new patch set (#38). Change subject: HACK trogdor: optimize coreboot.rom for T32 flash script HACK ...................................................................... HACK trogdor: optimize coreboot.rom for T32 flash script HACK Change-Id: I5293ac9365bf4ac74bc475e70a02062f5371f9b8 Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M src/security/vboot/Makefile.inc A util/qualcomm/optimize_coreboot 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/36278/38 -- To view, visit https://review.coreboot.org/c/coreboot/+/36278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5293ac9365bf4ac74bc475e70a02062f5371f9b8 Gerrit-Change-Number: 36278 Gerrit-PatchSet: 38 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: HACK trogdor: SoC makefile BLOB support HACK
by mturney mturney (Code Review) 18 Feb '20

18 Feb '20

Hello ashk(a)codeaurora.org, Ravi kumar, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35508 to look at the new patch set (#49). Change subject: HACK trogdor: SoC makefile BLOB support HACK ...................................................................... HACK trogdor: SoC makefile BLOB support HACK Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Signed-off-by: Ashwin Kumar <ashk(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Makefile.inc 1 file changed, 119 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/35508/49 -- To view, visit https://review.coreboot.org/c/coreboot/+/35508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Gerrit-Change-Number: 35508 Gerrit-PatchSet: 49 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/glkrvp/chromeos.fmd: Correct indentation
by Angel Pons (Code Review) 18 Feb '20

18 Feb '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38663 ) Change subject: mb/intel/glkrvp/chromeos.fmd: Correct indentation ...................................................................... mb/intel/glkrvp/chromeos.fmd: Correct indentation Tested with BUILD_TIMELESS, no changes. Change-Id: Iaf615e95a30e9c02ad49351a3c0db253ad713ad4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/glkrvp/chromeos.fmd 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/38663/1 diff --git a/src/mainboard/intel/glkrvp/chromeos.fmd b/src/mainboard/intel/glkrvp/chromeos.fmd index 5d4ba46..8f3c63a 100644 --- a/src/mainboard/intel/glkrvp/chromeos.fmd +++ b/src/mainboard/intel/glkrvp/chromeos.fmd @@ -13,11 +13,11 @@ } } MISC_RW@0x400000 0x4a000 { - UNIFIED_MRC_CACHE@0x0 0x31000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x20000 - RW_VAR_MRC_CACHE@0x30000 0x1000 - } + UNIFIED_MRC_CACHE@0x0 0x31000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x20000 + RW_VAR_MRC_CACHE@0x30000 0x1000 + } RW_ELOG(PRESERVE)@0x31000 0x4000 RW_SHARED@0x35000 0x4000 { SHARED_DATA@0x0 0x2000 -- To view, visit https://review.coreboot.org/c/coreboot/+/38663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf615e95a30e9c02ad49351a3c0db253ad713ad4 Gerrit-Change-Number: 38663 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu: Allow to configure microcode at pre-defined address
by 9elements QA (Code Review) 18 Feb '20

18 Feb '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38640 ) Change subject: cpu: Allow to configure microcode at pre-defined address ...................................................................... Patch Set 9: Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/697 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/696 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/695 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/38640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c02601a7ac64078e556e2032baeccaf27f77da2 Gerrit-Change-Number: 38640 Gerrit-PatchSet: 9 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 18 Feb 2020 20:21:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2020