coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: cpu: Add initial xeonsp support broilerplate
by Andrey Petrov (Code Review) 18 Feb '20

18 Feb '20

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38838 ) Change subject: cpu: Add initial xeonsp support broilerplate ...................................................................... Patch Set 2: (4 comments) https://review.coreboot.org/c/coreboot/+/38838/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38838/2//COMMIT_MSG@7 PS2, Line 7: broilerplate > Very likely. Done https://review.coreboot.org/c/coreboot/+/38838/2//COMMIT_MSG@9 PS2, Line 9: broilerplate > same here Done https://review.coreboot.org/c/coreboot/+/38838/2//COMMIT_MSG@10 PS2, Line 10: xeonsp > Xeon SP […] I like xeon_scalable more than xeonsp, thanks. I will not change the name just yet -- lets see if we will have other variants as well. The idea behind this patch is to add generic platform code that would be useful by multiple Xeon, uh, "platforms". The wrinkle with it that you can have a mainboard that can support skylake-sp and cascadelake-sp or icelake-something. Several of CPUs are actually pin-compatible. https://review.coreboot.org/c/coreboot/+/38838/2//COMMIT_MSG@14 PS2, Line 14: Change-Id: I24346b8a5c30342419db23b5f1adf27d4d0ebc5f > Missing Signed-off-by line. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/38838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24346b8a5c30342419db23b5f1adf27d4d0ebc5f Gerrit-Change-Number: 38838 Gerrit-PatchSet: 2 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 18 Feb 2020 19:16:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu: Allow to configure microcode at pre-defined address
by Andrey Petrov (Code Review) 18 Feb '20

18 Feb '20

Hello Jonathan Zhang, David Hendricks, Philipp Deppenwiese, Lance Zhao, build bot (Jenkins), Lijian Zhao, Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38640 to look at the new patch set (#8). Change subject: cpu: Allow to configure microcode at pre-defined address ...................................................................... cpu: Allow to configure microcode at pre-defined address FSP-T takes microcode pointer and location parameters, and FSP-T is invoked before CAR is set-up and before memory is trained. So it is not possible to modify supplied microcode pointer in runtime. Because of that we have to hardcode the pointer in bootblock. Also, current FSP-T on Xeons require microcode (it is not optional). Reasons for that are currently unclear and are being investigated. However for the present time we need to be able to add microcode at a certain offset so FSP-T can be used. TEST=test on OCP TiogaPass board, as well as out-of-tree CPU/board Change-Id: I6c02601a7ac64078e556e2032baeccaf27f77da2 Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> --- M src/cpu/Makefile.inc 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/38640/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/38640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c02601a7ac64078e556e2032baeccaf27f77da2 Gerrit-Change-Number: 38640 Gerrit-PatchSet: 8 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu: Add microcode at pre-defined address
by Andrey Petrov (Code Review) 18 Feb '20

18 Feb '20

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38640 ) Change subject: cpu: Add microcode at pre-defined address ...................................................................... Patch Set 7: (2 comments) https://review.coreboot.org/c/coreboot/+/38640/7//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38640/7//COMMIT_MSG@7 PS7, Line 7: cpu: Add microcode at pre-defined address > cpu: Allow to configure microcode at pre-defined address Done https://review.coreboot.org/c/coreboot/+/38640/7//COMMIT_MSG@10 PS7, Line 10: setup > set up Done -- To view, visit https://review.coreboot.org/c/coreboot/+/38640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c02601a7ac64078e556e2032baeccaf27f77da2 Gerrit-Change-Number: 38640 Gerrit-PatchSet: 7 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 18 Feb 2020 18:51:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu: Add microcode at pre-defined address
by Andrey Petrov (Code Review) 18 Feb '20

18 Feb '20

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38640 ) Change subject: cpu: Add microcode at pre-defined address ...................................................................... Patch Set 7: (2 comments) https://review.coreboot.org/c/coreboot/+/38640/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38640/6//COMMIT_MSG@7 PS6, Line 7: c > I'm aware that it's not possible to give the microcode location to FSP-T during runtime. […] ah, now I understand what you meant. Sorry for being so tone-deaf. I believe it may be a good approach (having assembly code load ucode). I do not think it is really necessary to load ucode specifically with assembly before CAR is set up. I'd guess the only reason why would want to do it is that microcode fix is required for CAR to function properly. Anyway, for now we have to use FSP-T but like I said we are planning on changing that. Arthur I am marking this comment as 'resolved', please let me know if you have objections. https://review.coreboot.org/c/coreboot/+/38640/6//COMMIT_MSG@13 PS6, Line 13: : Also, on current version of FSP-T on Xeons microcode is not optional. > I think we all agree we need less blobs not more. […] marking this as "resolved" -- To view, visit https://review.coreboot.org/c/coreboot/+/38640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c02601a7ac64078e556e2032baeccaf27f77da2 Gerrit-Change-Number: 38640 Gerrit-PatchSet: 7 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 18 Feb 2020 18:49:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Andrey Petrov <anpetrov(a)fb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/amdfwtool: Improve comment's grammar
by Patrick Georgi (Code Review) 18 Feb '20

18 Feb '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38944 ) Change subject: util/amdfwtool: Improve comment's grammar ...................................................................... util/amdfwtool: Improve comment's grammar Reported by: Angel Pons Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Change-Id: I2daa57c1982346e48dbd91a94864baf2f11c2129 --- M util/amdfwtool/amdfwtool.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/38944/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 522d332..379caaa 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1439,7 +1439,7 @@ integrate_firmwares(&ctx, amd_romsig, amd_fw_table); - ctx.current = ALIGN(ctx.current, 0x10000U); /* TODO: is necessary? */ + ctx.current = ALIGN(ctx.current, 0x10000U); /* TODO: is it necessary? */ if (multi) { /* Do 2nd PSP directory followed by 1st */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2daa57c1982346e48dbd91a94864baf2f11c2129 Gerrit-Change-Number: 38944 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/facebook/monolith: Use serial number and UUID from VPD
by Wim Vervoorn (Code Review) 18 Feb '20

18 Feb '20

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38753 ) Change subject: mb/facebook/monolith: Use serial number and UUID from VPD ...................................................................... mb/facebook/monolith: Use serial number and UUID from VPD The serial number and UUID returned by DMI are retrieved from VPD. The solution supports a 16 character "serial_number" and a 36 character "UUID" string. BUG=N/A TEST=tested on monolith Change-Id: I0b6ce769cfa81a1e248a35f6149b7d1bbcf1f836 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/monolith/ramstage.c 1 file changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/38753/1 diff --git a/src/mainboard/facebook/monolith/ramstage.c b/src/mainboard/facebook/monolith/ramstage.c index bed1049..3e46b85 100644 --- a/src/mainboard/facebook/monolith/ramstage.c +++ b/src/mainboard/facebook/monolith/ramstage.c @@ -14,7 +14,14 @@ * GNU General Public License for more details. */ +#include <stdint.h> +#include <console/console.h> +#include <drivers/vpd/vpd.h> +#include <lib.h> +#include <smbios.h> #include <soc/ramstage.h> +#include <uuid.h> + #include "gpio.h" void mainboard_silicon_init_params(FSP_SIL_UPD *params) @@ -24,3 +31,31 @@ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); params->CdClock = 3; } + +#define VPD_KEY_SERIAL "serial_number" +#define VPD_KEY_UUID "UUID" +#define VPD_SERIAL_LEN 17 + +const char *smbios_system_serial_number(void) +{ + static char serial[VPD_SERIAL_LEN]; + + if (vpd_gets(VPD_KEY_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) + return serial; + + printk(BIOS_ERR, "serial_number could not be read or invalid.\n"); + return ""; +} + +void smbios_system_set_uuid(u8 *uuid) +{ + static char vpd_uuid_string[UUID_STRLEN+1]; + + if (vpd_gets(VPD_KEY_UUID, vpd_uuid_string, UUID_STRLEN+1, VPD_RO)) { + if (parse_uuid(uuid, vpd_uuid_string)) + memset(uuid, 0, UUID_LEN); + else + return; + } + printk(BIOS_ERR, "UUID could not be read or invalid.\n"); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/38753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b6ce769cfa81a1e248a35f6149b7d1bbcf1f836 Gerrit-Change-Number: 38753 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/facebook/monolith: Enable use of VPD
by Wim Vervoorn (Code Review) 18 Feb '20

18 Feb '20

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38752 ) Change subject: mb/facebook/monolith: Enable use of VPD ...................................................................... mb/facebook/monolith: Enable use of VPD Enable use of VPD for monolith. This will be used to store the UUID and Serial number. BUG=N/A TEST=build Change-Id: I32b60fef44929c51427a124cbb81e5246db2546c Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/monolith/Kconfig M src/mainboard/facebook/monolith/vboot-ro.fmd M src/mainboard/facebook/monolith/vboot-rw.fmd 3 files changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/38752/1 diff --git a/src/mainboard/facebook/monolith/Kconfig b/src/mainboard/facebook/monolith/Kconfig index 203f8a5..b6c9f19 100644 --- a/src/mainboard/facebook/monolith/Kconfig +++ b/src/mainboard/facebook/monolith/Kconfig @@ -12,6 +12,7 @@ select MAINBOARD_USES_IFD_GBE_REGION select INTEL_GMA_HAVE_VBT select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE + select VPD config CBFS_SIZE hex "CBFS_SIZE" diff --git a/src/mainboard/facebook/monolith/vboot-ro.fmd b/src/mainboard/facebook/monolith/vboot-ro.fmd index 4abd883..569971a 100644 --- a/src/mainboard/facebook/monolith/vboot-ro.fmd +++ b/src/mainboard/facebook/monolith/vboot-ro.fmd @@ -13,12 +13,13 @@ RW_NVRAM(PRESERVE)@0x012000 0x6000 } WP_RO@0x20000 0x8E0000 { - RO_SECTION@0x0000 0x8E0000 { + RO_VPD(PRESERVE)@0x00000 0x1000 + RO_SECTION@0x1000 0x8DF000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 GBB@0x1000 0x4000 - COREBOOT(CBFS)@0x5000 0x8DB000 + COREBOOT(CBFS)@0x5000 0x8DA000 } } } diff --git a/src/mainboard/facebook/monolith/vboot-rw.fmd b/src/mainboard/facebook/monolith/vboot-rw.fmd index df2674b..dc2dadf 100644 --- a/src/mainboard/facebook/monolith/vboot-rw.fmd +++ b/src/mainboard/facebook/monolith/vboot-rw.fmd @@ -18,12 +18,13 @@ FW_MAIN_A(CBFS)@0x10040 0x84FFC0 } WP_RO@0x880000 0x080000 { - RO_SECTION@0x0000 0x80000 { + RO_VPD(PRESERVE)@0x00000 0x1000 + RO_SECTION@0x1000 0x7F000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 GBB@0x1000 0x4000 - COREBOOT(CBFS)@0x5000 0x07B000 + COREBOOT(CBFS)@0x5000 0x07A000 } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/38752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32b60fef44929c51427a124cbb81e5246db2546c Gerrit-Change-Number: 38752 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/intel/common/cse: Add helper functions to support CSE FW update
by Sridhar Siricilla (Code Review) 18 Feb '20

18 Feb '20

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36786 ) Change subject: src/soc/intel/common/cse: Add helper functions to support CSE FW update ...................................................................... src/soc/intel/common/cse: Add helper functions to support CSE FW update Below helper functions are added: * cse_wait_opmode_soft_temp_disable() - It polls for CSE's operation mode 'Soft Temporary Disable". The CSE enters this mode when it boots from RO_BP1 region. * cse_check_opmode_soft_temp_disable() - It reads CSE's FWSTS1 register and checks for CSE's operation mode 'Soft Temporary Disable'. Change-Id: Ibdcf01f31b0310932b8e834ae83144f8a67f1fef Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/36786/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 247e60a..d7fd21b 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -294,6 +294,35 @@ return 1; } +static int cse_check_opmode_soft_temp_disable(void) +{ + union me_hfsts1 hfs1; + + hfs1.data = me_read_config32(PCI_ME_HFSTS1); + + if (hfs1.fields.operation_mode == ME_HFS_TEMP_DISABLE) + return 1; + else + return 0; +} + +/* + * Polls for CSE's operation mode 'Soft Temporary Disable'. + * The CSE enters the operation mode when it boots from RO_BP1 region. + */ +uint8_t cse_wait_opmode_soft_temp_disable(void) +{ + struct stopwatch sw; + stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY); + while (!check_cse_opmode_soft_disable_state()) { + udelay(HECI_DELAY); + if (stopwatch_expired(&sw)) + return 0; + } + + return 1; +} + static int wait_heci_ready(void) { struct stopwatch sw; -- To view, visit https://review.coreboot.org/c/coreboot/+/36786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdcf01f31b0310932b8e834ae83144f8a67f1fef Gerrit-Change-Number: 36786 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: use list of northbridge device IDs
by Jonathan Kollasch (Code Review) 18 Feb '20

18 Feb '20

Jonathan Kollasch has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38882 ) Change subject: nb/intel/sandybridge: use list of northbridge device IDs ...................................................................... nb/intel/sandybridge: use list of northbridge device IDs Change-Id: Ida311a7b0c1f33b1724a07c7cd64ea9834cfc179 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- M src/northbridge/intel/sandybridge/northbridge.c 1 file changed, 5 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38882/1 diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index a9b1c25..68f8411 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -460,34 +460,16 @@ .acpi_fill_ssdt_generator = generate_cpu_entries, }; -static const struct pci_driver mc_driver_0100 __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0100, +static const unsigned short pci_device_ids[] = { + 0x0100, 0x0104, /* Sandy Bridge */ + 0x0150, 0x0154, 0x0158, /* Ivy Bridge */ + 0 }; static const struct pci_driver mc_driver __pci_driver = { .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0104, /* Sandy bridge */ -}; - -static const struct pci_driver mc_driver_150 __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0150, /* Ivy bridge */ -}; - -static const struct pci_driver mc_driver_1 __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0154, /* Ivy bridge */ -}; - -static const struct pci_driver mc_driver_158 __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0158, /* Ivy bridge */ + .devices = pci_device_ids, }; static struct device_operations cpu_bus_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/38882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida311a7b0c1f33b1724a07c7cd64ea9834cfc179 Gerrit-Change-Number: 38882 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Kollasch <jakllsch(a)kollasch.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Check prerequisites for HMRFPO_GET_STATUS command
by Sridhar Siricilla (Code Review) 18 Feb '20

18 Feb '20

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38799 ) Change subject: soc/intel/common: Check prerequisites for HMRFPO_GET_STATUS command ...................................................................... soc/intel/common: Check prerequisites for HMRFPO_GET_STATUS command Add code to check prerequisites before sending HMRFPO_GET_STATUS command. TEST=Verified on hatch. Change-Id: I4380e5096c6346d88aae6826d19a2f4ed1e97036 Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/38799/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 80f5a49..6035aaf 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -730,6 +730,11 @@ printk(BIOS_INFO, "HECI: Sending Get HMRFPO Status Command\n"); + if (!cse_is_hfs1_cws_normal()) { + printk(BIOS_ERR, "HECI: CSE does not meet required prerequisites\n"); + return -1; + } + if (!heci_send_receive(&msg, sizeof(struct hmrfpo_get_status_msg), &resp, &resp_size)) { printk(BIOS_ERR, "HECI: HMRFPO send/receive fail\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/38799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4380e5096c6346d88aae6826d19a2f4ed1e97036 Gerrit-Change-Number: 38799 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2020