coreboot-gerrit February 2020

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Change in coreboot[4.11_branch]: 4.11 branch builder test
by Martin Roth (Code Review) 18 Feb '20

18 Feb '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38950 ) Change subject: 4.11 branch builder test ...................................................................... 4.11 branch builder test Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I4b2c2d2c53d1c1aad1660710d1c0522e0b1863ab --- M Makefile 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/38950/1 diff --git a/Makefile b/Makefile index f3f9592..0a0707e 100644 --- a/Makefile +++ b/Makefile @@ -30,6 +30,9 @@ ## SUCH DAMAGE. ## +## 4.11 branch test + + ifneq ($(words $(CURDIR)),1) $(error Error: Path to the main directory cannot contain spaces) endif -- To view, visit https://review.coreboot.org/c/coreboot/+/38950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I4b2c2d2c53d1c1aad1660710d1c0522e0b1863ab Gerrit-Change-Number: 38950 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[4.11_branch]: Makefile.inc: Adapt $(spc) definition
by Martin Roth (Code Review) 18 Feb '20

18 Feb '20

Martin Roth has uploaded a new patch set (#2) to the change originally created by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/38958 ) Change subject: Makefile.inc: Adapt $(spc) definition ...................................................................... Makefile.inc: Adapt $(spc) definition GNU Make 4.3 is more picky about the $(spc) definition. It seems, the variable ends up empty. The old definition worked for nearly 8 years, RIP. Tested with GNU Make 4.2.1 and 4.3. Change-Id: I7981e0066b550251ae4a98d7b50e83049fc5586a Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38790 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> (cherry picked from commit 0f6f70c3942c152c512b1aa51b6f6079a05e003b) --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/38958/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/38958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I7981e0066b550251ae4a98d7b50e83049fc5586a Gerrit-Change-Number: 38958 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede: Add console UART configuration
by Karthik Ramasubramanian (Code Review) 18 Feb '20

18 Feb '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38776 ) Change subject: mb/google/dedede: Add console UART configuration ...................................................................... mb/google/dedede: Add console UART configuration Enable UART Port 2 as console UART and configure the concerned GPIOs. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I30a64a3c96226ce3244d55919b6d65fbf0a096e2 --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c 3 files changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/38776/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 9b5bd4a..c2f66a4 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -6,6 +6,7 @@ select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index e98b686..4b2a3c5 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -49,7 +49,7 @@ register "SerialIoUartMode" = "{ [PchSerialIoIndexUART0] = PchSerialIoDisabled, [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" # Intel Common SoC Config @@ -91,7 +91,7 @@ device pci 17.0 off end # SATA device pci 19.0 off end # I2C 4 device pci 19.1 off end # I2C 5 - device pci 19.2 off end # UART 2 + device pci 19.2 on end # UART 2 device pci 1a.0 off end # eMMC device pci 1c.0 off end # PCI Express Root Port 1 device pci 1c.1 off end # PCI Express Root Port 2 diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index b9d77bf..c334f11 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -32,6 +32,15 @@ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C20 : UART_DBG_TX_AP_RX */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* C21 : UART_AP_TX_DBG_RX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* C22 : UART2_RTS_N */ + PAD_NC(GPP_C22, DN_20K), + /* C23 : UART2_CTS_N */ + PAD_NC(GPP_C23, DN_20K), }; /* Early pad configuration in bootblock */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30a64a3c96226ce3244d55919b6d65fbf0a096e2 Gerrit-Change-Number: 38776 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[4.11_branch]: Makefile.inc: Ignore _HID & _ADR conflicts in Broadwell & Lynxpoint
by Martin Roth (Code Review) 18 Feb '20

18 Feb '20

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38959 ) Change subject: Makefile.inc: Ignore _HID & _ADR conflicts in Broadwell & Lynxpoint ...................................................................... Patch Set 1: I need to pull in the toolchain from the previous releases and use it for these builds. -- To view, visit https://review.coreboot.org/c/coreboot/+/38959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: Iced2e55e9f2aa7a262a5c1ffeff32af78acfa35e Gerrit-Change-Number: 38959 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 18 Feb 2020 00:00:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[4.11_branch]: Makefile.inc: Adapt $(spc) definition
by Nico Huber (Code Review) 17 Feb '20

17 Feb '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38958 ) Change subject: Makefile.inc: Adapt $(spc) definition ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/38958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I7981e0066b550251ae4a98d7b50e83049fc5586a Gerrit-Change-Number: 38958 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Mon, 17 Feb 2020 22:01:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: mb/lenovo: Make X1 uppercase
by Evgeny Zinoviev (Code Review) 17 Feb '20

17 Feb '20

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38935 ) Change subject: Documentation: mb/lenovo: Make X1 uppercase ...................................................................... Documentation: mb/lenovo: Make X1 uppercase x1 -> X1. Change-Id: Iab28e979102a6f98c41706ac0f483770466385dc Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M Documentation/mainboard/index.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/38935/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index ce30ee2..55903af 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -83,7 +83,7 @@ - [T420](lenovo/t420.md) - [T420 / T520 / X220 / T420s / W520 common](lenovo/xx20_series.md) -- [x1](lenovo/x1.md) +- [X1](lenovo/x1.md) ### Ivy Bridge series -- To view, visit https://review.coreboot.org/c/coreboot/+/38935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab28e979102a6f98c41706ac0f483770466385dc Gerrit-Change-Number: 38935 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation/lenovo: Replace RST code with markdown
by Patrick Rudolph (Code Review) 17 Feb '20

17 Feb '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38930 ) Change subject: Documentation/lenovo: Replace RST code with markdown ...................................................................... Documentation/lenovo: Replace RST code with markdown Latest Sphinx supports up path traversal in markdown. Replace old RST code that's no longer needed to prevent it being copy and pasted. Change-Id: Ieec5cc1f8d91a7fbc003efae465f61e6b72b39dc Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/mainboard/lenovo/t420.md M Documentation/mainboard/lenovo/t430.md M Documentation/mainboard/lenovo/t431s.md M Documentation/mainboard/lenovo/w530.md M Documentation/mainboard/lenovo/x1.md M Documentation/mainboard/lenovo/x301.md 6 files changed, 15 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/38930/1 diff --git a/Documentation/mainboard/lenovo/t420.md b/Documentation/mainboard/lenovo/t420.md index 40665b4..00ce45f 100644 --- a/Documentation/mainboard/lenovo/t420.md +++ b/Documentation/mainboard/lenovo/t420.md @@ -14,12 +14,10 @@ the blue dot pictured) to orient the pins! For more details have a look at [T420 / T520 / X220 / T420s / W520 common] and - -```eval_rst -:doc:`../../flash_tutorial/ext_power` -``` +the general [flashing tutorial]. Steps to access the flash IC are described here [T4xx series]. [T4xx series]: t4xx_series.md +[flashing tutorial]: ../../flash_tutorial/ext_power.md [T420 / T520 / X220 / T420s / W520 common]: Sandy_Bridge_series.md diff --git a/Documentation/mainboard/lenovo/t430.md b/Documentation/mainboard/lenovo/t430.md index 1ef4460..c2cddca 100644 --- a/Documentation/mainboard/lenovo/t430.md +++ b/Documentation/mainboard/lenovo/t430.md @@ -5,11 +5,10 @@ of the mainboard. For more details have a look at [T430 / T530 / X230 / T430s / W530 common] and -```eval_rst -:doc:`../../flash_tutorial/ext_power` -``` +the general [flashing tutorial]. Steps to access the flash IC are described here [T4xx series]. +[flashing tutorial]: ../../flash_tutorial/ext_power.md [T4xx series]: t4xx_series.md [T430 / T530 / X230 / T430s / W530 common]: Ivy_Bridge_series.md diff --git a/Documentation/mainboard/lenovo/t431s.md b/Documentation/mainboard/lenovo/t431s.md index 48315a2..f177e0f 100644 --- a/Documentation/mainboard/lenovo/t431s.md +++ b/Documentation/mainboard/lenovo/t431s.md @@ -26,9 +26,7 @@ ![t431s_programming](t431s_programming.jpg) -```eval_rst -:doc:`../../flash_tutorial/ext_power` -``` +The general [flashing tutorial] has more details. Currently, detecting the model of soldered RAM at runtime and loading the corresponding SPD datum from CBFS is not implemented yet. You may diff --git a/Documentation/mainboard/lenovo/w530.md b/Documentation/mainboard/lenovo/w530.md index 3b54303..e3fe6b8 100644 --- a/Documentation/mainboard/lenovo/w530.md +++ b/Documentation/mainboard/lenovo/w530.md @@ -10,9 +10,7 @@ both with an external programmer. For more details have a look at [T430 / T530 / X230 / T430s / W530 common] and -```eval_rst -:doc:`../../flash_tutorial/ext_power` -``` +the general [flashing tutorial]. ### After removing the keyboard and palm rest ![][w530-1] @@ -24,4 +22,5 @@ [w530-2]: w530-2.jpg +[flashing tutorial]: ../../flash_tutorial/ext_power.md [T430 / T530 / X230 / T430s / W530 common]: Ivy_Bridge_series.md diff --git a/Documentation/mainboard/lenovo/x1.md b/Documentation/mainboard/lenovo/x1.md index 9758197..9f915bc 100644 --- a/Documentation/mainboard/lenovo/x1.md +++ b/Documentation/mainboard/lenovo/x1.md @@ -13,12 +13,10 @@ a piece of insulation tape. For more details have a look at [T420 / T520 / X220 / T420s / W520 common] and - -```eval_rst -:doc:`../../flash_tutorial/ext_power` -``` +the general [flashing tutorial]. Steps to access the flash IC are described here [X2xx series]. [X2xx series]: x2xx_series.md +[flashing tutorial]: ../../flash_tutorial/ext_power.md [T420 / T520 / X220 / T420s / W520 common]: Sandy_Bridge_series.md diff --git a/Documentation/mainboard/lenovo/x301.md b/Documentation/mainboard/lenovo/x301.md index 28b512d..89b422f 100644 --- a/Documentation/mainboard/lenovo/x301.md +++ b/Documentation/mainboard/lenovo/x301.md @@ -26,9 +26,8 @@ -WINBOND_NEX_W25X64 (0xef, 0x3017) -ATMEL_AT25DF641 (0x1f, 0x4800) -```eval_rst -:doc:`../../flash_tutorial/ext_power` -``` +The general [flashing tutorial] has more details. + Tested: - CPU Core 2 Duo U9400 - Slotted DIMM 4GiB*2 from samsung @@ -42,3 +41,7 @@ - S3 - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from Linux payload (Heads) and Seabios. + + +[flashing tutorial]: ../../flash_tutorial/ext_power.md + -- To view, visit https://review.coreboot.org/c/coreboot/+/38930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieec5cc1f8d91a7fbc003efae465f61e6b72b39dc Gerrit-Change-Number: 38930 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: ifdtool/layout: use real table for FD regions
by Evgeny Zinoviev (Code Review) 17 Feb '20

17 Feb '20

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38933 ) Change subject: Documentation: ifdtool/layout: use real table for FD regions ...................................................................... Documentation: ifdtool/layout: use real table for FD regions Current doc transpiles to something completely unreadable. Change-Id: I197deb52974c88e067bc1615986a42c889214888 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M Documentation/ifdtool/layout.md 1 file changed, 20 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/38933/1 diff --git a/Documentation/ifdtool/layout.md b/Documentation/ifdtool/layout.md index 950db6f..2513929 100644 --- a/Documentation/ifdtool/layout.md +++ b/Documentation/ifdtool/layout.md @@ -14,14 +14,26 @@ starting with the prefix `SI_` which stands for `silicon initialization` as a way to categorize anything required by the SoC but not provided by coreboot. -|IFD Region index|IFD Region name|FMAP Name|Notes| -|---|---|---|---| -|0|Flash Descriptor|SI_DESC|Always the top 4KB of flash| -|1|BIOS|SI_BIOS|This is the region that contains coreboot| -|2|Intel ME|SI_ME|| -|3|Gigabit Ethernet|SI_GBE|| -|4|Platform Data|SI_PDR|| -|8|EC Firmware|SI_EC|Most Chrome OS devices do not use this region; EC firmware is stored BIOS region of flash| +```eval_rst ++------------+------------------+-----------+-------------------------------------------+ +| IFD Region | IFD Region name | FMAP Name | Notes | +| index | | | | ++============+==================+===========+===========================================+ +| 0 | Flash Descriptor | SI_DESC | Always the top 4KB of flash | ++------------+------------------+-----------+-------------------------------------------+ +| 1 | BIOS | SI_BIOS | This is the region that contains coreboot | ++------------+------------------+-----------+-------------------------------------------+ +| 2 | Intel ME | SI_ME | | ++------------+------------------+-----------+-------------------------------------------+ +| 3 | Gigabit Ethernet | SI_GBE | | ++------------+------------------+-----------+-------------------------------------------+ +| 4 | Platform Data | SI_PDR | | ++------------+------------------+-----------+-------------------------------------------+ +| 8 | EC Firmware | SI_EC | Most Chrome OS devices do not use this | +| | | | region; EC firmware is stored in BIOS | +| | | | region of flash | ++------------+------------------+-----------+-------------------------------------------+ +``` ## Validation -- To view, visit https://review.coreboot.org/c/coreboot/+/38933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I197deb52974c88e067bc1615986a42c889214888 Gerrit-Change-Number: 38933 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Remove confusing xyz0 naming convention for Lenovo dev...
by Patrick Rudolph (Code Review) 17 Feb '20

17 Feb '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38929 ) Change subject: Documentation: Remove confusing xyz0 naming convention for Lenovo devices ...................................................................... Documentation: Remove confusing xyz0 naming convention for Lenovo devices Replace xx30 with Ivy_Bridge and xx20 with Sandy_Bridge. Also add a note that the Ivy_Bridge tutorial doesn't covert T430s and T431s. Change-Id: I0b65bca83195ec22cc139130e7cb6183c0972484 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/mainboard/index.md R Documentation/mainboard/lenovo/Ivy_Bridge_series.md R Documentation/mainboard/lenovo/Sandy_Bridge_series.md R Documentation/mainboard/lenovo/flashlayout_Ivy_Bridge.svg R Documentation/mainboard/lenovo/flashlayout_Sandy_Bridge.svg M Documentation/mainboard/lenovo/t420.md M Documentation/mainboard/lenovo/t430.md M Documentation/mainboard/lenovo/t431s.md M Documentation/mainboard/lenovo/w530.md M Documentation/mainboard/lenovo/x1.md 10 files changed, 11 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/38929/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index ce30ee2..3e69119 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -82,7 +82,7 @@ ### Sandy Bridge series - [T420](lenovo/t420.md) -- [T420 / T520 / X220 / T420s / W520 common](lenovo/xx20_series.md) +- [T420 / T520 / X220 / T420s / W520 common](lenovo/Sandy_Bridge_series.md) - [x1](lenovo/x1.md) ### Ivy Bridge series @@ -90,7 +90,7 @@ - [T430](lenovo/t430.md) - [T530](lenovo/w530.md) - [W530](lenovo/w530.md) -- [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md) +- [T430 / T530 / X230 / W530 common](lenovo/Ivy_Bridge_series.md) - [T431s](lenovo/t431s.md) - [Internal flashing](lenovo/ivb_internal_flashing.md) diff --git a/Documentation/mainboard/lenovo/xx30_series.md b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md similarity index 96% rename from Documentation/mainboard/lenovo/xx30_series.md rename to Documentation/mainboard/lenovo/Ivy_Bridge_series.md index ad85605..2f83ffa 100644 --- a/Documentation/mainboard/lenovo/xx30_series.md +++ b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md @@ -1,5 +1,7 @@ # Lenovo Ivy Bridge series +This information is valid for all supported models, except T430s and T431s. + ## Flashing coreboot ```eval_rst +---------------------+--------------------------------+ @@ -72,5 +74,5 @@ ![][fl] -[fl]: flashlayout_xx30.svg +[fl]: flashlayout_Ivy_Bridge.svg diff --git a/Documentation/mainboard/lenovo/xx20_series.md b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md similarity index 97% rename from Documentation/mainboard/lenovo/xx20_series.md rename to Documentation/mainboard/lenovo/Sandy_Bridge_series.md index 8603853..0b833f5 100644 --- a/Documentation/mainboard/lenovo/xx20_series.md +++ b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md @@ -44,5 +44,5 @@ ![][fl] -[fl]: flashlayout_xx20.svg +[fl]: flashlayout_Sandy_Bridge.svg diff --git a/Documentation/mainboard/lenovo/flashlayout_xx30.svg b/Documentation/mainboard/lenovo/flashlayout_Ivy_Bridge.svg similarity index 100% rename from Documentation/mainboard/lenovo/flashlayout_xx30.svg rename to Documentation/mainboard/lenovo/flashlayout_Ivy_Bridge.svg diff --git a/Documentation/mainboard/lenovo/flashlayout_xx20.svg b/Documentation/mainboard/lenovo/flashlayout_Sandy_Bridge.svg similarity index 100% rename from Documentation/mainboard/lenovo/flashlayout_xx20.svg rename to Documentation/mainboard/lenovo/flashlayout_Sandy_Bridge.svg diff --git a/Documentation/mainboard/lenovo/t420.md b/Documentation/mainboard/lenovo/t420.md index 831cb58..40665b4 100644 --- a/Documentation/mainboard/lenovo/t420.md +++ b/Documentation/mainboard/lenovo/t420.md @@ -22,4 +22,4 @@ Steps to access the flash IC are described here [T4xx series]. [T4xx series]: t4xx_series.md -[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md +[T420 / T520 / X220 / T420s / W520 common]: Sandy_Bridge_series.md diff --git a/Documentation/mainboard/lenovo/t430.md b/Documentation/mainboard/lenovo/t430.md index 787246f..1ef4460 100644 --- a/Documentation/mainboard/lenovo/t430.md +++ b/Documentation/mainboard/lenovo/t430.md @@ -12,4 +12,4 @@ Steps to access the flash IC are described here [T4xx series]. [T4xx series]: t4xx_series.md -[T430 / T530 / X230 / T430s / W530 common]: xx30_series.md +[T430 / T530 / X230 / T430s / W530 common]: Ivy_Bridge_series.md diff --git a/Documentation/mainboard/lenovo/t431s.md b/Documentation/mainboard/lenovo/t431s.md index 146e1c12..48315a2 100644 --- a/Documentation/mainboard/lenovo/t431s.md +++ b/Documentation/mainboard/lenovo/t431s.md @@ -39,4 +39,4 @@ I do not know how to find gpio ports for that, and SPD data stored in vendor firmware.) -[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md +[T420 / T520 / X220 / T420s / W520 common]: Sandy_Bridge_series.md diff --git a/Documentation/mainboard/lenovo/w530.md b/Documentation/mainboard/lenovo/w530.md index f91d9ce..3b54303 100644 --- a/Documentation/mainboard/lenovo/w530.md +++ b/Documentation/mainboard/lenovo/w530.md @@ -24,4 +24,4 @@ [w530-2]: w530-2.jpg -[T430 / T530 / X230 / T430s / W530 common]: xx30_series.md +[T430 / T530 / X230 / T430s / W530 common]: Ivy_Bridge_series.md diff --git a/Documentation/mainboard/lenovo/x1.md b/Documentation/mainboard/lenovo/x1.md index cb9248a..9758197 100644 --- a/Documentation/mainboard/lenovo/x1.md +++ b/Documentation/mainboard/lenovo/x1.md @@ -21,4 +21,4 @@ Steps to access the flash IC are described here [X2xx series]. [X2xx series]: x2xx_series.md -[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md +[T420 / T520 / X220 / T420s / W520 common]: Sandy_Bridge_series.md -- To view, visit https://review.coreboot.org/c/coreboot/+/38929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b65bca83195ec22cc139130e7cb6183c0972484 Gerrit-Change-Number: 38929 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: capitalize 'BIOS'
by HAOUAS Elyes (Code Review) 17 Feb '20

17 Feb '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38932 ) Change subject: capitalize 'BIOS' ...................................................................... capitalize 'BIOS' Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Documentation/ifdtool/layout.md M Documentation/releases/coreboot-4.8.1-relnotes.md M Documentation/soc/intel/apollolake/index.md M Documentation/soc/intel/fit.md M Documentation/tutorial/part1.md M payloads/external/SeaBIOS/Kconfig M src/cpu/x86/smm/smm_module_loader.c M src/device/Kconfig M src/device/oprom/include/x86emu/x86emu.h M src/drivers/intel/gma/int15.c M src/mainboard/asus/p8z77-m_pro/cmos.layout M src/mainboard/asus/p8z77-m_pro/early_init.c M src/mainboard/google/cyan/Kconfig M src/mainboard/google/link/mainboard.c M src/mainboard/google/rambi/mainboard.c M src/mainboard/intel/strago/Kconfig M src/mainboard/kontron/ktqm77/mainboard.c M src/mainboard/lenovo/t420/early_init.c M src/soc/intel/apollolake/chip.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/pch/lockdown/lockdown.c M src/soc/intel/skylake/lockdown.c M util/inteltool/inteltool.8 M util/inteltool/spi.c 24 files changed, 34 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/38932/1 diff --git a/Documentation/ifdtool/layout.md b/Documentation/ifdtool/layout.md index 950db6f..84a9fa7 100644 --- a/Documentation/ifdtool/layout.md +++ b/Documentation/ifdtool/layout.md @@ -42,8 +42,8 @@ ```console foo@bar:~$ ifdtool -t bad_image.bin -Region mismatch between bios and SI_BIOS - Descriptor region bios: +Region mismatch between BIOS and SI_BIOS + Descriptor region BIOS: offset: 0x00400000 length: 0x01c00000 FMAP area SI_BIOS: @@ -63,4 +63,4 @@ FMAP area SI_PDR: offset: 0x007fc000 length: 0x00004000 -``` \ No newline at end of file +``` diff --git a/Documentation/releases/coreboot-4.8.1-relnotes.md b/Documentation/releases/coreboot-4.8.1-relnotes.md index 8a6ab96..e246236 100644 --- a/Documentation/releases/coreboot-4.8.1-relnotes.md +++ b/Documentation/releases/coreboot-4.8.1-relnotes.md @@ -40,7 +40,7 @@ Lenovo mainboards ----------------- -* Started integration of VBT (Video Bios Table) binary files to +* Started integration of VBT (Video BIOS Table) binary files to support native graphics initialisation Internal changes diff --git a/Documentation/soc/intel/apollolake/index.md b/Documentation/soc/intel/apollolake/index.md index d4a5ee5..01f4a7c 100644 --- a/Documentation/soc/intel/apollolake/index.md +++ b/Documentation/soc/intel/apollolake/index.md @@ -5,7 +5,7 @@ With Apollolake Intel invented another flash layout for x86 firmware called IFWI (Intel FirmWare Image). -Usually on x86 platforms the bootblock is stored at the end of the bios region +Usually on x86 platforms the bootblock is stored at the end of the BIOS region and the Intel ME / TXE has its own IFD region. On Apollolake both have been moved into the IFWI region, which is a subregion of "BIOS", since it allows to store multiple firmware components. diff --git a/Documentation/soc/intel/fit.md b/Documentation/soc/intel/fit.md index 8b638f0..553fef3 100644 --- a/Documentation/soc/intel/fit.md +++ b/Documentation/soc/intel/fit.md @@ -57,4 +57,4 @@ ## References * [Intel TXT LAB handout](https://downloadmirror.intel.com/18931/eng/Intel%20TXT%20LAB%20Han… -* [FIT bios specification](https://www.intel.com/content/dam/www/public/us/en/documents… +* [FIT BIOS specification](https://www.intel.com/content/dam/www/public/us/en/documents… diff --git a/Documentation/tutorial/part1.md b/Documentation/tutorial/part1.md index 0c7ef67..159aafe 100644 --- a/Documentation/tutorial/part1.md +++ b/Documentation/tutorial/part1.md @@ -173,7 +173,7 @@ This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3 PCI to ISA bridge. * `-bios build/coreboot.rom` -Use the bios rom image that we just built. If this flag is left out, the +Use the BIOS rom image that we just built. If this flag is left out, the standard SeaBIOS image that comes with QEMU is used. * `-serial stdio` Send the serial output to the console. This allows you to view the coreboot diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 8ec7361..e816775 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -125,7 +125,7 @@ level 1 - Basic output, interrupts 5, 18h, 19h, 40h, SMP, PNP, PMM level 2 - AHCI, Floppy, Basic ps2, interrupts 11h, 12h, 14h, 17h level 3 - bootsplash, initializations, SeaBIOS VGA BIOS interrupts - level 4 - bios tables, more optionrom + level 4 - BIOS tables, more optionrom level 5 - Extra bootsplash, more XHCI level 6 - ATA commands, extra optionrom level 7 - extra ps2 commands, more OHCI & EHCI diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 81020a4..a6714b2 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -397,7 +397,7 @@ total_size = total_stack_size + handler_size; total_size += fxsave_size + SMM_DEFAULT_SIZE; - // account for the bios resource list + // account for the BIOS resource list if (CONFIG(STM)) total_size += CONFIG_BIOS_RESOURCE_LIST_SIZE; diff --git a/src/device/Kconfig b/src/device/Kconfig index a25bb91..603c7eb 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -721,7 +721,7 @@ config INTEL_GMA_ADD_VBT depends on SOC_INTEL_COMMON || CPU_INTEL_COMMON - bool "Add a Video Bios Table (VBT) binary to CBFS" + bool "Add a Video BIOS Table (VBT) binary to CBFS" default y if INTEL_GMA_HAVE_VBT help Add a VBT data file to CBFS. The VBT describes the integrated diff --git a/src/device/oprom/include/x86emu/x86emu.h b/src/device/oprom/include/x86emu/x86emu.h index 4ae82d9..e7f48e4 100644 --- a/src/device/oprom/include/x86emu/x86emu.h +++ b/src/device/oprom/include/x86emu/x86emu.h @@ -170,7 +170,7 @@ #define DEBUG_SVC_F 0x000020 #define DEBUG_FS_F 0x000080 #define DEBUG_PROC_F 0x000100 -#define DEBUG_SYSINT_F 0x000200 /* bios system interrupts. */ +#define DEBUG_SYSINT_F 0x000200 /* BIOS system interrupts. */ #define DEBUG_TRACECALL_F 0x000400 #define DEBUG_INSTRUMENT_F 0x000800 #define DEBUG_MEM_TRACE_F 0x001000 diff --git a/src/drivers/intel/gma/int15.c b/src/drivers/intel/gma/int15.c index 7e0ece3..11efe8c 100644 --- a/src/drivers/intel/gma/int15.c +++ b/src/drivers/intel/gma/int15.c @@ -33,7 +33,7 @@ * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video BIOS default */ X86_AX = 0x005f; X86_CX = pfit; diff --git a/src/mainboard/asus/p8z77-m_pro/cmos.layout b/src/mainboard/asus/p8z77-m_pro/cmos.layout index da29d1c..4ac7b5d 100644 --- a/src/mainboard/asus/p8z77-m_pro/cmos.layout +++ b/src/mainboard/asus/p8z77-m_pro/cmos.layout @@ -77,7 +77,7 @@ 421 2 e 8 usb3_mode # usb3_drv -# Load (or not) pre-OS xHCI USB3 bios driver +# Load (or not) pre-OS xHCI USB3 BIOS driver # 423 1 e 1 usb3_drv diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c index 800d975..6c76a7a 100644 --- a/src/mainboard/asus/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8z77-m_pro/early_init.c @@ -115,7 +115,7 @@ .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 0, /* Asus 2203 bios shows XUECA016, but no EC */ + .ec_present = 0, /* Asus 2203 BIOS shows XUECA016, but no EC */ .gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */ .dimm_channel0_disabled = 0, /* Both DIMM enabled */ .dimm_channel1_disabled = 0, /* Both DIMM enabled */ diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index 6331419..94ffbc0 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -78,7 +78,7 @@ depends on VGA_BIOS default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin" help - The C0 version of the video bios gets computed from this name + The C0 version of the video BIOS gets computed from this name so that they can both be added. Only the correct one for the system will be run. @@ -87,7 +87,7 @@ depends on VGA_BIOS default "8086,22b0" help - The VGA_BIOS_ID for the C0 version of the video bios is hardcoded + The VGA_BIOS_ID for the C0 version of the video BIOS is hardcoded in soc/intel/braswell/Makefile.inc as 8086,22b1 config CBFS_SIZE diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 8be4012..32e5487 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -47,10 +47,10 @@ * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video BIOS default */ X86_AX = 0x005f; - X86_CL = 0x00; /* Use video bios default */ + X86_CL = 0x00; /* Use video BIOS default */ res = 1; break; case 0x5f35: @@ -66,7 +66,7 @@ * bit 7 = LFP2 */ X86_AX = 0x005f; - X86_CX = 0x0000; /* Use video bios default */ + X86_CX = 0x0000; /* Use video BIOS default */ res = 1; break; case 0x5f51: diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index d4e38d0..7e9b343 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -48,7 +48,7 @@ * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video BIOS default */ X86_AX = 0x005f; X86_CX = 0x0001; diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 5e710a5..640f5d4 100644 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -35,7 +35,7 @@ depends on VGA_BIOS default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin" help - The C0 version of the video bios gets computed from this name + The C0 version of the video BIOS gets computed from this name so that they can both be added. Only the correct one for the system will be run. @@ -44,7 +44,7 @@ depends on VGA_BIOS default "8086,22b0" help - The VGA_BIOS_ID for the C0 version of the video bios is hardcoded + The VGA_BIOS_ID for the C0 version of the video BIOS is hardcoded in soc/intel/braswell/Makefile.inc as 8086,22b1 config EC_GOOGLE_CHROMEEC_BOARDNAME diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index 2af5eb2..5cd3fc4 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -41,12 +41,12 @@ * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video BIOS default */ X86_EAX &= 0xffff0000; X86_EAX |= 0x005f; X86_ECX &= 0xffffff00; - X86_ECX |= 0x00; /* Use video bios default */ + X86_ECX |= 0x00; /* Use video BIOS default */ res = 1; break; case 0x5f35: @@ -64,7 +64,7 @@ X86_EAX &= 0xffff0000; X86_EAX |= 0x005f; X86_ECX &= 0xffff0000; - X86_ECX |= 0x0000; /* Use video bios default */ + X86_ECX |= 0x0000; /* Use video BIOS default */ res = 1; break; case 0x5f51: diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c index 2e39885..c675512 100644 --- a/src/mainboard/lenovo/t420/early_init.c +++ b/src/mainboard/lenovo/t420/early_init.c @@ -48,7 +48,7 @@ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -// OC3 set in bios to port 2-7, OC7 set in bios to port 10-13 +// OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13 const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* P0: system port 4, OC0 */ { 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */ diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index d9c42f9..b9c5a4f 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -733,7 +733,7 @@ /* Enable Audio clk gate and power gate */ silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; - /* Bios config lockdown Audio clk and power gate */ + /* BIOS config lockdown Audio clk and power gate */ silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown; if (CONFIG(SOC_INTEL_GLK)) glk_fsp_silicon_init_params_cb(cfg, silconfig); diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 019976a..49284e9 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -237,7 +237,7 @@ /* LOCAL APIC default address is 0xFEE0000, bios_size over 16MB will * cause memory type conflict when setting memory type to write - * protection, so limit the cached bios region to be no more than 16MB. + * protection, so limit the cached BIOS region to be no more than 16MB. * */ bios_size = MIN(bios_size, 16 * MiB); if (bios_size <= 0) diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index 4a3209e..3fa6e77 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -69,12 +69,12 @@ /* Lock FAST_SPIBAR */ fast_spi_lock_bar(); - /* Set Bios Interface Lock, Bios Lock */ + /* Set BIOS Interface Lock, BIOS Lock */ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { - /* Bios Interface Lock */ + /* BIOS Interface Lock */ fast_spi_set_bios_interface_lock_down(); - /* Bios Lock */ + /* BIOS Lock */ fast_spi_set_lock_enable(); } } diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c index 66dae8c..6911744 100644 --- a/src/soc/intel/skylake/lockdown.c +++ b/src/soc/intel/skylake/lockdown.c @@ -22,7 +22,7 @@ static void lpc_lockdown_config(int chipset_lockdown) { - /* Set Bios Interface Lock, Bios Lock */ + /* Set BIOS Interface Lock, BIOS Lock */ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { lpc_set_bios_interface_lock_down(); lpc_set_lock_enable(); diff --git a/util/inteltool/inteltool.8 b/util/inteltool/inteltool.8 index 86a76bd..01e3cfd 100644 --- a/util/inteltool/inteltool.8 +++ b/util/inteltool/inteltool.8 @@ -32,7 +32,7 @@ Dump I/O Controller Hub (ICH) southbridge RCBA registers. .TP .B "\-s, \-\-spi" -Dump I/O Controller Hub (ICH) southbridge SPI registers and bios control. +Dump I/O Controller Hub (ICH) southbridge SPI registers and BIOS control. .TP .B "\-f, \-\-gfx" .RB "Dump graphics registers. " \ diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c index 22ba3d4..e8289ac 100644 --- a/util/inteltool/spi.c +++ b/util/inteltool/spi.c @@ -22,7 +22,7 @@ { 0x1, 1, "BLE - lock enable" }, { 0x2, 2, "SPI Read configuration" }, { 0x4, 1, "TopSwapStatus" }, - { 0x5, 1, "SMM Bios Write Protect Disable" }, + { 0x5, 1, "SMM BIOS Write Protect Disable" }, { 0x6, 2, "reserved" }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/38932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273 Gerrit-Change-Number: 38932 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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