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Change in coreboot[master]: payloads: Fix typos
by HAOUAS Elyes (Code Review) 17 Feb '20

17 Feb '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38911 ) Change subject: payloads: Fix typos ...................................................................... payloads: Fix typos Change-Id: Ib7f1ba1766e5c972542ce7571a8aa3583c513823 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M payloads/coreinfo/cpuinfo_module.c M payloads/libpayload/drivers/i8042/keyboard.c M payloads/libpayload/drivers/serial/ipq40xx.c M payloads/libpayload/drivers/serial/ipq806x.c M payloads/libpayload/drivers/serial/qcs405.c M payloads/libpayload/drivers/udc/dwc2.c M payloads/libpayload/drivers/usb/dwc2.c M payloads/libpayload/drivers/usb/ehci.c M payloads/libpayload/drivers/usb/ohci.c M payloads/libpayload/drivers/usb/usb.c M payloads/libpayload/drivers/usb/usbhub.c M payloads/libpayload/drivers/usb/usbmsc.c M payloads/libpayload/drivers/video/graphics.c 13 files changed, 22 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/38911/1 diff --git a/payloads/coreinfo/cpuinfo_module.c b/payloads/coreinfo/cpuinfo_module.c index 94379f3..2b833a9 100644 --- a/payloads/coreinfo/cpuinfo_module.c +++ b/payloads/coreinfo/cpuinfo_module.c @@ -233,7 +233,7 @@ } if (cpu_khz != 0) - mvwprintw(win, row++, 1, "CPU Speed: %d Mhz", cpu_khz / 1000); + mvwprintw(win, row++, 1, "CPU Speed: %d MHz", cpu_khz / 1000); else mvwprintw(win, row++, 1, "CPU Speed: Error"); diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index 79455cf..4ddf99d 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -353,7 +353,7 @@ */ ret = keyboard_cmd(I8042_KBCMD_SET_DEFAULT); if (!ret) { - printf("ERROR: Keyboard set default params failed!\n"); + printf("ERROR: Keyboard set default parameters failed!\n"); return ret; } diff --git a/payloads/libpayload/drivers/serial/ipq40xx.c b/payloads/libpayload/drivers/serial/ipq40xx.c index 7656ad7..709f169 100644 --- a/payloads/libpayload/drivers/serial/ipq40xx.c +++ b/payloads/libpayload/drivers/serial/ipq40xx.c @@ -442,7 +442,7 @@ } /* - * msm_boot_uart_dm_init - initilaizes UART controller + * msm_boot_uart_dm_init - Initializes UART controller * @uart_dm_base: UART controller base address */ unsigned int msm_boot_uart_dm_init(void *uart_dm_base) @@ -550,7 +550,7 @@ static struct console_input_driver consin = {}; static struct console_output_driver consout = {}; -/* For simplicity sake let's rely on coreboot initalizing the UART. */ +/* For simplicity sake let's rely on coreboot initializing the UART. */ void serial_console_init(void) { struct cb_serial *sc_ptr = lib_sysinfo.serial; diff --git a/payloads/libpayload/drivers/serial/ipq806x.c b/payloads/libpayload/drivers/serial/ipq806x.c index 183ada6..0a62149 100644 --- a/payloads/libpayload/drivers/serial/ipq806x.c +++ b/payloads/libpayload/drivers/serial/ipq806x.c @@ -235,7 +235,7 @@ } /* - * msm_boot_uart_dm_init - initilaizes UART controller + * msm_boot_uart_dm_init - Initializes UART controller * @uart_dm_base: UART controller base address */ static unsigned int msm_boot_uart_dm_init(void *uart_dm_base) @@ -340,7 +340,7 @@ return byte; } -/* For simplicity sake let's rely on coreboot initalizing the UART. */ +/* For simplicity sake let's rely on coreboot initializing the UART. */ void serial_console_init(void) { struct cb_serial *sc_ptr = lib_sysinfo.serial; diff --git a/payloads/libpayload/drivers/serial/qcs405.c b/payloads/libpayload/drivers/serial/qcs405.c index 06ec5b9..d6151d2 100644 --- a/payloads/libpayload/drivers/serial/qcs405.c +++ b/payloads/libpayload/drivers/serial/qcs405.c @@ -434,7 +434,7 @@ } /* - * msm_boot_uart_dm_init - initilaizes UART controller + * msm_boot_uart_dm_init - Initializes UART controller * @uart_dm_base: UART controller base address */ unsigned int msm_boot_uart_dm_init(void *uart_dm_base) @@ -538,7 +538,7 @@ return byte; } -/* For simplicity sake let's rely on coreboot initalizing the UART. */ +/* For simplicity sake let's rely on coreboot initializing the UART. */ void serial_console_init(void) { struct cb_serial *sc_ptr = lib_sysinfo.serial; diff --git a/payloads/libpayload/drivers/udc/dwc2.c b/payloads/libpayload/drivers/udc/dwc2.c index e95eb79..f8a15e2 100644 --- a/payloads/libpayload/drivers/udc/dwc2.c +++ b/payloads/libpayload/drivers/udc/dwc2.c @@ -253,7 +253,7 @@ usb_debug("dwc2_halt_ep ep %d-%d\n", ep, in_dir); depctl.d32 = readl(&ep_reg->depctl); - /*Alread disabled*/ + /*Already disabled*/ if (!depctl.epena) return; /* First step: disable EP */ @@ -558,7 +558,7 @@ writel(DXEPINT_AHBERR, &ep->ep_regs->depint); } - /* Handle Setup Phase Done (Contorl Ep) */ + /* Handle Setup Phase Done (Control Ep) */ if (depint.setup) { usb_debug("DEPINT_SETUP\n"); writel(DXEPINT_SETUP, &ep->ep_regs->depint); diff --git a/payloads/libpayload/drivers/usb/dwc2.c b/payloads/libpayload/drivers/usb/dwc2.c index 963ae84..eef486b 100644 --- a/payloads/libpayload/drivers/usb/dwc2.c +++ b/payloads/libpayload/drivers/usb/dwc2.c @@ -233,7 +233,7 @@ packet_size = ep->maxpacketsize; packet_cnt = ALIGN_UP(size, packet_size) / packet_size; inpkt_length = packet_cnt * packet_size; - /* At least 1 packet should be programed */ + /* At least 1 packet should be programmed */ packet_cnt = (packet_cnt == 0) ? 1 : packet_cnt; /* diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index 6876340..1cfa8bb 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -78,7 +78,7 @@ usb_debug("+===================================================+\n"); usb_debug("| ############# EHCI QH at [0x%08lx] ########### |\n", virt_to_phys(cur)); usb_debug("+---------------------------------------------------+\n"); - usb_debug("| Horizonal Link Pointer [0x%08lx] |\n", cur->horiz_link_ptr); + usb_debug("| Horizontal Link Pointer [0x%08lx] |\n", cur->horiz_link_ptr); usb_debug("+------------------[ 0x%08lx ]-------------------+\n", cur->epchar); usb_debug("| | Maximum Packet Length | [%04ld] |\n", ((cur->epchar & (0x7ffUL << 16)) >> 16)); usb_debug("| | Device Address | [%ld] |\n", cur->epchar & 0x7F); @@ -133,7 +133,7 @@ { short count = 0; ehci_stop(controller); - /* wait 10 ms just to be shure */ + /* wait 10 ms just to be sure */ mdelay(10); if (EHCI_INST(controller)->operation->usbsts & HC_OP_HC_HALTED) { EHCI_INST(controller)->operation->usbcmd = HC_OP_HC_RESET; @@ -215,7 +215,7 @@ total_len += page_len; while (page_no < 5) { - /* we have a continguous mapping between virtual and physical memory */ + /* we have a contiguous mapping between virtual and physical memory */ page += 4096; td->bufptrs[page_no++] = page; diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index f1dc081..2571273 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -66,7 +66,7 @@ usb_debug("|:| C | Condition Code | [%02ld] |:|\n", (cur->config & (0xFUL << 28)) >> 28); usb_debug("|:| O | Direction/PID | [%ld] |:|\n", (cur->config & (3UL << 19)) >> 19); usb_debug("|:| N | Buffer Rounding | [%ld] |:|\n", (cur->config & (1UL << 18)) >> 18); - usb_debug("|:| F | Delay Intterrupt | [%ld] |:|\n", (cur->config & (7UL << 21)) >> 21); + usb_debug("|:| F | Delay Interrupt | [%ld] |:|\n", (cur->config & (7UL << 21)) >> 21); usb_debug("|:| I | Data Toggle | [%ld] |:|\n", (cur->config & (3UL << 24)) >> 24); usb_debug("|:| G | Error Count | [%ld] |:|\n", (cur->config & (3UL << 26)) >> 26); usb_debug("|:+-----------------------------------------------+:|\n"); @@ -879,7 +879,7 @@ intrq_td_t *const td = INTRQ_TD_FROM_TD(done_td); intr_queue_t *const intrq = td->intrq; /* Check if the corresponding interrupt - queue is still beeing processed. */ + queue is still being processed. */ if (intrq->destroy) { /* Free this TD, and */ free(td); diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index 4004def..d98fd9e 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -499,7 +499,7 @@ break; } - /* Gather up all endpoints belonging to this inteface */ + /* Gather up all endpoints belonging to this interface */ dev->num_endp = 1; for (; ptr + 2 <= end && ptr[0] && ptr + ptr[0] <= end; ptr += ptr[0]) { if (ptr[1] == DT_INTF || ptr[1] == DT_CFG || @@ -654,7 +654,7 @@ controller->devices[devno]->configuration = NULL; /* Tear down the device itself *after* destroy_device() - * has had a chance to interoogate it. */ + * has had a chance to interrogate it. */ free(controller->devices[devno]); controller->devices[devno] = NULL; } diff --git a/payloads/libpayload/drivers/usb/usbhub.c b/payloads/libpayload/drivers/usb/usbhub.c index 87c5816..5c39eac 100644 --- a/payloads/libpayload/drivers/usb/usbhub.c +++ b/payloads/libpayload/drivers/usb/usbhub.c @@ -285,7 +285,7 @@ return; } - /* Get number of ports from hub decriptor */ + /* Get number of ports from hub descriptor */ int type = is_usb_speed_ss(dev->speed) ? 0x2a : 0x29; /* similar enough */ hub_descriptor_t desc; /* won't fit the whole thing, we don't care */ if (get_descriptor(dev, gen_bmRequestType(device_to_host, class_type, diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c index d8b7bce..50fd24b 100755 --- a/payloads/libpayload/drivers/usb/usbmsc.c +++ b/payloads/libpayload/drivers/usb/usbmsc.c @@ -538,7 +538,7 @@ time_t start_time_secs; struct timeval tv; /* SCSI/ATA specs say we have to wait up to 30s, but most devices - * are ready much sooner. Use a 5 sec timeout to better accomodate + * are ready much sooner. Use a 5 sec timeout to better accommodate * devices which fail to respond. */ const int timeout_secs = 5; @@ -569,7 +569,7 @@ MSC_INST (dev)->ready = USB_MSC_NOT_READY; } - /* Don't bother spinning up the stroage device if the device is not + /* Don't bother spinning up the storage device if the device is not * ready. This can happen when empty card readers are present. * Polling will pick it back up if readiness changes. */ if (!MSC_INST (dev)->ready) diff --git a/payloads/libpayload/drivers/video/graphics.c b/payloads/libpayload/drivers/video/graphics.c index d346e4b..8cb984b8 100644 --- a/payloads/libpayload/drivers/video/graphics.c +++ b/payloads/libpayload/drivers/video/graphics.c @@ -509,7 +509,7 @@ * When d hits the right bottom corner, s0 also hits the right bottom * corner of the pixel array because that's how scale->x and scale->y * have been set. Since the pixel array size is already validated in - * parse_bitmap_header_v3, s0 is guranteed not to exceed pixel array + * parse_bitmap_header_v3, s0 is guaranteed not to exceed pixel array * boundary. */ struct vector s0, s1, d; -- To view, visit https://review.coreboot.org/c/coreboot/+/38911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7f1ba1766e5c972542ce7571a8aa3583c513823 Gerrit-Change-Number: 38911 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: libpayload/corebootfb: Fix character buffer relocation
by Nico Huber (Code Review) 17 Feb '20

17 Feb '20

Hello Julius Werner, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38536 to review the following change. Change subject: libpayload/corebootfb: Fix character buffer relocation ...................................................................... libpayload/corebootfb: Fix character buffer relocation The `chars` pointer references the heap which is part of the payload and relocated along with it. So calling phys_to_virt() on it was always wrong; and the virt_to_phys() at its initialization was a no-op anyway, when the console was brought up before relocation. While we are at it, add a null-pointer check. Change-Id: Ic03150f0bcd14a6ec6bf514dffe2b9153d5a6d2a Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M payloads/libpayload/drivers/video/corebootfb.c 1 file changed, 6 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/38536/1 diff --git a/payloads/libpayload/drivers/video/corebootfb.c b/payloads/libpayload/drivers/video/corebootfb.c index b5ad1a5..11397ba 100644 --- a/payloads/libpayload/drivers/video/corebootfb.c +++ b/payloads/libpayload/drivers/video/corebootfb.c @@ -64,11 +64,11 @@ /* Addresses for the various components */ static unsigned long fbinfo; static unsigned long fbaddr; -static unsigned long chars; +static unsigned short *chars; #define FI ((struct cb_framebuffer *) phys_to_virt(fbinfo)) #define FB ((unsigned char *) phys_to_virt(fbaddr)) -#define CHARS ((unsigned short *) phys_to_virt(chars)) +#define CHARS (chars) static void corebootfb_scroll_up(void) { @@ -243,9 +243,10 @@ coreboot_video_console.columns = FI->x_resolution / font_width; coreboot_video_console.rows = FI->y_resolution / font_height; - /* See setting of fbinfo above. */ - chars = virt_to_phys(malloc(coreboot_video_console.rows * - coreboot_video_console.columns * 2)); + chars = malloc(coreboot_video_console.rows * + coreboot_video_console.columns * 2); + if (!chars) + return -1; // clear boot splash screen if there is one. corebootfb_clear(); -- To view, visit https://review.coreboot.org/c/coreboot/+/38536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic03150f0bcd14a6ec6bf514dffe2b9153d5a6d2a Gerrit-Change-Number: 38536 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

6 12

Change in coreboot[master]: src/src/intel: Define HFSTS3 register
by Sridhar Siricilla (Code Review) 17 Feb '20

17 Feb '20

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38798 ) Change subject: src/src/intel: Define HFSTS3 register ...................................................................... src/src/intel: Define HFSTS3 register Changes: 1. Define HFSTS3 register across SoCs(apl/cnl/icl/tgl). 2. Define cse_is_hfs3_fw_sku_custom() which checks ME's Firmware SKU is Custom or not. TEST=Verified on hatch, soraka, bobba and iclrvp. Change-Id: I4188e58a4a08d87be2d84674e00ed1407fb8bf82 Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/apollolake/include/soc/me.h M src/soc/intel/cannonlake/include/soc/me.h M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h M src/soc/intel/icelake/include/soc/me.h M src/soc/intel/tigerlake/include/soc/me.h 6 files changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/38798/1 diff --git a/src/soc/intel/apollolake/include/soc/me.h b/src/soc/intel/apollolake/include/soc/me.h index 7ac4dee..e1916f6 100644 --- a/src/soc/intel/apollolake/include/soc/me.h +++ b/src/soc/intel/apollolake/include/soc/me.h @@ -40,4 +40,18 @@ } __packed fields; }; +/* ME Host Firmware Status Register 3 */ +union me_hfsts3 { + u32 data; + struct { + u32 reserved_0: 4; + u32 fw_sku: 3; + u32 reserved_7: 2; + u32 reserved_9: 2; + u32 resered_11: 3; + u32 resered_14: 16; + u32 reserved_30: 2; + } __packed fields; +}; + #endif /* _APOLLOLAKE_ME_H_ */ diff --git a/src/soc/intel/cannonlake/include/soc/me.h b/src/soc/intel/cannonlake/include/soc/me.h index 041769b..ba4a11a 100644 --- a/src/soc/intel/cannonlake/include/soc/me.h +++ b/src/soc/intel/cannonlake/include/soc/me.h @@ -44,6 +44,20 @@ } __packed fields; }; +/* ME Host Firmware Status Register 3 */ +union me_hfsts3 { + u32 data; + struct { + u32 reserved_0: 4; + u32 fw_sku: 3; + u32 reserved_7: 2; + u32 reserved_9: 2; + u32 resered_11: 3; + u32 resered_14: 16; + u32 reserved_30: 2; + } __packed fields; +}; + void dump_me_status(void *unused); #endif /* _CANNONLAKE_ME_H_ */ diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index e97cf26..c9feedd 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -270,6 +270,15 @@ return cse_check_hfs1_com(ME_HFS1_COM_SOFT_TEMP_DISABLE); } +bool cse_is_hfs3_fw_sku_custom(void) +{ + union me_hfsts3 hfs3; + hfs3.data = me_read_config32(PCI_ME_HFSTS3); + if (hfs3.fields.fw_sku == ME_HFS3_FW_SKU_CUSTOM) + return true; + return false; +} + /* Makes the host ready to communicate with CSE */ void cse_set_host_ready(void) { diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 6f8f4ff..af8d852 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -186,4 +186,10 @@ */ bool cse_is_hfs1_com_soft_temp_disable(void); +/* + * Checks CSE's Firmware SKU is Custom or not. + * Returns true if CSE's Firmware SKU is Custom, otherwise false + */ +bool cse_is_hfs3_fw_sku_custom(void); + #endif // SOC_INTEL_COMMON_CSE_H diff --git a/src/soc/intel/icelake/include/soc/me.h b/src/soc/intel/icelake/include/soc/me.h index b1646a2..1146fdf 100644 --- a/src/soc/intel/icelake/include/soc/me.h +++ b/src/soc/intel/icelake/include/soc/me.h @@ -40,4 +40,18 @@ } __packed fields; }; +/* ME Host Firmware Status Register 3 */ +union me_hfsts3 { + u32 data; + struct { + u32 reserved_0: 4; + u32 fw_sku: 3; + u32 reserved_7: 2; + u32 reserved_9: 2; + u32 resered_11: 3; + u32 resered_14: 16; + u32 reserved_30: 2; + } __packed fields; +}; + #endif /* _ICELAKE_ME_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/me.h b/src/soc/intel/tigerlake/include/soc/me.h index 3baa004..9bb41ca 100644 --- a/src/soc/intel/tigerlake/include/soc/me.h +++ b/src/soc/intel/tigerlake/include/soc/me.h @@ -40,4 +40,17 @@ } __packed fields; }; +/* ME Host Firmware Status Register 3 */ +union me_hfsts3 { + u32 data; + struct { + u32 reserved_0: 4; + u32 fw_sku: 3; + u32 reserved_7: 2; + u32 reserved_9: 2; + u32 resered_11: 3; + u32 resered_14: 16; + u32 reserved_30: 2; + } __packed fields; +}; #endif /* _TIGERLAKE_ME_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4188e58a4a08d87be2d84674e00ed1407fb8bf82 Gerrit-Change-Number: 38798 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: soc/intel/skl: Rename me_hfs union into me_hfsts
by Sridhar Siricilla (Code Review) 17 Feb '20

17 Feb '20

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38797 ) Change subject: soc/intel/skl: Rename me_hfs union into me_hfsts ...................................................................... soc/intel/skl: Rename me_hfs union into me_hfsts Rename below union tags for consistency: me_hfs2 -> me_hfsts2 me_hfs3 -> me_hfsts3 me_hfs6 -> me_hfsts6 TEST=Verified on Soraka Change-Id: Ibb53e6a5f2b95021f86b3e42e100b711b7d6e64e Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/skylake/include/soc/me.h M src/soc/intel/skylake/me.c 2 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/38797/1 diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index e8de30d..332340f 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -147,7 +147,7 @@ } __packed fields; }; -union me_hfs2 { +union me_hfsts2 { u32 data; struct { u32 reserved1: 3; @@ -168,7 +168,7 @@ } __packed fields; }; -union me_hfs3 { +union me_hfsts3 { u32 data; struct { u32 reserved1: 4; @@ -184,7 +184,7 @@ #define ME_HFS6_FPF_NOT_COMMITTED 0x0 #define ME_HFS6_FPF_ERROR 0x2 -union me_hfs6 { +union me_hfsts6 { u32 data; struct { u32 reserved1: 30; diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index 17a66bc..b45234e 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -273,9 +273,9 @@ void intel_me_status(void) { union me_hfsts1 hfs1; - union me_hfs2 hfs2; - union me_hfs3 hfs3; - union me_hfs6 hfs6; + union me_hfsts2 hfs2; + union me_hfsts3 hfs3; + union me_hfsts6 hfs6; if (!is_cse_enabled()) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/38797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb53e6a5f2b95021f86b3e42e100b711b7d6e64e Gerrit-Change-Number: 38797 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: util/k8resdump: Remove util
by Arthur Heymans (Code Review) 17 Feb '20

17 Feb '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36085 ) Change subject: util/k8resdump: Remove util ...................................................................... util/k8resdump: Remove util AMD K8 support dropped. Change-Id: I94c38e588c0ebdc6b9e830067c935814a5d26b0a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- D util/k8resdump/Makefile D util/k8resdump/description.md D util/k8resdump/k8resdump.c 3 files changed, 0 insertions(+), 177 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/36085/1 diff --git a/util/k8resdump/Makefile b/util/k8resdump/Makefile deleted file mode 100644 index a1d4dfa..0000000 --- a/util/k8resdump/Makefile +++ /dev/null @@ -1,61 +0,0 @@ -## -## Makefile for k8resdump utility -## -## (C) 2005 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -PROGRAM = k8resdump - -CC = gcc -INSTALL = /usr/bin/env install -PREFIX = /usr/local -#CFLAGS = -O2 -g -Wall -Werror -CFLAGS = -Os -Wall -Werror -OS_ARCH = $(shell uname) -ifeq ($(OS_ARCH), SunOS) -LDFLAGS = -lpci -else -LDFLAGS = -lpci -lz -static -endif - -OBJS = k8resdump.o - -all: pciutils dep $(PROGRAM) - -$(PROGRAM): $(OBJS) - $(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS) - -clean: - rm -f *.o *~ - -distclean: clean - rm -f $(PROGRAM) .dependencies - -dep: - @$(CC) -MM *.c > .dependencies - -pciutils: - @echo; echo -n "Checking for pciutils and zlib... " - @$(shell ( echo "#include <pci/pci.h>"; \ - echo "struct pci_access *pacc;"; \ - echo "int main(int argc, char **argv)"; \ - echo "{ pacc = pci_alloc(); return 0; }"; ) > .test.c ) - @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) &>/dev/null && \ - echo "found." || ( echo "not found."; echo; \ - echo "Please install pciutils-devel and zlib-devel."; \ - echo "See README for more information."; echo; \ - rm -f .test.c .test; exit 1) - @rm -f .test.c .test - -.PHONY: all clean distclean dep pciutils - --include .dependencies diff --git a/util/k8resdump/description.md b/util/k8resdump/description.md deleted file mode 100644 index dd1f144..0000000 --- a/util/k8resdump/description.md +++ /dev/null @@ -1,2 +0,0 @@ -This program will dump the IO/memory/PCI resources from the K8 memory -controller `C` diff --git a/util/k8resdump/k8resdump.c b/util/k8resdump/k8resdump.c deleted file mode 100644 index 66d7060..0000000 --- a/util/k8resdump/k8resdump.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the LinuxBIOS project. - * - * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License v2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This program will dump the IO/memory/PCI resources from the K8 - * memory controller - */ - -#include <stdio.h> -#include <stdlib.h> -#include <stdint.h> -#include <unistd.h> -#include <sys/types.h> -#include <pci/pci.h> - -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - -static uint8_t dram_bases[] = - { 0x40, 0x48, 0x50, 0x58, 0x60, 0x68, 0x70, 0x78 }; -static uint8_t dram_limits[] = - { 0x44, 0x4C, 0x54, 0x5C, 0x64, 0x6C, 0x74, 0x7C }; -static uint8_t iomem_bases[] = - { 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0, 0xB8 }; -static uint8_t iomem_limits[] = - { 0x84, 0x8C, 0x94, 0x9C, 0xA4, 0xAC, 0xB4, 0xBC }; - -static uint8_t pciio_bases[] = { 0xC0, 0xC8, 0xD0, 0xD8 }; -static uint8_t pciio_limits[] = { 0xC4, 0xCC, 0xD4, 0xDC }; - -void print_info(struct pci_dev *dev) -{ - int i; - uint32_t regb, regl; - - for (i = 0; i < ARRAY_SIZE(dram_bases); i++) { - regb = pci_read_long(dev, dram_bases[i]); - regl = pci_read_long(dev, dram_limits[i]); - - printf - ("DRAM map: #%d 0x%04x000000 - 0x%04xffffff Access: %s/%s" - " IntlvEN:0x%x IntlvSEL:0x%x Dstnode:%d\n", - i, regb >> 16, regl >> 16, regb & 1 ? "R" : "", - regb & 2 ? "W" : "", (regb & 0x700) >> 8, - (regl & 0x700) >> 8, (regl & 0x7)); - } - - - for (i = 0; i < ARRAY_SIZE(iomem_bases); i++) { - regb = pci_read_long(dev, iomem_bases[i]); - regl = pci_read_long(dev, iomem_limits[i]); - - printf - ("MMIO map: #%d 0x%06x0000 - 0x%06xffff Access: %s/%s %s %s" - " %s Dstnode:%d DstLink %d\n", - i, regb >> 8, regl >> 8, regb & 1 ? "R" : "", - regb & 2 ? "W" : "", regb & 4 ? "CPU Dis" : "", - regb & 8 ? "Locked" : "", - regl & 0x80 ? "NonPosted" : "", regl & 0x7, - (regl & 0x30) >> 4); - } - - for (i = 0; i < ARRAY_SIZE(pciio_bases); i++) { - regb = pci_read_long(dev, pciio_bases[i]); - regl = pci_read_long(dev, pciio_limits[i]); - - printf - (" IO map: #%d 0x%03x000 - 0x%03xfff Access: %s/%s %s %s" - " Dstnode:%d DstLink %d\n", - i, (regb & ~0xff000000) >> 12, - (regl & ~0xff000000) >> 12, regb & 1 ? "R" : "", - regb & 2 ? "W" : "", regb & 0x20 ? "ISA" : "", - regb & 0x10 ? "VGA" : "", regl & 0x7, - (regl & 0x30) >> 4); - } - - -} - -int main(void) -{ - struct pci_access *pacc; - struct pci_dev *dev; - - if (getuid()) { - fprintf(stderr, "Please run me root, need access to all" - " PCI regs!\n"); - exit(1); - } - - pacc = pci_alloc(); - pci_init(pacc); - pci_scan_bus(pacc); - for (dev = pacc->devices; dev; dev = dev->next) { - pci_fill_info(dev, PCI_FILL_IDENT | PCI_FILL_BASES | - PCI_FILL_CLASS); - if ((dev->vendor_id == 0x1022) /* AMD */ - && (dev->device_id == 0x1101)) { /* Address MAP */ - print_info(dev); - } - } - pci_cleanup(pacc); - return 0; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/36085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94c38e588c0ebdc6b9e830067c935814a5d26b0a Gerrit-Change-Number: 36085 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: src/soc/tigerlake: Add header specific changes for JSP
by Meera Ravindranath (Code Review) 17 Feb '20

17 Feb '20

Hello Ronak Kanabar, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38754 to review the following change. Change subject: src/soc/tigerlake: Add header specific changes for JSP ...................................................................... src/soc/tigerlake: Add header specific changes for JSP Updates the include files in tigerlake soc with JSP specific changes. BUG=None BRANCH=None TEST=Compilation for jasper lake board is working Change-Id: Ia8e88e02989fe80d7bd1f28942e005cb0d862fcb Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/tigerlake/include/soc/iomap.h M src/soc/intel/tigerlake/include/soc/irq.h A src/soc/intel/tigerlake/include/soc/irq_jsl.h A src/soc/intel/tigerlake/include/soc/irq_tgl.h 4 files changed, 213 insertions(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/38754/1 diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index 2e61477..01f11a5 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -42,12 +42,6 @@ UART_BASE_SIZE * (x))) #define UART_BASE(x) UART_BASE_0_ADDR(x) -#define EARLY_I2C_BASE_ADDRESS 0xfe020000 -#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) - -#define MCH_BASE_ADDRESS 0xfedc0000 -#define MCH_BASE_SIZE 0x20000 - #define DMI_BASE_ADDRESS 0xfeda0000 #define DMI_BASE_SIZE 0x1000 @@ -66,7 +60,6 @@ #define PCH_PWRM_BASE_SIZE 0x10000 #define SPI_BASE_ADDRESS 0xfe010000 -#define EARLY_GSPI_BASE_ADDRESS 0xfe030000 #define GPIO_BASE_SIZE 0x10000 @@ -78,6 +71,28 @@ #define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB) #define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB) +#if CONFIG(SOC_INTEL_TIGERLAKE) + +#define MCH_BASE_ADDRESS 0xfedc0000 +#define MCH_BASE_SIZE 0x20000 + +#define EARLY_GSPI_BASE_ADDRESS 0xfe030000 + +#define EARLY_I2C_BASE_ADDRESS 0xfe020000 +#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) + +#else /* CONFIG_SOC_INTEL_JASPERLAKE */ + +#define MCH_BASE_ADDRESS 0xfea80000 +#define MCH_BASE_SIZE 0x8000 + +#define EARLY_GSPI_BASE_ADDRESS 0xfe011000 + +#define EARLY_I2C_BASE_ADDRESS 0xfe040000 +#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) + +#endif + /* * I/O port address space */ diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h index 4d6318f..dec8376 100644 --- a/src/soc/intel/tigerlake/include/soc/irq.h +++ b/src/soc/intel/tigerlake/include/soc/irq.h @@ -16,69 +16,10 @@ #ifndef _SOC_IRQ_H_ #define _SOC_IRQ_H_ -#define GPIO_IRQ14 14 -#define GPIO_IRQ15 15 +#if CONFIG(SOC_INTEL_TIGERLAKE) + #include "irq_tgl.h" +#else + #include "irq_jsl.h" +#endif /* CONFIG_SOC_INTEL_TIGERLAKE */ -#define PCH_IRQ10 10 -#define PCH_IRQ11 11 - -#define LPSS_I2C0_IRQ 27 -#define LPSS_I2C1_IRQ 28 -#define LPSS_I2C2_IRQ 29 -#define LPSS_I2C3_IRQ 30 -#define LPSS_I2C4_IRQ 31 -#define LPSS_I2C5_IRQ 32 -#define LPSS_SPI0_IRQ 36 -#define LPSS_SPI1_IRQ 37 -#define LPSS_SPI2_IRQ 18 -#define LPSS_SPI3_IRQ 23 -#define LPSS_UART0_IRQ 34 -#define LPSS_UART1_IRQ 35 -#define LPSS_UART2_IRQ 33 - -#define HDA_IRQ 16 -#define SMBUS_IRQ 16 -#define TRACEHUB_IRQ 16 - -#define PCIE_1_IRQ 16 -#define PCIE_2_IRQ 17 -#define PCIE_3_IRQ 18 -#define PCIE_4_IRQ 19 -#define PCIE_5_IRQ 16 -#define PCIE_6_IRQ 17 -#define PCIE_7_IRQ 18 -#define PCIE_8_IRQ 19 -#define PCIE_9_IRQ 16 -#define PCIE_10_IRQ 17 -#define PCIE_11_IRQ 18 -#define PCIE_12_IRQ 19 - -#define SATA_IRQ 16 - -#define xHCI_IRQ 16 -#define xDCI_IRQ 17 -#define CNVI_WIFI_IRQ 16 - -#define CNVI_BT_IRQ 18 - -#define THC0_IRQ 16 -#define THC1_IRQ 17 - -#define ISH_IRQ 16 - -#define TBT_PCIe0_IRQ 16 -#define TBT_PCIe1_IRQ 17 -#define TBT_PCIe2_IRQ 18 -#define TBT_PCIe3_IRQ 19 - -#define HECI_1_IRQ 16 -#define HECI_2_IRQ 17 -#define HECI_3_IRQ 16 -#define HECI_4_IRQ 19 - -#define PEG_IRQ 16 -#define IGFX_IRQ 16 -#define THERMAL_IRQ 16 -#define IPU_IRQ 16 -#define GNA_IRQ 16 #endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/irq_jsl.h b/src/soc/intel/tigerlake/include/soc/irq_jsl.h new file mode 100644 index 0000000..fa94620 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/irq_jsl.h @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_JSL_IRQ_H_ +#define _SOC_JSL_IRQ_H_ + +#define GPIO_IRQ14 14 +#define GPIO_IRQ15 15 + +#define PCH_IRQ10 10 +#define PCH_IRQ11 11 + +#define SCI_IRQ9 9 +#define SCI_IRQ10 10 +#define SCI_IRQ11 11 +#define SCI_IRQ20 20 +#define SCI_IRQ21 21 +#define SCI_IRQ22 22 +#define SCI_IRQ23 23 + +#define TCO_IRQ9 9 +#define TCO_IRQ10 10 +#define TCO_IRQ11 11 +#define TCO_IRQ20 20 +#define TCO_IRQ21 21 +#define TCO_IRQ22 22 +#define TCO_IRQ23 23 + +#define LPSS_I2C0_IRQ 16 +#define LPSS_I2C1_IRQ 17 +#define LPSS_I2C2_IRQ 18 +#define LPSS_I2C3_IRQ 19 +#define LPSS_I2C4_IRQ 32 +#define LPSS_I2C5_IRQ 33 +#define LPSS_SPI0_IRQ 22 +#define LPSS_SPI1_IRQ 23 +#define LPSS_SPI2_IRQ 24 +#define LPSS_UART0_IRQ 20 +#define LPSS_UART1_IRQ 21 +#define LPSS_UART2_IRQ 34 +#define SDIO_IRQ 22 + +#define cAVS_INTA_IRQ 16 +#define SMBUS_INTA_IRQ 16 +#define SMBUS_INTB_IRQ 17 +#define GbE_INTA_IRQ 16 +#define GbE_INTC_IRQ 18 +#define TRACE_HUB_INTA_IRQ 16 +#define TRACE_HUB_INTD_IRQ 19 + +#define eMMC_IRQ 16 +#define SD_IRQ 19 + +#define PCIE_1_IRQ 16 +#define PCIE_2_IRQ 17 +#define PCIE_3_IRQ 18 +#define PCIE_4_IRQ 19 +#define PCIE_5_IRQ 16 +#define PCIE_6_IRQ 17 +#define PCIE_7_IRQ 18 +#define PCIE_8_IRQ 19 + +#define SATA_IRQ 16 + +#define HECI_1_IRQ 16 +#define HECI_2_IRQ 17 +#define IDER_IRQ 18 +#define KT_IRQ 19 +#define HECI_3_IRQ 16 + +#define XHCI_IRQ 16 +#define OTG_IRQ 17 +#define PMC_SRAM_IRQ 18 +#define THERMAL_IRQ 16 +#define CNViWIFI_IRQ 19 +#define UFS_IRQ 16 +#define CIO_INTA_IRQ 16 +#define CIO_INTD_IRQ 19 +#define ISH_IRQ 20 + +#define PEG_RP_INTA_IRQ 16 +#define PEG_RP_INTB_IRQ 17 +#define PEG_RP_INTC_IRQ 18 +#define PEG_RP_INTD_IRQ 19 + +#define IGFX_IRQ 16 +#define SA_THERMAL_IRQ 16 +#define IPU_IRQ 16 +#define GNA_IRQ 16 +#endif /* _JSL_IRQ_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/irq_tgl.h b/src/soc/intel/tigerlake/include/soc/irq_tgl.h new file mode 100644 index 0000000..2a446a6 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/irq_tgl.h @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TGL_IRQ_H_ +#define _SOC_TGL_IRQ_H_ + +#define GPIO_IRQ14 14 +#define GPIO_IRQ15 15 + +#define PCH_IRQ10 10 +#define PCH_IRQ11 11 + +#define LPSS_I2C0_IRQ 27 +#define LPSS_I2C1_IRQ 28 +#define LPSS_I2C2_IRQ 29 +#define LPSS_I2C3_IRQ 30 +#define LPSS_I2C4_IRQ 31 +#define LPSS_I2C5_IRQ 32 +#define LPSS_SPI0_IRQ 36 +#define LPSS_SPI1_IRQ 37 +#define LPSS_SPI2_IRQ 18 +#define LPSS_SPI3_IRQ 23 +#define LPSS_UART0_IRQ 34 +#define LPSS_UART1_IRQ 35 +#define LPSS_UART2_IRQ 33 + +#define HDA_IRQ 16 +#define SMBUS_IRQ 16 +#define TRACEHUB_IRQ 16 + +#define PCIE_1_IRQ 16 +#define PCIE_2_IRQ 17 +#define PCIE_3_IRQ 18 +#define PCIE_4_IRQ 19 +#define PCIE_5_IRQ 16 +#define PCIE_6_IRQ 17 +#define PCIE_7_IRQ 18 +#define PCIE_8_IRQ 19 +#define PCIE_9_IRQ 16 +#define PCIE_10_IRQ 17 +#define PCIE_11_IRQ 18 +#define PCIE_12_IRQ 19 + +#define SATA_IRQ 16 + +#define xHCI_IRQ 16 +#define xDCI_IRQ 17 +#define CNVI_WIFI_IRQ 16 + +#define CNVI_BT_IRQ 18 + +#define THC0_IRQ 16 +#define THC1_IRQ 17 + +#define ISH_IRQ 16 + +#define TBT_PCIe0_IRQ 16 +#define TBT_PCIe1_IRQ 17 +#define TBT_PCIe2_IRQ 18 +#define TBT_PCIe3_IRQ 19 + +#define HECI_1_IRQ 16 +#define HECI_2_IRQ 17 +#define HECI_3_IRQ 16 +#define HECI_4_IRQ 19 + +#define PEG_IRQ 16 +#define IGFX_IRQ 16 +#define THERMAL_IRQ 16 +#define IPU_IRQ 16 +#define GNA_IRQ 16 +#endif /* _SOC_IRQ_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8e88e02989fe80d7bd1f28942e005cb0d862fcb Gerrit-Change-Number: 38754 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: mb/google/drallion: Set baseline config for U42 and U62 CPU
by John Su (Code Review) 17 Feb '20

17 Feb '20

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38811 ) Change subject: mb/google/drallion: Set baseline config for U42 and U62 CPU ...................................................................... mb/google/drallion: Set baseline config for U42 and U62 CPU VR settings will be selected by CPU SKU. Change-Id: Ie471dee0c70e1831a822860c0a44455772a2b8be Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/38811/1 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 06d3e5d..489b383 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -65,6 +65,9 @@ register "PchHdaIDispCodecDisconnect" = "1" register "PchHdaAudioLinkHda" = "1" + # Select CPU PL2/PL4 config + register "cpu_pl2_4_cfg" = "baseline" + # VR Settings Configuration for 2/4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | -- To view, visit https://review.coreboot.org/c/coreboot/+/38811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie471dee0c70e1831a822860c0a44455772a2b8be Gerrit-Change-Number: 38811 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: util: Fix typos
by HAOUAS Elyes (Code Review) 17 Feb '20

17 Feb '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38653 ) Change subject: util: Fix typos ...................................................................... util: Fix typos Change-Id: Ia405384211aa53ac089a99ecd31acc25effdb71e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/amdfwtool/amdfwtool.c M util/cbmem/cbmem.c M util/ifdtool/ifdtool.c 3 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/38653/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index d5c63de..522d332 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1439,7 +1439,7 @@ integrate_firmwares(&ctx, amd_romsig, amd_fw_table); - ctx.current = ALIGN(ctx.current, 0x10000U); /* todo: is necessary? */ + ctx.current = ALIGN(ctx.current, 0x10000U); /* TODO: is necessary? */ if (multi) { /* Do 2nd PSP directory followed by 1st */ diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index ca6a2f4..f8da7da 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -258,7 +258,7 @@ * passed in memory offset. Could be called recursively in case a forwarding * entry is found. * - * Returns pointer to a memory buffer containg the timestamp table or zero if + * Returns pointer to a memory buffer containing the timestamp table or zero if * none found. */ diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 0b6b210..fb3fd89 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -631,11 +631,11 @@ static void dump_jid(uint32_t jid) { - printf(" SPI Componend Vendor ID: 0x%02x\n", + printf(" SPI Component Vendor ID: 0x%02x\n", jid & 0xff); - printf(" SPI Componend Device ID 0: 0x%02x\n", + printf(" SPI Component Device ID 0: 0x%02x\n", (jid >> 8) & 0xff); - printf(" SPI Componend Device ID 1: 0x%02x\n", + printf(" SPI Component Device ID 1: 0x%02x\n", (jid >> 16) & 0xff); } -- To view, visit https://review.coreboot.org/c/coreboot/+/38653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia405384211aa53ac089a99ecd31acc25effdb71e Gerrit-Change-Number: 38653 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: libpayload: arm64: Keep instruction cache enabled at all times
by Julius Werner (Code Review) 17 Feb '20

17 Feb '20

Hello Aaron Durbin, Hung-Te Lin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38908 to review the following change. Change subject: libpayload: arm64: Keep instruction cache enabled at all times ...................................................................... libpayload: arm64: Keep instruction cache enabled at all times This patch makes libpayload enable the instruction cache as the very first thing, which is similar to how we treat it in coreboot. It also prevents the icache from being disabled again during mmu_disable() as part of the two-stage page table setup in post_sysinfo_scan_mmu_setup(). It replaces the existing mmu_disable() implementation with the assembly version from coreboot which handles certain edge cases better (see CB:27238 for details). The SCTLR flag definitions in libpayload seem to have still been copy&pasted from arm32, so replace with the actual arm64 defintions from coreboot. Change-Id: Ifdbec34f0875ecc69fedcbea5c20e943379a3d2d Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/libpayload/arch/arm64/cpu.S M payloads/libpayload/arch/arm64/head.S M payloads/libpayload/arch/arm64/mmu.c M payloads/libpayload/include/arm64/arch/cache.h M payloads/libpayload/include/arm64/arch/lib_helpers.h 5 files changed, 39 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/38908/1 diff --git a/payloads/libpayload/arch/arm64/cpu.S b/payloads/libpayload/arch/arm64/cpu.S index d80f73c1..70a1044 100644 --- a/payloads/libpayload/arch/arm64/cpu.S +++ b/payloads/libpayload/arch/arm64/cpu.S @@ -29,6 +29,7 @@ */ #include <arch/asm.h> +#include <arch/lib_helpers.h> .macro dcache_apply_all crm dsb sy @@ -96,3 +97,17 @@ ENTRY(dcache_clean_invalidate_all) dcache_apply_all crm=cisw ENDPROC(dcache_clean_invalidate_all) + +/* This must be implemented in assembly to ensure there are no accesses to + memory (e.g. the stack) in between disabling and flushing the cache. */ +ENTRY(mmu_disable) + str x30, [sp, #-0x8] + mrs x0, sctlr_el2 + mov x1, #~(SCTLR_C | SCTLR_M) + and x0, x0, x1 + msr sctlr_el2, x0 + isb + bl dcache_clean_invalidate_all + ldr x30, [sp, #-0x8] + ret +ENDPROC(mmu_disable) diff --git a/payloads/libpayload/arch/arm64/head.S b/payloads/libpayload/arch/arm64/head.S index 8bac70f..c44169b8 100644 --- a/payloads/libpayload/arch/arm64/head.S +++ b/payloads/libpayload/arch/arm64/head.S @@ -28,11 +28,15 @@ */ #include <arch/asm.h> +#include <arch/lib_helpers.h> /* * Our entry point */ ENTRY(_entry) + /* Initialize SCTLR to intended state (icache and stack-alignment on) */ + ldr w1, =(SCTLR_RES1 | SCTLR_I | SCTLR_SA) + msr sctlr_el2, x1 /* Save off the location of the coreboot tables */ ldr x1, 1f diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c index d1dd5b0..3a5e04d 100644 --- a/payloads/libpayload/arch/arm64/mmu.c +++ b/payloads/libpayload/arch/arm64/mmu.c @@ -304,30 +304,6 @@ } /* - * Func: mmu_disable - * Desc: Invalidate caches and disable mmu - */ -void mmu_disable(void) -{ - uint32_t sctlr; - - sctlr = raw_read_sctlr_el2(); - sctlr &= ~(SCTLR_C | SCTLR_M | SCTLR_I); - - tlbiall_el2(); - dcache_clean_invalidate_all(); - - dsb(); - isb(); - - raw_write_sctlr_el2(sctlr); - - dcache_clean_invalidate_all(); - dsb(); - isb(); -} - -/* * Func: mmu_enable * Desc: Initialize MAIR, TCR, TTBR and enable MMU by setting appropriate bits * in SCTLR diff --git a/payloads/libpayload/include/arm64/arch/cache.h b/payloads/libpayload/include/arm64/arch/cache.h index de68cee..ace0e0e 100644 --- a/payloads/libpayload/include/arm64/arch/cache.h +++ b/payloads/libpayload/include/arm64/arch/cache.h @@ -35,38 +35,6 @@ #include <stddef.h> #include <stdint.h> -/* SCTLR bits */ -#define SCTLR_M (1 << 0) /* MMU enable */ -#define SCTLR_A (1 << 1) /* Alignment check enable */ -#define SCTLR_C (1 << 2) /* Data/unified cache enable */ -/* Bits 4:3 are reserved */ -#define SCTLR_CP15BEN (1 << 5) /* CP15 barrier enable */ -/* Bit 6 is reserved */ -#define SCTLR_B (1 << 7) /* Endianness */ -/* Bits 9:8 */ -#define SCTLR_SW (1 << 10) /* SWP and SWPB enable */ -#define SCTLR_Z (1 << 11) /* Branch prediction enable */ -#define SCTLR_I (1 << 12) /* Instruction cache enable */ -#define SCTLR_V (1 << 13) /* Low/high exception vectors */ -#define SCTLR_RR (1 << 14) /* Round Robin select */ -/* Bits 16:15 are reserved */ -#define SCTLR_HA (1 << 17) /* Hardware Access flag enable */ -/* Bit 18 is reserved */ -/* Bits 20:19 reserved virtualization not supported */ -#define SCTLR_WXN (1 << 19) /* Write permission implies XN */ -#define SCTLR_UWXN (1 << 20) /* Unprivileged write permission - implies PL1 XN */ -#define SCTLR_FI (1 << 21) /* Fast interrupt config enable */ -#define SCTLR_U (1 << 22) /* Unaligned access behavior */ -#define SCTLR_VE (1 << 24) /* Interrupt vectors enable */ -#define SCTLR_EE (1 << 25) /* Exception endianness */ -/* Bit 26 is reserved */ -#define SCTLR_NMFI (1 << 27) /* Non-maskable FIQ support */ -#define SCTLR_TRE (1 << 28) /* TEX remap enable */ -#define SCTLR_AFE (1 << 29) /* Access flag enable */ -#define SCTLR_TE (1 << 30) /* Thumb exception enable */ -/* Bit 31 is reserved */ - /* * Cache maintenance API */ diff --git a/payloads/libpayload/include/arm64/arch/lib_helpers.h b/payloads/libpayload/include/arm64/arch/lib_helpers.h index 7617f97..b2e3a06 100644 --- a/payloads/libpayload/include/arm64/arch/lib_helpers.h +++ b/payloads/libpayload/include/arm64/arch/lib_helpers.h @@ -30,11 +30,29 @@ #ifndef __ARCH_LIB_HELPERS_H__ #define __ARCH_LIB_HELPERS_H__ +#define SCTLR_M (1 << 0) /* MMU enable */ +#define SCTLR_A (1 << 1) /* Alignment check enable */ +#define SCTLR_C (1 << 2) /* Data/unified cache enable */ +#define SCTLR_SA (1 << 3) /* Stack alignment check enable */ +#define SCTLR_NAA (1 << 6) /* non-aligned access STA/LDR */ +#define SCTLR_I (1 << 12) /* Instruction cache enable */ +#define SCTLR_ENDB (1 << 13) /* Pointer auth (data B) */ +#define SCTLR_WXN (1 << 19) /* Write permission implies XN */ +#define SCTLR_IESB (1 << 21) /* Implicit error sync event */ +#define SCTLR_EE (1 << 25) /* Exception endianness (BE) */ +#define SCTLR_ENDA (1 << 27) /* Pointer auth (data A) */ +#define SCTLR_ENIB (1 << 30) /* Pointer auth (insn B) */ +#define SCTLR_ENIA (1 << 31) /* Pointer auth (insn A) */ +#define SCTLR_RES1 ((0x3 << 4) | (0x1 << 11) | (0x1 << 16) | \ + (0x1 << 18) | (0x3 << 22) | (0x3 << 28)) + #define DAIF_DBG_BIT (1 << 3) #define DAIF_ABT_BIT (1 << 2) #define DAIF_IRQ_BIT (1 << 1) #define DAIF_FIQ_BIT (1 << 0) +#ifndef __ASSEMBLER__ + #include <stdint.h> #define MAKE_REGISTER_ACCESSORS(reg) \ @@ -273,4 +291,6 @@ #define dsb() dsb_opt(sy) #define isb() isb_opt() +#endif /* __ASSEMBLER__ */ + #endif /* __ARCH_LIB_HELPERS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdbec34f0875ecc69fedcbea5c20e943379a3d2d Gerrit-Change-Number: 38908 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek: dsi: Correct bits_per_pixel for MIPI_DSI_FMT_RGB666
by Yu-Ping Wu (Code Review) 17 Feb '20

17 Feb '20

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38845 ) Change subject: soc/mediatek: dsi: Correct bits_per_pixel for MIPI_DSI_FMT_RGB666 ...................................................................... soc/mediatek: dsi: Correct bits_per_pixel for MIPI_DSI_FMT_RGB666 The number of bits per pixel for MIPI_DSI_FMT_RGB666 should be 24 instead of 18. BRANCH=none BUG=none TEST=none Change-Id: I9574502b2dec4b5a042df3886922ddd8c755da1a Signed-off-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/common/dsi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/38845/1 diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 238b1eb..3efcf16 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -28,9 +28,9 @@ switch (format) { case MIPI_DSI_FMT_RGB565: return 16; - case MIPI_DSI_FMT_RGB666: case MIPI_DSI_FMT_RGB666_PACKED: return 18; + case MIPI_DSI_FMT_RGB666: case MIPI_DSI_FMT_RGB888: return 24; } -- To view, visit https://review.coreboot.org/c/coreboot/+/38845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9574502b2dec4b5a042df3886922ddd8c755da1a Gerrit-Change-Number: 38845 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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