coreboot-gerrit February 2020

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Change in coreboot[master]: drivers/intel/gma: Print EDID with leading instead of trailing space
by Paul Menzel (Code Review) 17 Feb '20

17 Feb '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38915 ) Change subject: drivers/intel/gma: Print EDID with leading instead of trailing space ...................................................................... drivers/intel/gma: Print EDID with leading instead of trailing space This way, the block is a little indented below `EDID:` making it a little more structured for the eye. Change-Id: I12066efefb23c5ffa8ba6b8c486cd54e142d4dc1 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/drivers/intel/gma/edid.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/38915/1 diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index cf6ea51..ca3ab32 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -103,7 +103,7 @@ printk (BIOS_SPEW, "EDID:\n"); for (i = 0; i < 128; i++) { - printk(BIOS_SPEW, "%02x ", edid[i]); + printk(BIOS_SPEW, " %02x", edid[i]); if ((i & 0xf) == 0xf) printk (BIOS_SPEW, "\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/38915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12066efefb23c5ffa8ba6b8c486cd54e142d4dc1 Gerrit-Change-Number: 38915 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/gma: Remove space between `printf ()`
by Paul Menzel (Code Review) 17 Feb '20

17 Feb '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38914 ) Change subject: drivers/intel/gma: Remove space between `printf ()` ...................................................................... drivers/intel/gma: Remove space between `printf ()` Fix the warning below. WARNING: space prohibited between function name and open parenthesis '(' Change-Id: I28d9ba64c790c659040cd34eda37125e191dab39 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/drivers/intel/gma/edid.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/38914/1 diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 4d4aec3..cf6ea51 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -103,7 +103,7 @@ printk (BIOS_SPEW, "EDID:\n"); for (i = 0; i < 128; i++) { - printk (BIOS_SPEW, "%02x ", edid[i]); + printk(BIOS_SPEW, "%02x ", edid[i]); if ((i & 0xf) == 0xf) printk (BIOS_SPEW, "\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/38914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28d9ba64c790c659040cd34eda37125e191dab39 Gerrit-Change-Number: 38914 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/edid: Zero struct only when used
by Paul Menzel (Code Review) 17 Feb '20

17 Feb '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38913 ) Change subject: lib/edid: Zero struct only when used ...................................................................... lib/edid: Zero struct only when used Change-Id: I1c14e7458153fb992b17f30d7015321fae533bb2 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/lib/edid.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/38913/1 diff --git a/src/lib/edid.c b/src/lib/edid.c index 238fed5..048cc6a 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -1138,8 +1138,6 @@ .conformant = EDID_CONFORMANT, }; - memset(out, 0, sizeof(*out)); - if (!edid) { printk(BIOS_ERR, "No EDID found\n"); return EDID_ABSENT; @@ -1152,6 +1150,8 @@ return EDID_ABSENT; } + memset(out, 0, sizeof(*out)); + if (manufacturer_name(edid + 0x08, out->manufacturer_name)) c.manufacturer_name_well_formed = 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/38913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c14e7458153fb992b17f30d7015321fae533bb2 Gerrit-Change-Number: 38913 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/smm: Edit - improve clarity
by Name of user not set (Code Review) 17 Feb '20

17 Feb '20

cedarhouse1(a)comcast.net has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38821 ) Change subject: cpu/x86/smm: Edit - improve clarity ...................................................................... cpu/x86/smm: Edit - improve clarity Removed blank line to maintain the relation between the previous comment and the remainder of the block. Signed-off-by: Eugene D. Myers <edmyers(a)tycho.nsa.gov> Change-Id: Ib9754c6723ecd5e4895898490fc7228e1c3839d0 --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/38821/1 diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 81020a4..66a40c4 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -396,7 +396,6 @@ /* Does the required amount of memory exceed the SMRAM region size? */ total_size = total_stack_size + handler_size; total_size += fxsave_size + SMM_DEFAULT_SIZE; - // account for the bios resource list if (CONFIG(STM)) total_size += CONFIG_BIOS_RESOURCE_LIST_SIZE; -- To view, visit https://review.coreboot.org/c/coreboot/+/38821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9754c6723ecd5e4895898490fc7228e1c3839d0 Gerrit-Change-Number: 38821 Gerrit-PatchSet: 1 Gerrit-Owner: cedarhouse1(a)comcast.net Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/edid.c: Remove trailing space from detailed mode output
by Patrick Georgi (Code Review) 17 Feb '20

17 Feb '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/17644 ) Change subject: lib/edid.c: Remove trailing space from detailed mode output ...................................................................... lib/edid.c: Remove trailing space from detailed mode output When the bit for interlaced mode is not set, a trailing space is added to the end. As the space is already accounted for in `" interlaced"`, remove that space. TEST=Boot on Lenovo X60t, and verify the trailing space in the detailed mode is gone. Change-Id: I4114c9e61a040fa005c806404ec51c12e2f02f4d Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/17644 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> --- M src/lib/edid.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved diff --git a/src/lib/edid.c b/src/lib/edid.c index 4a2f07a..238fed5 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -573,7 +573,7 @@ "Detailed mode (IN HEX): Clock %d KHz, %x mm x %x mm\n" " %04x %04x %04x %04x hborder %x\n" " %04x %04x %04x %04x vborder %x\n" - " %chsync %cvsync%s%s %s\n", + " %chsync %cvsync%s%s%s\n", out->mode.pixel_clock, extra_info.x_mm, extra_info.y_mm, -- To view, visit https://review.coreboot.org/c/coreboot/+/17644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4114c9e61a040fa005c806404ec51c12e2f02f4d Gerrit-Change-Number: 17644 Gerrit-PatchSet: 4 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/octopus/variants/dood: add new SKU ID
by Kenneth Chan (Code Review) 17 Feb '20

17 Feb '20

Kenneth Chan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38730 ) Change subject: mb/google/octopus/variants/dood: add new SKU ID ...................................................................... mb/google/octopus/variants/dood: add new SKU ID add SKU ID 3 and 4 for dood DVT 1: Dood WiFi + LTE (evt) 2: Dood WiFi (evt) 3: Dood WiFi + LTE + dual camera (dvt) 4: Dood WiFi + dual camera (dvt) BUG=b:148988979 TEST=build firmware and verify on the DUT of sku 3 and 4 check LTE module with moden status Change-Id: If86efe2a2f7b2e165ad44220b6dd59e9080b5892 Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/dood/gpio.c M src/mainboard/google/octopus/variants/dood/variant.c 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/38730/1 diff --git a/src/mainboard/google/octopus/variants/dood/gpio.c b/src/mainboard/google/octopus/variants/dood/gpio.c index 5b567b3..ee4ca7f 100644 --- a/src/mainboard/google/octopus/variants/dood/gpio.c +++ b/src/mainboard/google/octopus/variants/dood/gpio.c @@ -22,6 +22,8 @@ enum { SKU_1_LTE = 1, /* Wifi + LTE */ SKU_2_WIFI = 2, /* Wifi */ + SKU_3_LTE_2CAM = 3, /* Wifi + LTE + dual camera*/ + SKU_4_WIFI_2CAM = 4, /* Wifi + dual Camera*/ }; static const struct pad_config default_override_table[] = { @@ -62,6 +64,7 @@ switch (sku_id) { case SKU_1_LTE: + case SKU_3_LTE_2CAM: *num = ARRAY_SIZE(lte_override_table); return lte_override_table; default: diff --git a/src/mainboard/google/octopus/variants/dood/variant.c b/src/mainboard/google/octopus/variants/dood/variant.c index 7116061..e4e4b18 100644 --- a/src/mainboard/google/octopus/variants/dood/variant.c +++ b/src/mainboard/google/octopus/variants/dood/variant.c @@ -23,6 +23,8 @@ enum { SKU_1_LTE = 1, /* Wifi + LTE */ SKU_2_WIFI = 2, /* Wifi */ + SKU_3_LTE_2CAM = 3, /* Wifi + LTE + dual camera*/ + SKU_4_WIFI_2CAM = 4, /* Wifi + dual Camera*/ }; struct gpio_with_delay { @@ -63,6 +65,7 @@ switch (get_board_sku()) { case SKU_1_LTE: + case SKU_3_LTE_2CAM: power_off_lte_module(slp_typ); return; default: -- To view, visit https://review.coreboot.org/c/coreboot/+/38730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If86efe2a2f7b2e165ad44220b6dd59e9080b5892 Gerrit-Change-Number: 38730 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/docker: Use more stable URL
by Patrick Georgi (Code Review) 17 Feb '20

17 Feb '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38899 ) Change subject: util/docker: Use more stable URL ...................................................................... util/docker: Use more stable URL The pgeorgi namespace is my own and things could change without notice there. encapsulate is now maintained on review.coreboot.org/encapsulate.git and mirrored over to github, so let's use that. Change-Id: I12e43f61f693a6b0392b84dd56ede665a1a2129a Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/docker/coreboot-jenkins-node/Dockerfile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/38899/1 diff --git a/util/docker/coreboot-jenkins-node/Dockerfile b/util/docker/coreboot-jenkins-node/Dockerfile index cfe5abb..73f7f18 100644 --- a/util/docker/coreboot-jenkins-node/Dockerfile +++ b/util/docker/coreboot-jenkins-node/Dockerfile @@ -45,7 +45,7 @@ echo "tmpfs /home/coreboot/.ccache tmpfs rw,mode=1777 0 0" >> /etc/fstab # Build encapsulate tool -ADD https://raw.githubusercontent.com/pgeorgi/encapsulate/master/encapsulate.c /tmp/encapsulate.c +ADD https://raw.githubusercontent.com/coreboot/encapsulate/master/encapsulate.c /tmp/encapsulate.c RUN gcc -o /usr/sbin/encapsulate /tmp/encapsulate.c && \ chown root /usr/sbin/encapsulate && \ chmod +s /usr/sbin/encapsulate -- To view, visit https://review.coreboot.org/c/coreboot/+/38899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12e43f61f693a6b0392b84dd56ede665a1a2129a Gerrit-Change-Number: 38899 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/drallion: correct USB3 OC pin error
by EricR Lai (Code Review) 17 Feb '20

17 Feb '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38885 ) Change subject: mb/google/drallion: correct USB3 OC pin error ...................................................................... mb/google/drallion: correct USB3 OC pin error USB3 OC pin was configured wrong pin. Follow HW circuit to set it. BUG=b:147869924 TEST=USB function works well Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I61234a2054ab52fa508482d3dd0f94b13f96a5c9 --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/38885/1 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 06d3e5d..92f3fb9 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -154,9 +154,9 @@ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Right Type-A Port 1 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port 2 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Right Type-A Port 1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port 2 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port 2 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN register "usb3_ports[5]" = "USB3_PORT_EMPTY" -- To view, visit https://review.coreboot.org/c/coreboot/+/38885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61234a2054ab52fa508482d3dd0f94b13f96a5c9 Gerrit-Change-Number: 38885 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/puff: Enable SPD_READ_BY_WORD to short the boottime
by Jamie Chen (Code Review) 17 Feb '20

17 Feb '20

Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38848 ) Change subject: mb/google/puff: Enable SPD_READ_BY_WORD to short the boottime ...................................................................... mb/google/puff: Enable SPD_READ_BY_WORD to short the boottime Puff uses the smbus to access SPD of memory DIMM. Add select SPD_READ_BY_WORD under BOARD_GOOGLE_PUFF in Kconfig.name It's for shorting the SPD reading time. BUG=b:149360051 BRANCH=None TEST=build puff and boot up OS ran cbmem -t | grep FspMemoryInit Without this patch: 950:calling FspMemoryInit 643,199 (257,588) With this patch: 950:calling FspMemoryInit 477,714 (154,612) Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> Change-Id: I161e8eb386ab604b16746f0deeecc3d6c9063c3a --- M src/mainboard/google/hatch/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38848/1 diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index e216135..2427b12 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -48,6 +48,7 @@ select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_32768 select ROMSTAGE_SPD_SMBUS + select SPD_READ_BY_WORD config BOARD_GOOGLE_HELIOS_DISKSWAP bool "-> Helios_Diskswap" -- To view, visit https://review.coreboot.org/c/coreboot/+/38848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I161e8eb386ab604b16746f0deeecc3d6c9063c3a Gerrit-Change-Number: 38848 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/apple/macbookair4_2: Add CMOS support
by Evgeny Zinoviev (Code Review) 17 Feb '20

17 Feb '20

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33045 Change subject: mb/apple/macbookair4_2: Add CMOS support ...................................................................... mb/apple/macbookair4_2: Add CMOS support Added CMOS support for MacBook Air 4,2. In future, I hope there will be more useful options available, because I'm working on macbooks support. Also, it may be necessary for hyper_threading support (#29669) once it will be ready. Change-Id: I369ed9aeff2098a4840918531be6a34cfc8d2a1e Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/mainboard/apple/macbookair4_2/Kconfig A src/mainboard/apple/macbookair4_2/cmos.default A src/mainboard/apple/macbookair4_2/cmos.layout 3 files changed, 100 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/33045/1 diff --git a/src/mainboard/apple/macbookair4_2/Kconfig b/src/mainboard/apple/macbookair4_2/Kconfig index 4b2ee8f..263d550 100644 --- a/src/mainboard/apple/macbookair4_2/Kconfig +++ b/src/mainboard/apple/macbookair4_2/Kconfig @@ -14,6 +14,8 @@ select SYSTEM_TYPE_LAPTOP select GFX_GMA_INTERNAL_IS_EDP select MAINBOARD_HAS_LIBGFXINIT + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE config MAINBOARD_DIR string diff --git a/src/mainboard/apple/macbookair4_2/cmos.default b/src/mainboard/apple/macbookair4_2/cmos.default new file mode 100644 index 0000000..53e85a3 --- /dev/null +++ b/src/mainboard/apple/macbookair4_2/cmos.default @@ -0,0 +1 @@ +debug_level=Debug diff --git a/src/mainboard/apple/macbookair4_2/cmos.layout b/src/mainboard/apple/macbookair4_2/cmos.layout new file mode 100644 index 0000000..86d55b4 --- /dev/null +++ b/src/mainboard/apple/macbookair4_2/cmos.layout @@ -0,0 +1,97 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +# ----------------------------------------------------------------- +entries +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused +#400 8 r 0 reserved for century byte +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +# coreboot config options: EC +#411 1 e 8 first_battery +#412 1 e 1 bluetooth +#413 1 e 1 wwan +#414 1 e 1 touchpad +#415 1 e 1 wlan +#416 1 e 1 trackpoint +#417 1 e 1 fn_ctrl_swap +#418 1 e 1 sticky_fn +#419 2 e 13 usb_always_on +#421 1 e 9 sata_mode +#422 2 e 10 backlight +# coreboot config options: cpu +#424 8 r 0 unused +# coreboot config options: northbridge +#432 5 e 11 gfx_uma_size +#437 3 r 0 unused +#440 8 h 0 volume +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk +# coreboot config options: check sums +984 16 h 0 check_sum +# ----------------------------------------------------------------- +enumerations +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums +checksum 392 447 984 -- To view, visit https://review.coreboot.org/c/coreboot/+/33045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I369ed9aeff2098a4840918531be6a34cfc8d2a1e Gerrit-Change-Number: 33045 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2020