coreboot-gerrit February 2020

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Change in ...coreboot[master]: mb/apple/macbookair4_2: Add CMOS support
by Evgeny Zinoviev (Code Review) 17 Feb '20

17 Feb '20

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33045 Change subject: mb/apple/macbookair4_2: Add CMOS support ...................................................................... mb/apple/macbookair4_2: Add CMOS support Added CMOS support for MacBook Air 4,2. In future, I hope there will be more useful options available, because I'm working on macbooks support. Also, it may be necessary for hyper_threading support (#29669) once it will be ready. Change-Id: I369ed9aeff2098a4840918531be6a34cfc8d2a1e Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/mainboard/apple/macbookair4_2/Kconfig A src/mainboard/apple/macbookair4_2/cmos.default A src/mainboard/apple/macbookair4_2/cmos.layout 3 files changed, 100 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/33045/1 diff --git a/src/mainboard/apple/macbookair4_2/Kconfig b/src/mainboard/apple/macbookair4_2/Kconfig index 4b2ee8f..263d550 100644 --- a/src/mainboard/apple/macbookair4_2/Kconfig +++ b/src/mainboard/apple/macbookair4_2/Kconfig @@ -14,6 +14,8 @@ select SYSTEM_TYPE_LAPTOP select GFX_GMA_INTERNAL_IS_EDP select MAINBOARD_HAS_LIBGFXINIT + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE config MAINBOARD_DIR string diff --git a/src/mainboard/apple/macbookair4_2/cmos.default b/src/mainboard/apple/macbookair4_2/cmos.default new file mode 100644 index 0000000..53e85a3 --- /dev/null +++ b/src/mainboard/apple/macbookair4_2/cmos.default @@ -0,0 +1 @@ +debug_level=Debug diff --git a/src/mainboard/apple/macbookair4_2/cmos.layout b/src/mainboard/apple/macbookair4_2/cmos.layout new file mode 100644 index 0000000..86d55b4 --- /dev/null +++ b/src/mainboard/apple/macbookair4_2/cmos.layout @@ -0,0 +1,97 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +# ----------------------------------------------------------------- +entries +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused +#400 8 r 0 reserved for century byte +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +# coreboot config options: EC +#411 1 e 8 first_battery +#412 1 e 1 bluetooth +#413 1 e 1 wwan +#414 1 e 1 touchpad +#415 1 e 1 wlan +#416 1 e 1 trackpoint +#417 1 e 1 fn_ctrl_swap +#418 1 e 1 sticky_fn +#419 2 e 13 usb_always_on +#421 1 e 9 sata_mode +#422 2 e 10 backlight +# coreboot config options: cpu +#424 8 r 0 unused +# coreboot config options: northbridge +#432 5 e 11 gfx_uma_size +#437 3 r 0 unused +#440 8 h 0 volume +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk +# coreboot config options: check sums +984 16 h 0 check_sum +# ----------------------------------------------------------------- +enumerations +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums +checksum 392 447 984 -- To view, visit https://review.coreboot.org/c/coreboot/+/33045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I369ed9aeff2098a4840918531be6a34cfc8d2a1e Gerrit-Change-Number: 33045 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

6 9

Change in coreboot[master]: mb/google/kukui: fine tune the video timing of panel-BOE_TV101WUM_N53
by jitao shi (Code Review) 17 Feb '20

17 Feb '20

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38401 ) Change subject: mb/google/kukui: fine tune the video timing of panel-BOE_TV101WUM_N53 ...................................................................... mb/google/kukui: fine tune the video timing of panel-BOE_TV101WUM_N53 Fine tune the video timing of panel-BOE_TV101WUM_N53 to avoid noise. Change-Id: Ia9e2cc90f233e87d712c2dc6f4441ca2e5423162 Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> --- M src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/38401/1 diff --git a/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c b/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c index dc5a2ac..10753d9 100644 --- a/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c +++ b/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c @@ -22,11 +22,11 @@ .panel_bits_per_color = 8, .panel_bits_per_pixel = 24, .mode = { - .pixel_clock = 159834, + .pixel_clock = 159916, .lvds_dual_channel = 0, .refresh = 60, - .ha = 1200, .hbl = 164, .hso = 114, .hspw = 10, - .va = 1920, .vbl = 33, .vso = 19, .vspw = 4, + .ha = 1200, .hbl = 164, .hso = 80, .hspw = 24, + .va = 1920, .vbl = 34, .vso = 20, .vspw = 4, .phsync = '-', .pvsync = '-', .x_mm = 135, .y_mm = 216, }, -- To view, visit https://review.coreboot.org/c/coreboot/+/38401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9e2cc90f233e87d712c2dc6f4441ca2e5423162 Gerrit-Change-Number: 38401 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

6 9

Change in coreboot[master]: soc/mediatek/mt8183: reduce the hbp and hfp for phy timing
by jitao shi (Code Review) 17 Feb '20

17 Feb '20

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38400 ) Change subject: soc/mediatek/mt8183: reduce the hbp and hfp for phy timing ...................................................................... soc/mediatek/mt8183: reduce the hbp and hfp for phy timing There are some extra data transfer in dsi. ex. LPX, hs_prepare, hs_zero, hs_exit and the sof/eof of dsi packet. This signal will enlarge the line time. So the real frame on dsi bus will be lower than calc by video timing. So dsi driver reduces the hbp and hfp to keep the line time. Change-Id: I10a4d8a4fb41c309fa1917cf1cdf19dabed98227 Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> --- M src/soc/mediatek/common/dsi.c 1 file changed, 22 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/38400/1 diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 238b1eb..66bc6b6 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -73,30 +73,28 @@ static void mtk_dsi_phy_timing(int data_rate, struct mtk_phy_timing *phy_timing) { - u32 cycle_time, ui; - - ui = 1000 / data_rate + 0x01; - cycle_time = 8000 / data_rate + 0x01; + u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000); memset(phy_timing, 0, sizeof(*phy_timing)); - phy_timing->lpx = DIV_ROUND_UP(60, cycle_time); - phy_timing->da_hs_prepare = DIV_ROUND_UP((50 + 5 * ui), cycle_time); - phy_timing->da_hs_zero = DIV_ROUND_UP((110 + 6 * ui), cycle_time); - phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 77), cycle_time); + phy_timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; + phy_timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000; + phy_timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 - + phy_timing->da_hs_prepare + 1; + phy_timing->da_hs_trail = phy_timing->da_hs_prepare + 1; - phy_timing->ta_go = 4U * phy_timing->lpx; - phy_timing->ta_sure = 3U * phy_timing->lpx / 2U; - phy_timing->ta_get = 5U * phy_timing->lpx; - phy_timing->da_hs_exit = 2U * phy_timing->lpx; + phy_timing->ta_go = 4 * phy_timing->lpx - 2; + phy_timing->ta_sure = phy_timing->lpx + 2; + phy_timing->ta_get = 4 * phy_timing->lpx; + phy_timing->da_hs_exit = 2 * phy_timing->lpx + 1; phy_timing->da_hs_sync = 1; - phy_timing->clk_hs_zero = DIV_ROUND_UP(0x150U, cycle_time); - phy_timing->clk_hs_trail = DIV_ROUND_UP(0x64U, cycle_time) + 0xaU; + phy_timing->clk_hs_zero = phy_timing->clk_hs_trail * 4; + phy_timing->clk_hs_trail = phy_timing->clk_hs_prepare; - phy_timing->clk_hs_prepare = DIV_ROUND_UP(0x40U, cycle_time); - phy_timing->clk_hs_post = DIV_ROUND_UP(80U + 52U * ui, cycle_time); - phy_timing->clk_hs_exit = 2U * phy_timing->lpx; + phy_timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000); + phy_timing->clk_hs_post = phy_timing->clk_hs_prepare + 8; + phy_timing->clk_hs_exit = 2 * phy_timing->clk_hs_trail; /* Allow board-specific tuning. */ mtk_dsi_override_phy_timing(phy_timing); @@ -200,12 +198,12 @@ hspw = edid->mode.hspw; hbp_byte = (edid->mode.hbl - edid->mode.hso - hspw - edid->mode.hborder) - * bytes_per_pixel - 10; + * bytes_per_pixel - 10; hsync_active_byte = edid->mode.hspw * bytes_per_pixel - 10; hfp_byte = (edid->mode.hso - edid->mode.hborder) * bytes_per_pixel; data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare + - phy_timing->da_hs_zero + phy_timing->da_hs_exit + 2; + phy_timing->da_hs_zero + phy_timing->da_hs_exit + 3; u32 delta = 12; if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) @@ -214,11 +212,13 @@ u32 d_phy = phy_timing->d_phy; if (d_phy == 0) d_phy = data_phy_cycles * lanes + delta; - if (hfp_byte > d_phy) - hfp_byte -= d_phy; - else + if ((hfp_byte + hbp_byte) > d_phy) { + hfp_byte -= (d_phy * hfp_byte) / (hfp_byte + hbp_byte); + hbp_byte -= (d_phy * hbp_byte) / (hfp_byte + hbp_byte); + } else { printk(BIOS_ERR, "HFP is not greater than d-phy, FPS < 60Hz " "and the panel may not work properly.\n"); + } write32(&dsi0->dsi_hsa_wc, hsync_active_byte); write32(&dsi0->dsi_hbp_wc, hbp_byte); -- To view, visit https://review.coreboot.org/c/coreboot/+/38400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10a4d8a4fb41c309fa1917cf1cdf19dabed98227 Gerrit-Change-Number: 38400 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

6 15

Change in coreboot[master]: dsi: Fix data rate
by Yu-Ping Wu (Code Review) 17 Feb '20

17 Feb '20

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38827 ) Change subject: dsi: Fix data rate ...................................................................... dsi: Fix data rate Change-Id: I23220d446833b956431006027bbc8cb20fc696a5 --- M src/soc/mediatek/common/dsi.c 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/38827/1 diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 238b1eb..618a2d4 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -48,9 +48,11 @@ * for older platforms which do not have complete implementation in HFP. * Newer platforms should just set that to 1.0 (100 / 100). */ - int data_rate = (u64)edid->mode.pixel_clock * bits_per_pixel * - MTK_DSI_MIPI_RATIO_NUMERATOR / - (1000 * lanes * MTK_DSI_MIPI_RATIO_DENOMINATOR); + int data_rate = DIV_ROUND_UP((u64)edid->mode.pixel_clock * + bits_per_pixel * + MTK_DSI_MIPI_RATIO_NUMERATOR, + 1000ULL * lanes * + MTK_DSI_MIPI_RATIO_DENOMINATOR); printk(BIOS_INFO, "DSI data_rate: %d Mbps\n", data_rate); if (data_rate < MTK_DSI_DATA_RATE_MIN_MHZ) { -- To view, visit https://review.coreboot.org/c/coreboot/+/38827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23220d446833b956431006027bbc8cb20fc696a5 Gerrit-Change-Number: 38827 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: mb/google/kukui: Add panel for Kakadu
by Casper Chang (Code Review) 17 Feb '20

17 Feb '20

Casper Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38822 ) Change subject: mb/google/kukui: Add panel for Kakadu ...................................................................... mb/google/kukui: Add panel for Kakadu Declare the following panel for Kakadu: - BOE_TV105WUM_NW0 BUG=b:148997748 TEST=build Kakadu image passed Change-Id: I394b8cafa8be40e5fd6bf8ceb81b520df73718a4 --- M src/mainboard/google/kukui/Makefile.inc A src/mainboard/google/kukui/panel_kakadu.c M src/mainboard/google/kukui/panel_params/Makefile.inc A src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c 4 files changed, 363 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/38822/1 diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index 7839422..a2a147c 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -26,6 +26,7 @@ ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-$(CONFIG_BOARD_GOOGLE_FLAPJACK) += panel_flapjack.c +ramstage-$(CONFIG_BOARD_GOOGLE_KAKADU) += panel_kakadu.c ramstage-$(CONFIG_BOARD_GOOGLE_KODAMA) += panel_kodama.c ramstage-$(CONFIG_BOARD_GOOGLE_KRANE) += panel_krane.c ramstage-$(CONFIG_BOARD_GOOGLE_KUKUI) += panel_kukui.c diff --git a/src/mainboard/google/kukui/panel_kakadu.c b/src/mainboard/google/kukui/panel_kakadu.c new file mode 100644 index 0000000..55eb377 --- /dev/null +++ b/src/mainboard/google/kukui/panel_kakadu.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Bitland Tech Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "panel.h" + +static struct panel_description kakadu_panels[] = { + [1] = { .name = "BOE_TV105WUM-NW0", }, +}; + +struct panel_description *get_panel_description(int panel_id) +{ + if (panel_id < 0 || panel_id >= ARRAY_SIZE(kakadu_panels)) + return NULL; + + return get_panel_from_cbfs(&kakadu_panels[panel_id]); +} diff --git a/src/mainboard/google/kukui/panel_params/Makefile.inc b/src/mainboard/google/kukui/panel_params/Makefile.inc index 016dad0..3bd605d 100644 --- a/src/mainboard/google/kukui/panel_params/Makefile.inc +++ b/src/mainboard/google/kukui/panel_params/Makefile.inc @@ -3,6 +3,7 @@ panel-params-$(CONFIG_BOARD_GOOGLE_KRANE) += panel-BOE_TV101WUM_NL6 panel-params-$(CONFIG_BOARD_GOOGLE_KODAMA) += panel-AUO_B101UAN08_3 panel-params-$(CONFIG_BOARD_GOOGLE_KODAMA) += panel-BOE_TV101WUM_N53 +panel-params-$(CONFIG_BOARD_GOOGLE_KAKADU) += panel-BOE_TV105WUM_NW0 panel-params-$(CONFIG_BOARD_GOOGLE_KUKUI) += panel-CMN_P097PFG_SSD2858 panel-params-$(CONFIG_BOARD_GOOGLE_FLAPJACK) += panel-AUO_NT51021D8P panel-params-$(CONFIG_BOARD_GOOGLE_FLAPJACK) += panel-BOE_TV080WUM_NG0 diff --git a/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c b/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c new file mode 100644 index 0000000..1f03fb9 --- /dev/null +++ b/src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c @@ -0,0 +1,333 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Huaqin Telecom Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../panel.h" + +struct panel_serializable_data BOE_TV105WUM_NW0 = { + .edid = { + .ascii_string = "TV105WUM-NW0", + .manufacturer_name = "BOE", + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .pixel_clock = 159261, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 164, .hso = 60, .hspw = 24, + .va = 1920, .vbl = 26, .vso = 14, .vspw = 2, + .phsync = '-', .pvsync = '-', + .x_mm = 147, .y_mm = 236, + }, + }, + .init = { + INIT_DCS_CMD(0x10), + INIT_DELAY_CMD(34), + INIT_DCS_CMD(0xB0, 0x05), + INIT_DCS_CMD(0xB1, 0xE5), + INIT_DCS_CMD(0xB3, 0x52), + INIT_DCS_CMD(0xB0, 0x00), + INIT_DCS_CMD(0xB3, 0x88), + INIT_DCS_CMD(0xB0, 0x04), + INIT_DCS_CMD(0xB8, 0x00), + INIT_DCS_CMD(0xB0, 0x00), + INIT_DCS_CMD(0xB6, 0x03), + INIT_DCS_CMD(0xBA, 0x87), + INIT_DCS_CMD(0xBF, 0x1F), + INIT_DCS_CMD(0xC0, 0x0F), + INIT_DCS_CMD(0xC2, 0x0E), + INIT_DCS_CMD(0xC3, 0x02), + INIT_DCS_CMD(0xC4, 0x0E), + INIT_DCS_CMD(0xC5, 0x02), + INIT_DCS_CMD(0xB0, 0x01), + INIT_DCS_CMD(0xE0, 0x26), + INIT_DCS_CMD(0xE1, 0x26), + INIT_DCS_CMD(0xDC, 0x00), + INIT_DCS_CMD(0xDD, 0x00), + INIT_DCS_CMD(0xCC, 0x26), + INIT_DCS_CMD(0xCD, 0x26), + INIT_DCS_CMD(0xC8, 0x00), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xD2, 0x03), + INIT_DCS_CMD(0xD3, 0x03), + INIT_DCS_CMD(0xE6, 0x04), + INIT_DCS_CMD(0xE7, 0x04), + INIT_DCS_CMD(0xC4, 0x09), + INIT_DCS_CMD(0xC5, 0x09), + INIT_DCS_CMD(0xD8, 0x0A), + INIT_DCS_CMD(0xD9, 0x0A), + INIT_DCS_CMD(0xC2, 0x0B), + INIT_DCS_CMD(0xC3, 0x0B), + INIT_DCS_CMD(0xD6, 0x0C), + INIT_DCS_CMD(0xD7, 0x0C), + INIT_DCS_CMD(0xC0, 0x05), + INIT_DCS_CMD(0xC1, 0x05), + INIT_DCS_CMD(0xD4, 0x06), + INIT_DCS_CMD(0xD5, 0x06), + INIT_DCS_CMD(0xCA, 0x07), + INIT_DCS_CMD(0xCB, 0x07), + INIT_DCS_CMD(0xDE, 0x08), + INIT_DCS_CMD(0xDF, 0x08), + INIT_DCS_CMD(0xB0, 0x02), + INIT_DCS_CMD(0xC0, 0x00), + INIT_DCS_CMD(0xC1, 0x11), + INIT_DCS_CMD(0xC2, 0x1D), + INIT_DCS_CMD(0xC3, 0x2E), + INIT_DCS_CMD(0xC4, 0x3F), + INIT_DCS_CMD(0xC5, 0x3F), + INIT_DCS_CMD(0xC6, 0x3F), + INIT_DCS_CMD(0xC7, 0x3F), + INIT_DCS_CMD(0xC8, 0x3F), + INIT_DCS_CMD(0xC9, 0x3F), + INIT_DCS_CMD(0xCA, 0x3F), + INIT_DCS_CMD(0xCB, 0x3F), + INIT_DCS_CMD(0xCC, 0x3F), + INIT_DCS_CMD(0xCD, 0x33), + INIT_DCS_CMD(0xCE, 0x32), + INIT_DCS_CMD(0xCF, 0x31), + INIT_DCS_CMD(0xD0, 0x07), + INIT_DCS_CMD(0xD2, 0x00), + INIT_DCS_CMD(0xD3, 0x11), + INIT_DCS_CMD(0xD4, 0x1D), + INIT_DCS_CMD(0xD5, 0x2E), + INIT_DCS_CMD(0xD6, 0x3F), + INIT_DCS_CMD(0xD7, 0x3F), + INIT_DCS_CMD(0xD8, 0x3F), + INIT_DCS_CMD(0xD9, 0x3F), + INIT_DCS_CMD(0xDA, 0x3F), + INIT_DCS_CMD(0xDB, 0x3F), + INIT_DCS_CMD(0xDC, 0x3F), + INIT_DCS_CMD(0xDD, 0x3F), + INIT_DCS_CMD(0xDE, 0x3F), + INIT_DCS_CMD(0xDF, 0x33), + INIT_DCS_CMD(0xE0, 0x32), + INIT_DCS_CMD(0xE1, 0x31), + INIT_DCS_CMD(0xE2, 0x07), + INIT_DCS_CMD(0xB0, 0x03), + INIT_DCS_CMD(0xC8, 0x0B), + INIT_DCS_CMD(0xC9, 0x07), + INIT_DCS_CMD(0xC3, 0x00), + INIT_DCS_CMD(0xE7, 0x00), + INIT_DCS_CMD(0xC5, 0x2A), + INIT_DCS_CMD(0xDE, 0x2A), + INIT_DCS_CMD(0xCA, 0x43), + INIT_DCS_CMD(0xC9, 0x07), + INIT_DCS_CMD(0xE4, 0xC0), + INIT_DCS_CMD(0xE5, 0x0D), + INIT_DCS_CMD(0xCB, 0x00), + INIT_DCS_CMD(0xB0, 0x06), + INIT_DCS_CMD(0xB8, 0xA5), + INIT_DCS_CMD(0xC0, 0xA5), + INIT_DCS_CMD(0xC7, 0x0F), + INIT_DCS_CMD(0xD5, 0x32), + INIT_DCS_CMD(0xBC, 0x33), + INIT_DCS_CMD(0xB0, 0x07), + INIT_DCS_CMD(0xB1, 0x00), + INIT_DCS_CMD(0xB2, 0x02), + INIT_DCS_CMD(0xB3, 0x0B), + INIT_DCS_CMD(0xB4, 0x1A), + INIT_DCS_CMD(0xB5, 0x29), + INIT_DCS_CMD(0xB6, 0x38), + INIT_DCS_CMD(0xB7, 0x58), + INIT_DCS_CMD(0xB8, 0x76), + INIT_DCS_CMD(0xB9, 0xB9), + INIT_DCS_CMD(0xBA, 0xF7), + INIT_DCS_CMD(0xBB, 0x6D), + INIT_DCS_CMD(0xBC, 0xE5), + INIT_DCS_CMD(0xBD, 0xE9), + INIT_DCS_CMD(0xBE, 0x5E), + INIT_DCS_CMD(0xBF, 0xD6), + INIT_DCS_CMD(0xC0, 0x15), + INIT_DCS_CMD(0xC1, 0x51), + INIT_DCS_CMD(0xC2, 0x71), + INIT_DCS_CMD(0xC3, 0x90), + INIT_DCS_CMD(0xC4, 0x9C), + INIT_DCS_CMD(0xC5, 0xA8), + INIT_DCS_CMD(0xC6, 0xB5), + INIT_DCS_CMD(0xC7, 0xBC), + INIT_DCS_CMD(0xC8, 0xC0), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x05), + INIT_DCS_CMD(0xCC, 0x6B), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x08), + INIT_DCS_CMD(0xB1, 0x00), + INIT_DCS_CMD(0xB2, 0x04), + INIT_DCS_CMD(0xB3, 0x0B), + INIT_DCS_CMD(0xB4, 0x1A), + INIT_DCS_CMD(0xB5, 0x29), + INIT_DCS_CMD(0xB6, 0x38), + INIT_DCS_CMD(0xB7, 0x58), + INIT_DCS_CMD(0xB8, 0x76), + INIT_DCS_CMD(0xB9, 0xB8), + INIT_DCS_CMD(0xBA, 0xF7), + INIT_DCS_CMD(0xBB, 0x6C), + INIT_DCS_CMD(0xBC, 0xE3), + INIT_DCS_CMD(0xBD, 0xE7), + INIT_DCS_CMD(0xBE, 0x5C), + INIT_DCS_CMD(0xBF, 0xD3), + INIT_DCS_CMD(0xC0, 0x10), + INIT_DCS_CMD(0xC1, 0x4C), + INIT_DCS_CMD(0xC2, 0x6A), + INIT_DCS_CMD(0xC3, 0x8A), + INIT_DCS_CMD(0xC4, 0x96), + INIT_DCS_CMD(0xC5, 0xA2), + INIT_DCS_CMD(0xC6, 0xAE), + INIT_DCS_CMD(0xC7, 0xB4), + INIT_DCS_CMD(0xC8, 0xB8), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x05), + INIT_DCS_CMD(0xCC, 0x6B), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x09), + INIT_DCS_CMD(0xB1, 0x04), + INIT_DCS_CMD(0xB2, 0x04), + INIT_DCS_CMD(0xB3, 0x0C), + INIT_DCS_CMD(0xB4, 0x1C), + INIT_DCS_CMD(0xB5, 0x2D), + INIT_DCS_CMD(0xB6, 0x3C), + INIT_DCS_CMD(0xB7, 0x5F), + INIT_DCS_CMD(0xB8, 0x80), + INIT_DCS_CMD(0xB9, 0xC8), + INIT_DCS_CMD(0xBA, 0x0D), + INIT_DCS_CMD(0xBB, 0x8A), + INIT_DCS_CMD(0xBC, 0x10), + INIT_DCS_CMD(0xBD, 0x14), + INIT_DCS_CMD(0xBE, 0x91), + INIT_DCS_CMD(0xBF, 0x13), + INIT_DCS_CMD(0xC0, 0x53), + INIT_DCS_CMD(0xC1, 0x93), + INIT_DCS_CMD(0xC2, 0xAB), + INIT_DCS_CMD(0xC3, 0xC6), + INIT_DCS_CMD(0xC4, 0xD6), + INIT_DCS_CMD(0xC5, 0xE4), + INIT_DCS_CMD(0xC6, 0xF3), + INIT_DCS_CMD(0xC7, 0xF9), + INIT_DCS_CMD(0xC8, 0xFC), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x0A), + INIT_DCS_CMD(0xB1, 0x00), + INIT_DCS_CMD(0xB2, 0x02), + INIT_DCS_CMD(0xB3, 0x0B), + INIT_DCS_CMD(0xB4, 0x1A), + INIT_DCS_CMD(0xB5, 0x29), + INIT_DCS_CMD(0xB6, 0x38), + INIT_DCS_CMD(0xB7, 0x58), + INIT_DCS_CMD(0xB8, 0x76), + INIT_DCS_CMD(0xB9, 0xB9), + INIT_DCS_CMD(0xBA, 0xF7), + INIT_DCS_CMD(0xBB, 0x6D), + INIT_DCS_CMD(0xBC, 0xE5), + INIT_DCS_CMD(0xBD, 0xE9), + INIT_DCS_CMD(0xBE, 0x5E), + INIT_DCS_CMD(0xBF, 0xD6), + INIT_DCS_CMD(0xC0, 0x15), + INIT_DCS_CMD(0xC1, 0x51), + INIT_DCS_CMD(0xC2, 0x71), + INIT_DCS_CMD(0xC3, 0x90), + INIT_DCS_CMD(0xC4, 0x9C), + INIT_DCS_CMD(0xC5, 0xA8), + INIT_DCS_CMD(0xC6, 0xB5), + INIT_DCS_CMD(0xC7, 0xBC), + INIT_DCS_CMD(0xC8, 0xC0), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x05), + INIT_DCS_CMD(0xCC, 0x6B), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x0B), + INIT_DCS_CMD(0xB1, 0x00), + INIT_DCS_CMD(0xB2, 0x04), + INIT_DCS_CMD(0xB3, 0x0B), + INIT_DCS_CMD(0xB4, 0x1A), + INIT_DCS_CMD(0xB5, 0x29), + INIT_DCS_CMD(0xB6, 0x38), + INIT_DCS_CMD(0xB7, 0x58), + INIT_DCS_CMD(0xB8, 0x76), + INIT_DCS_CMD(0xB9, 0xB8), + INIT_DCS_CMD(0xBA, 0xF7), + INIT_DCS_CMD(0xBB, 0x6C), + INIT_DCS_CMD(0xBC, 0xE3), + INIT_DCS_CMD(0xBD, 0xE7), + INIT_DCS_CMD(0xBE, 0x5C), + INIT_DCS_CMD(0xBF, 0xD3), + INIT_DCS_CMD(0xC0, 0x10), + INIT_DCS_CMD(0xC1, 0x4C), + INIT_DCS_CMD(0xC2, 0x6A), + INIT_DCS_CMD(0xC3, 0x8A), + INIT_DCS_CMD(0xC4, 0x96), + INIT_DCS_CMD(0xC5, 0xA2), + INIT_DCS_CMD(0xC6, 0xAE), + INIT_DCS_CMD(0xC7, 0xB4), + INIT_DCS_CMD(0xC8, 0xB8), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x05), + INIT_DCS_CMD(0xCC, 0x6B), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DCS_CMD(0xB0, 0x0C), + INIT_DCS_CMD(0xB1, 0x04), + INIT_DCS_CMD(0xB2, 0x04), + INIT_DCS_CMD(0xB3, 0x0C), + INIT_DCS_CMD(0xB4, 0x1C), + INIT_DCS_CMD(0xB5, 0x2D), + INIT_DCS_CMD(0xB6, 0x3C), + INIT_DCS_CMD(0xB7, 0x5F), + INIT_DCS_CMD(0xB8, 0x80), + INIT_DCS_CMD(0xB9, 0xC8), + INIT_DCS_CMD(0xBA, 0x0D), + INIT_DCS_CMD(0xBB, 0x8A), + INIT_DCS_CMD(0xBC, 0x10), + INIT_DCS_CMD(0xBD, 0x14), + INIT_DCS_CMD(0xBE, 0x91), + INIT_DCS_CMD(0xBF, 0x13), + INIT_DCS_CMD(0xC0, 0x53), + INIT_DCS_CMD(0xC1, 0x93), + INIT_DCS_CMD(0xC2, 0xAB), + INIT_DCS_CMD(0xC3, 0xC6), + INIT_DCS_CMD(0xC4, 0xD6), + INIT_DCS_CMD(0xC5, 0xE4), + INIT_DCS_CMD(0xC6, 0xF3), + INIT_DCS_CMD(0xC7, 0xF9), + INIT_DCS_CMD(0xC8, 0xFC), + INIT_DCS_CMD(0xC9, 0x00), + INIT_DCS_CMD(0xCA, 0x00), + INIT_DCS_CMD(0xCB, 0x16), + INIT_DCS_CMD(0xCC, 0xAF), + INIT_DCS_CMD(0xCD, 0xFF), + INIT_DCS_CMD(0xCE, 0xFF), + INIT_DELAY_CMD(100), + INIT_DCS_CMD(0xB0, 0x00), + INIT_DCS_CMD(0xB3, 0x08), + INIT_DCS_CMD(0xB0, 0x04), + INIT_DCS_CMD(0xB8, 0x68), + INIT_DELAY_CMD(10), + INIT_DCS_CMD(0x11), + INIT_DELAY_CMD(100), + INIT_DCS_CMD(0x29), + INIT_DELAY_CMD(50), + INIT_END_CMD, + }, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/38822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I394b8cafa8be40e5fd6bf8ceb81b520df73718a4 Gerrit-Change-Number: 38822 Gerrit-PatchSet: 1 Gerrit-Owner: Casper Chang <casper.chang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

5 22

Change in coreboot[master]: soc/common: Add Device id for Tigerlake Dual Core
by Srinidhi N Kaushik (Code Review) 17 Feb '20

17 Feb '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38774 ) Change subject: soc/common: Add Device id for Tigerlake Dual Core ...................................................................... soc/common: Add Device id for Tigerlake Dual Core Add device id for Tigerlake Dual core part. BUG=b:148965583 BRANCH=none TEST="emerge-tglrvp coreboot chromeos-bootimage", flash and boot Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: Ied0cef2fcc8ae6f25949f98f886c4d79f64b54cd --- M src/include/device/pci_ids.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/tigerlake/bootblock/report_platform.c 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/38774/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index e117ac2..7434cf1 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3444,6 +3444,7 @@ #define PCI_DEVICE_ID_INTEL_CML_H_4_2 0x9B64 #define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44 #define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14 +#define PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2 0x9A04 #define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12 #define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A10 #define PCI_DEVICE_ID_INTEL_JSL_PRE_PROD 0x4e2a diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 4c7d8c8..59076fc 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -397,6 +397,7 @@ PCI_DEVICE_ID_INTEL_CML_H_4_2, PCI_DEVICE_ID_INTEL_CML_H_8_2, PCI_DEVICE_ID_INTEL_TGL_ID_U, + PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, PCI_DEVICE_ID_INTEL_TGL_ID_U_1, PCI_DEVICE_ID_INTEL_TGL_ID_Y, PCI_DEVICE_ID_INTEL_JSL_PRE_PROD, diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index 127994d..f38e9cf 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -46,6 +46,7 @@ } mch_table[] = { { PCI_DEVICE_ID_INTEL_TGL_ID_U, "Tigerlake-U-4-2" }, { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" }, + { PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, "Tigerlake-U-2-2" }, { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" }, { PCI_DEVICE_ID_INTEL_JSL_PRE_PROD, "Jasperlake Pre Prod" }, { PCI_DEVICE_ID_INTEL_JSL_EHL, "Jasperlake Elkhartlake" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/38774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied0cef2fcc8ae6f25949f98f886c4d79f64b54cd Gerrit-Change-Number: 38774 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-MessageType: newchange

6 20

Change in coreboot[master]: mb/google/octopus: Add custom SAR values for Bipship
by Tony Huang (Code Review) 17 Feb '20

17 Feb '20

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38859 ) Change subject: mb/google/octopus: Add custom SAR values for Bipship ...................................................................... mb/google/octopus: Add custom SAR values for Bipship Bipship is a sustaining project of Blooguard. SAR value follow Blooguard. BUG=b:149414960 BRANCH=octopus TEST=build and verify load correct SAR value by sku-id Change-Id: Ic45ed10fc147401d4278f1811a86cd2b2e4c63ac Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/bloog/variant.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/38859/1 diff --git a/src/mainboard/google/octopus/variants/bloog/variant.c b/src/mainboard/google/octopus/variants/bloog/variant.c index 699385e..6c85e50 100644 --- a/src/mainboard/google/octopus/variants/bloog/variant.c +++ b/src/mainboard/google/octopus/variants/bloog/variant.c @@ -55,6 +55,8 @@ case SKU_50_BLOOGUARD: case SKU_51_BLOOGUARD: case SKU_52_BLOOGUARD: + case SKU_53_BIPSHIP: + case SKU_54_BIPSHIP: filename = "wifi_sar-blooguard.hex"; break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/38859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic45ed10fc147401d4278f1811a86cd2b2e4c63ac Gerrit-Change-Number: 38859 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/google/dedede: Configure I2C ports
by Karthik Ramasubramanian (Code Review) 17 Feb '20

17 Feb '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38847 ) Change subject: mb/google/dedede: Configure I2C ports ...................................................................... mb/google/dedede: Configure I2C ports Enable I2C ports that are used. Add GPIO configuration for the I2C ports. Enable config items that are required for I2C HID & Generic devices. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I12e974530fb5f61fae5d12cadbb3f928e617d73a --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c 3 files changed, 53 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38847/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index c2f66a4..a3d189d 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -1,5 +1,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE def_bool n + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID select DRIVERS_SPI_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 4b2a3c5..2d57a14 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -20,11 +20,11 @@ register "pmc_gpe0_dw2" = "GPP_H" register "SerialIoI2cMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, [PchSerialIoIndexI2C5] = PchSerialIoDisabled, }" @@ -60,12 +60,32 @@ #| | required to set up a BAR | #| | for TPM communication | #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ .gspi[0] = { .speed_mhz = 1, .early_init = 1, }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, }" device domain 0 on @@ -80,16 +100,16 @@ device pci 14.2 off end # PMC SRAM device pci 14.3 off end # CNVi wifi device pci 14.5 off end # SDCard - device pci 15.0 off end # I2C 0 - device pci 15.1 off end # I2C 1 - device pci 15.2 off end # I2C 2 - device pci 15.3 off end # I2C 3 + device pci 15.0 on end # I2C 0 + device pci 15.1 on end # I2C 1 + device pci 15.2 on end # I2C 2 + device pci 15.3 on end # I2C 3 device pci 16.0 off end # HECI 1 device pci 16.1 off end # HECI 2 device pci 16.4 off end # HECI 3 device pci 16.5 off end # HECI 4 device pci 17.0 off end # SATA - device pci 19.0 off end # I2C 4 + device pci 19.0 on end # I2C 4 device pci 19.1 off end # I2C 5 device pci 19.2 on end # UART 2 device pci 1a.0 off end # eMMC diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index c334f11..8e4200a 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -33,6 +33,14 @@ /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C16 : AP_I2C_TRACKPAD_SDA_3V3 */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : AP_I2C_TRACKPAD_SCL_3V3 */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : AP_I2C_EMR_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : AP_I2C_EMR_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* C20 : UART_DBG_TX_AP_RX */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* C21 : UART_AP_TX_DBG_RX */ @@ -41,6 +49,19 @@ PAD_NC(GPP_C22, DN_20K), /* C23 : UART2_CTS_N */ PAD_NC(GPP_C23, DN_20K), + + /* H4 : AP_I2C_TS_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : AP_I2C_TS_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H6 : AP_I2C_CAM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : AP_I2C_CAM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : AP_I2C_AUDIO_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* H9 : AP_I2C_AUDIO_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), }; /* Early pad configuration in bootblock */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12e974530fb5f61fae5d12cadbb3f928e617d73a Gerrit-Change-Number: 38847 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Enable AP <-> H1 Communication
by Karthik Ramasubramanian (Code Review) 17 Feb '20

17 Feb '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38772 ) Change subject: mb/google/dedede: Enable AP <-> H1 Communication ...................................................................... mb/google/dedede: Enable AP <-> H1 Communication Turn on the H1 device in the devicetree. Configure the concerned GPIOs and enable the required config items. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I37972635454cd0d35608623e7be4110012ace658 --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c 3 files changed, 54 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/38772/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 5254d16..9b5bd4a 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -1,11 +1,14 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE def_bool n + select DRIVERS_SPI_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_SPI_TPM_CR50 + select MAINBOARD_HAS_TPM2 select SOC_INTEL_JASPERLAKE if BOARD_GOOGLE_BASEBOARD_DEDEDE @@ -25,6 +28,9 @@ string default "variants/baseboard/devicetree.cb" +config DRIVER_TPM_SPI_BUS + default 0x1 + config MAINBOARD_DIR string default "google/dedede" @@ -41,6 +47,10 @@ int default 4 +config TPM_TIS_ACPI_INTERRUPT + int + default 4 # GPE0_DW0_4 (GPP_B4) + config UART_FOR_CONSOLE int default 2 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 44d9ca2..0cf696c 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -19,6 +19,22 @@ register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_H" + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + }" + device domain 0 on device pci 00.0 off end # Host Bridge device pci 02.0 off end # Integrated Graphics Device @@ -54,7 +70,14 @@ device pci 1c.7 off end # PCI Express Root Port 8 device pci 1e.0 off end # UART 0 device pci 1e.1 off end # UART 1 - device pci 1e.2 off end # GSPI 0 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B4_IRQ)" + device spi 0 on end + end + end # GSPI 0 device pci 1e.3 off end # GSPI 1 device pci 1f.0 on chip ec/google/chromeec diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 0908412..fc63ffe 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -21,11 +21,30 @@ /* A4 : ESPI_CS# */ /* A5 : ESPI_CLK */ /* A6 : ESPI_RESET_L */ + /* B4 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - /* ToDo: Fill early gpio configuration */ + /* B4 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), }; const struct pad_config *__weak variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/38772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37972635454cd0d35608623e7be4110012ace658 Gerrit-Change-Number: 38772 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: cpu/x86: Remove unnecessary guard.
by Name of user not set (Code Review) 17 Feb '20

17 Feb '20

cedarhouse1(a)comcast.net has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38820 ) Change subject: cpu/x86: Remove unnecessary guard. ...................................................................... cpu/x86: Remove unnecessary guard. The is_smm_enabled is not necessary because it is done previously in this code path. Signed-off-by: Eugene D. Myers <edmyers(a)tycho.nsa.gov> Change-Id: I20d50acbea891cb56ad49edc128df25d21c5f1ca --- M src/cpu/x86/mp_init.c 1 file changed, 7 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/38820/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 5169861..6082df9 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -747,20 +747,15 @@ mp_state.ops.relocation_handler(cpu, curr_smbase, perm_smbase); if (CONFIG(STM)) { - if (is_smm_enabled()) { - uintptr_t mseg; + uintptr_t mseg; - mseg = mp_state.perm_smbase + - (mp_state.perm_smsize - CONFIG_MSEG_SIZE); + mseg = mp_state.perm_smbase + + (mp_state.perm_smsize - CONFIG_MSEG_SIZE); - stm_setup(mseg, p->cpu, runtime->num_cpus, - perm_smbase, - mp_state.perm_smbase, - runtime->start32_offset); - } else { - printk(BIOS_DEBUG, - "STM not loaded because SMM is not enabled!\n"); - } + stm_setup(mseg, p->cpu, runtime->num_cpus, + perm_smbase, + mp_state.perm_smbase, + runtime->start32_offset); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/38820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20d50acbea891cb56ad49edc128df25d21c5f1ca Gerrit-Change-Number: 38820 Gerrit-PatchSet: 1 Gerrit-Owner: cedarhouse1(a)comcast.net Gerrit-MessageType: newchange

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