coreboot-gerrit February 2020

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Change in coreboot[master]: src/cpu/x86: Adjust STM smm_save_state_size
by Name of user not set (Code Review) 17 Feb '20

17 Feb '20

cedarhouse1(a)comcast.net has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38819 ) Change subject: src/cpu/x86: Adjust STM smm_save_state_size ...................................................................... src/cpu/x86: Adjust STM smm_save_state_size Initial testing of STM support revealed a sizing issue for greater than 4 threads. This patch reduces the STM smm_save_state_size, which should allow for 24 threads. Signed-off-by: Eugene D. Myers <edmyers(a)tycho.nsa.gov> Change-Id: I025694185469577e072a92ea75cbbb53c24b2c24 --- M src/cpu/x86/mp_init.c 1 file changed, 1 insertion(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/38819/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index c747207..5169861 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -1046,19 +1046,7 @@ */ if (CONFIG(STM)) { state->smm_save_state_size += - sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR); - - /* Currently, the CPU SMM save state size is based on a simplistic - * algorithm. (align on 4K) - * note: In the future, this will need to handle newer x86 processors - * that require alignment of the save state on 32K boundaries. - * The alignment is done here because coreboot has a hard coded - * value of 0x400 for this value. - * Also, this alignment only works on CPUs less than 5 threads - */ - if (CONFIG(STM)) - state->smm_save_state_size = - ALIGN_UP(state->smm_save_state_size, 0x1000); + ALIGN_UP(sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR), 0x100); } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/38819 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I025694185469577e072a92ea75cbbb53c24b2c24 Gerrit-Change-Number: 38819 Gerrit-PatchSet: 1 Gerrit-Owner: cedarhouse1(a)comcast.net Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/purism/librem: Add ACPI temp reporting
by Matt DeVillier (Code Review) 17 Feb '20

17 Feb '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38835 ) Change subject: ec/purism/librem: Add ACPI temp reporting ...................................................................... ec/purism/librem: Add ACPI temp reporting Add EC ACPI reporting of current temp and platform critical temp. Adapted from ACPI dump of ODM AMI firmware. TEST: check reporting of current/critical temps via lm-sensors from ACPI on Librem 13v1 and 13v4 boards. Change-Id: I92641fbbdda46e0c388607a37f7a7cc2dcd6c26d Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/ec/purism/librem/acpi/ec.asl M src/mainboard/purism/librem_bdw/acpi/ec.asl M src/mainboard/purism/librem_skl/acpi/ec.asl 3 files changed, 25 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/38835/1 diff --git a/src/ec/purism/librem/acpi/ec.asl b/src/ec/purism/librem/acpi/ec.asl index ff325aa..6f6ced1 100644 --- a/src/ec/purism/librem/acpi/ec.asl +++ b/src/ec/purism/librem/acpi/ec.asl @@ -52,7 +52,9 @@ OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF) Field (ERAM, ByteAcc, Lock, Preserve) { - Offset (0x15), + Offset (0x13), + RTMP, 8, + , 8, BSTS, 2, /* Battery Status */ , 3, BTEX, 1, /* Battery Present */ @@ -231,3 +233,23 @@ #include "ac.asl" #include "battery.asl" } + +Scope (\_TZ) +{ + ThermalZone (TZ0) + { + /* _TMP: Temperature */ + Method (_TMP, 0, Serialized) + { + Local0 = (0x0AAC + (\_SB.PCI0.LPCB.EC.RTMP * 0x0A)) + Return (Local0) + } + + /* _CRT: Critical Temperature */ + Method (_CRT, 0, Serialized) + { + /* defined in board ec.asl */ + Return (CRIT_TEMP) + } + } +} diff --git a/src/mainboard/purism/librem_bdw/acpi/ec.asl b/src/mainboard/purism/librem_bdw/acpi/ec.asl index b2fa5b9..a660a52 100644 --- a/src/mainboard/purism/librem_bdw/acpi/ec.asl +++ b/src/mainboard/purism/librem_bdw/acpi/ec.asl @@ -16,5 +16,6 @@ #define EC_SCI_GPI 10 #define PPCM_TURBO Zero #define PPCM_NOTURBO One +#define CRIT_TEMP 105 #include <ec/purism/librem/acpi/ec.asl> diff --git a/src/mainboard/purism/librem_skl/acpi/ec.asl b/src/mainboard/purism/librem_skl/acpi/ec.asl index c667b6c..c440ff8 100644 --- a/src/mainboard/purism/librem_skl/acpi/ec.asl +++ b/src/mainboard/purism/librem_skl/acpi/ec.asl @@ -16,5 +16,6 @@ #define EC_SCI_GPI 0x50 #define PPCM_TURBO One #define PPCM_NOTURBO 0x02 +#define CRIT_TEMP 100 #include <ec/purism/librem/acpi/ec.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/38835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92641fbbdda46e0c388607a37f7a7cc2dcd6c26d Gerrit-Change-Number: 38835 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Revert "mb/google/hatch: Override CPU flex ratio"
by Tim Wawrzynczak (Code Review) 17 Feb '20

17 Feb '20

Hello Pratikkumar V Prajapati, Subrata Banik, Tim Wawrzynczak, Shelley Chen, V Sowmya, build bot (Jenkins), Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38324 to review the following change. Change subject: Revert "mb/google/hatch: Override CPU flex ratio" ...................................................................... Revert "mb/google/hatch: Override CPU flex ratio" This reverts commit a017e5fb3dda5ea6bbc94ee15b2e981eeaa2d918. Reason for revert: The extra reset in the FSP after the flex ratio is changed causes recovery reasons to be lost. There are some vboot changes that recently landed that could help with this issue, but for now, we are working on a new AU image for Kohaku and this is causing our automated testing to fail. Change-Id: Ic38b390842e2a533033587b3247b7c8d982b1dff --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38324/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index e0291bb..b4d7afd 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -194,9 +194,6 @@ register "gpio_pm[COMM_3]" = "0" register "gpio_pm[COMM_4]" = "0" - # CPU Ratio Override - register "cpu_ratio_override" = "15" - # chipset_lockdown configuration # Use below format to override value in overridetree.cb if required # format: -- To view, visit https://review.coreboot.org/c/coreboot/+/38324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic38b390842e2a533033587b3247b7c8d982b1dff Gerrit-Change-Number: 38324 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774 u...
by Wim Vervoorn (Code Review) 17 Feb '20

17 Feb '20

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38747 ) Change subject: soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774 update ...................................................................... soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774 update Make sure the Skylake comment refers to the correct BWG paragraph and update the text for all. BUG=N/A TEST=build Change-Id: Id383f200e079bdb91cea2240bd7a957d723a7b89 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/tigerlake/bootblock/pch.c 4 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38747/1 diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index e7b79a0..eca28b3 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -168,8 +168,8 @@ if (pch_check_decode_enable() == 0) { io_enables = lpc_enable_fixed_io_ranges(io_enables); /* - * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same - * value program in LPC PCI offset 82h. + * Set LPC IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in LPC PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); /* diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index b1309a4..f51ecab 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -140,8 +140,8 @@ if (pch_check_decode_enable() == 0) { io_enables = lpc_enable_fixed_io_ranges(io_enables); /* - * Set up ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same - * value program in ESPI PCI offset 82h. + * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in ESPI PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); /* diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 7763cf0..d5d3aed 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -135,9 +135,9 @@ if (pch_check_decode_enable() == 0) { io_enables = lpc_enable_fixed_io_ranges(io_enables); /* - * As per PCH BWG 2.5.16. - * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same - * value program in LPC PCI offset 82h. + * As per PCH BWG 2.5.1.6. + * Set LPC IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in LPC PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); /* diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 8a132ce..ccdeadc 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -165,8 +165,8 @@ if (pch_check_decode_enable() == 0) { io_enables = lpc_enable_fixed_io_ranges(io_enables); /* - * Set up ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same - * value program in ESPI PCI offset 82h. + * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in ESPI PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); /* -- To view, visit https://review.coreboot.org/c/coreboot/+/38747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id383f200e079bdb91cea2240bd7a957d723a7b89 Gerrit-Change-Number: 38747 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel{cnl,icl,skl,tgl}\bootblock: Make sure DMI PCR 2770 is set
by Wim Vervoorn (Code Review) 17 Feb '20

17 Feb '20

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38746 ) Change subject: soc/intel{cnl,icl,skl,tgl}\bootblock: Make sure DMI PCR 2770 is set ...................................................................... soc/intel{cnl,icl,skl,tgl}\bootblock: Make sure DMI PCR 2770 is set DMI PCR 2770 (LPC IO DECODE RANGES) should be identical to LPC PCI offset 0x80. This is specified in PCH BWG par 2.5.1.5. Add the support to make sure this PCR is always set correctly. BUG=N/A TEST=tested on facebook monolith. Change-Id: I33ff2b96dea78b5ff1c7c9416cf74f67d79f265d Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/tigerlake/bootblock/pch.c 4 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/38746/1 diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index a6e9f9d..e7b79a0 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -172,6 +172,11 @@ * value program in LPC PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); + /* + * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same + * value programmed in LPC PCI offset 80h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); } /* Program generic IO Decode Range */ diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index fd2ffd2..b1309a4 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -144,6 +144,11 @@ * value program in ESPI PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); + /* + * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same + * value programmed in LPC PCI offset 80h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); } /* Program generic IO Decode Range */ diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index ddf1139..7763cf0 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -140,6 +140,12 @@ * value program in LPC PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); + /* + * As per PCH BWG 2.5.1.5. + * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same + * value programmed in LPC PCI offset 80h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); } /* Program generic IO Decode Range */ diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 1654809..8a132ce 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -169,6 +169,11 @@ * value program in ESPI PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); + /* + * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same + * value programmed in LPC PCI offset 80h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); } /* Program generic IO Decode Range */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33ff2b96dea78b5ff1c7c9416cf74f67d79f265d Gerrit-Change-Number: 38746 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/lpc: create LPC_GET_DEV macro
by Nico Huber (Code Review) 17 Feb '20

17 Feb '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30209 ) Change subject: soc/intel/common/block/lpc: create LPC_GET_DEV macro ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/30209/2/src/soc/intel/common/block… File src/soc/intel/common/block/lpc/lpc_lib.c: https://review.coreboot.org/c/coreboot/+/30209/2/src/soc/intel/common/block… PS2, Line 29: #if !defined(__SIMPLE_DEVICE__) : #include <device/device.h> : #define LPC_GET_DEV pcidev_on_root(PCH_DEV_SLOT_LPC, 0x0) : #else : #define LPC_GET_DEV PCH_DEV_LPC : #endif > > > > Compiles fine as by Aamir's suggestion, btw. > > > > > > yes compilation will work as long as #define __SIMPLE_DEVICE__ is there. > > > > No, I meant this patch but with PCH_DEV_LPC from soc/pci_devs.h instead > > of your new macro works fine. > > Do you mean PCH_DEV_LPC from soc/pci_devs.h will work without having #define __SIMPLE_DEVICE__ at line 18? Yes, if you do the same, related modifications below, i.e. remove the pci_devfn_t declarations. > > > > > > > > > But i don't know why we have this guard at first place and want to compile this entire file as part of simple device. is that saving anything ? general query. > > > > It provides a stable API even if the file is compiled for ramstage and > > pre-ram stages. > > Intention is not to break the stability here for sure, just wondering if you have real reason why #define __SIMPLE_DEVICE__ been added at first place ? Let me rephrase: If we #define __SIMPLE_DEVICE__ on top of a .c file. All included headers will behave the same, no matter if we compile for ramstage or not. That's what I called `stable API`. The same API for ramstage and others. If we don't #define __SIMPLE_DEVICE__ explicitly, it's still defined by the build system for pre-ram stages. Then the #if in header files apply in one way or the other depending on if we build for ramstage or not. This was originally intended for the headers files in src/ include/device/. So, the explicit define (as it was done here) makes it easier to compile the same .c file for both ramstage and pre-ram stages _without_ further tricks (like #if in include/soc/pci_def.h). It makes, however, usage of `struct device` harder. The way include/soc/pci_def.h does it, with the #if, has led to many errors in the past (mostly due to missing null-checks). Hence, I call it discouraged. > > > Hence, avoids the need for any #if in platform code. > > FYI, this is soc code not the platform code. hatch, poppy are the platform code in my understanding. this is soc library. i was adhering old review comments from Arthur who has suggested to have a macro rather function names. Sorry, I don't know how you call things. To me, a platform in this context is chipset + CPU. What I actually meant is #if outside of src/include/device/. About Arthur's comments, they were for patch set 1 which looks much differently. Also, the original problem patch set 1 tried to solve was fixed in the meantime. There was #ifdef __SIMPLE_DEVICE__ pci_devfn_t dev; #else struct device *dev; #endif earlier, but isn't anymore. Which explains the commit message, maybe. Maybe let's back up and start with the problem you are trying to solve? Is there anything you want to add to / change in this file that isn't possible because of the `#define __SIMPLE_DEVICE__`? > > > because you can't use them anymore to get a `struct device *`. That's > > why there are some explicit calls to pcidev_on_root() below. > > yes, that's the point. this could have been avoided but it has some other assumptions :) about "struct device *" Why avoid it? The code is more explicit this way. It's clear to the reader that a pointer is involved, which makes review and maintenance easier. -- To view, visit https://review.coreboot.org/c/coreboot/+/30209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84a6102bf3849e9d4fe28e4c6a11bc7badcf5114 Gerrit-Change-Number: 30209 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 17 Feb 2020 14:53:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/gm45: Fix typo
by HAOUAS Elyes (Code Review) 17 Feb '20

17 Feb '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38927 ) Change subject: nb/intel/gm45: Fix typo ...................................................................... nb/intel/gm45: Fix typo Change-Id: Ia0d7d5ecf376af97ee54ff3ca536160202e43f79 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/gm45/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/38927/1 diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 5b8d1d8..90dfa92 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1293,7 +1293,7 @@ MCHBAR32(DCC_MCHBAR) &= ~DCC_INTERLEAVED; break; case CHANNEL_MODE_DUAL_ASYNC: - printk(BIOS_DEBUG, "Memory configured in dual-channel assymetric mode.\n"); + printk(BIOS_DEBUG, "Memory configured in dual-channel asymmetric mode.\n"); MCHBAR32(DCC_MCHBAR) &= ~DCC_INTERLEAVED; break; case CHANNEL_MODE_DUAL_INTERLEAVED: -- To view, visit https://review.coreboot.org/c/coreboot/+/38927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0d7d5ecf376af97ee54ff3ca536160202e43f79 Gerrit-Change-Number: 38927 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/nehalem: Remove unused MRC_CACHE_SIZE
by HAOUAS Elyes (Code Review) 17 Feb '20

17 Feb '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38906 ) Change subject: nb/intel/nehalem: Remove unused MRC_CACHE_SIZE ...................................................................... nb/intel/nehalem: Remove unused MRC_CACHE_SIZE Change-Id: I5d00fb238be6399ea6e9f394d8f899b03b1d44cf Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/nehalem/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/38906/1 diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index a119b81..cfd7fe2 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -58,10 +58,6 @@ The amount of anticipated stack usage in CAR by bootblock and other stages. -config MRC_CACHE_SIZE - hex - default 0x10000 - config MMCONF_BASE_ADDRESS hex default 0xe0000000 -- To view, visit https://review.coreboot.org/c/coreboot/+/38906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d00fb238be6399ea6e9f394d8f899b03b1d44cf Gerrit-Change-Number: 38906 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu: Add initial xeonsp support broilerplate
by Angel Pons (Code Review) 17 Feb '20

17 Feb '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38838 ) Change subject: cpu: Add initial xeonsp support broilerplate ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/c/coreboot/+/38838/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38838/2//COMMIT_MSG@7 PS2, Line 7: broilerplate > boilerplate? Very likely. https://review.coreboot.org/c/coreboot/+/38838/2//COMMIT_MSG@9 PS2, Line 9: broilerplate same here https://review.coreboot.org/c/coreboot/+/38838/2//COMMIT_MSG@10 PS2, Line 10: xeonsp Xeon SP Is it Xeon Single Processor or Xeon Scalable Platform? If the latter, I would probably call it "Xeon Scalable", and use "xeon_scalable" -- To view, visit https://review.coreboot.org/c/coreboot/+/38838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24346b8a5c30342419db23b5f1adf27d4d0ebc5f Gerrit-Change-Number: 38838 Gerrit-PatchSet: 2 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 17 Feb 2020 12:23:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu: Add initial xeonsp support broilerplate
by Paul Menzel (Code Review) 17 Feb '20

17 Feb '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38838 ) Change subject: cpu: Add initial xeonsp support broilerplate ...................................................................... Patch Set 2: (4 comments) Please make the spelling in the copyright header consistent, or move to SPDX. https://review.coreboot.org/c/coreboot/+/38838/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38838/2//COMMIT_MSG@7 PS2, Line 7: broilerplate boilerplate? https://review.coreboot.org/c/coreboot/+/38838/2//COMMIT_MSG@14 PS2, Line 14: Change-Id: I24346b8a5c30342419db23b5f1adf27d4d0ebc5f Missing Signed-off-by line. https://review.coreboot.org/c/coreboot/+/38838/2/src/cpu/intel/xeonsp/bootb… File src/cpu/intel/xeonsp/bootblock.c: https://review.coreboot.org/c/coreboot/+/38838/2/src/cpu/intel/xeonsp/bootb… PS2, Line 4: * Copyright (C) 2019 Facebook Inc Inc.? https://review.coreboot.org/c/coreboot/+/38838/2/src/cpu/intel/xeonsp/bootb… PS2, Line 38: {0} Please add spaces around the 0. -- To view, visit https://review.coreboot.org/c/coreboot/+/38838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24346b8a5c30342419db23b5f1adf27d4d0ebc5f Gerrit-Change-Number: 38838 Gerrit-PatchSet: 2 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 17 Feb 2020 12:10:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2020