coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: cpu: Allow to configure microcode at pre-defined address
by Patrick Georgi (Code Review) 18 Feb '20

18 Feb '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38640 ) Change subject: cpu: Allow to configure microcode at pre-defined address ...................................................................... cpu: Allow to configure microcode at pre-defined address FSP-T takes microcode pointer and location parameters, and FSP-T is invoked before CAR is set-up and before memory is trained. So it is not possible to modify supplied microcode pointer in runtime. Because of that we have to hardcode the pointer in bootblock. Also, current FSP-T on Xeons require microcode (it is not optional). Reasons for that are currently unclear and are being investigated. However for the present time we need to be able to add microcode at a certain offset so FSP-T can be used. TEST=test on OCP TiogaPass board, as well as out-of-tree CPU/board Change-Id: I6c02601a7ac64078e556e2032baeccaf27f77da2 Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38640 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/cpu/Makefile.inc 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 4b5d67b..0289be0 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -60,3 +60,7 @@ cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin cpu_microcode_blob.bin-type := microcode cpu_microcode_blob.bin-align := 16 + +ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) +cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) +endif -- To view, visit https://review.coreboot.org/c/coreboot/+/38640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c02601a7ac64078e556e2032baeccaf27f77da2 Gerrit-Change-Number: 38640 Gerrit-PatchSet: 9 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu: Allow to configure microcode at pre-defined address
by Patrick Georgi (Code Review) 18 Feb '20

18 Feb '20

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38640 ) Change subject: cpu: Allow to configure microcode at pre-defined address ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/38640/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38640/6//COMMIT_MSG@7 PS6, Line 7: c > yeah that _could_ work. But I'd rather drop FSP-T for xeons altogether. […] Sounds like a plan, thanks for being open to the discussion. I just hope the long run isn't too long ;-) -- To view, visit https://review.coreboot.org/c/coreboot/+/38640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c02601a7ac64078e556e2032baeccaf27f77da2 Gerrit-Change-Number: 38640 Gerrit-PatchSet: 8 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 18 Feb 2020 20:12:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Andrey Petrov <anpetrov(a)fb.com> Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu: Allow to configure microcode at pre-defined address
by Andrey Petrov (Code Review) 18 Feb '20

18 Feb '20

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38640 ) Change subject: cpu: Allow to configure microcode at pre-defined address ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/38640/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38640/6//COMMIT_MSG@7 PS6, Line 7: c > I think Arthur's proposal is to use our pre-CAR code for doing the µcode update and then (in the sce […] yeah that _could_ work. But I'd rather drop FSP-T for xeons altogether. Whatever we can use pre-CAR code and make FSP-T work as is today I don't know. It needs to be tried. But it feels like waste of time to do that experiment because in the long run we are dropping FSP-T anyway. So I'd advocate for having this patch in, live with FSP-T for a while, and then get rid of it when FSP-T is no longer mandatory. -- To view, visit https://review.coreboot.org/c/coreboot/+/38640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c02601a7ac64078e556e2032baeccaf27f77da2 Gerrit-Change-Number: 38640 Gerrit-PatchSet: 8 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 18 Feb 2020 20:08:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Andrey Petrov <anpetrov(a)fb.com> Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Fixes for Lenovo X301 page
by Evgeny Zinoviev (Code Review) 18 Feb '20

18 Feb '20

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38948 ) Change subject: Documentation: Fixes for Lenovo X301 page ...................................................................... Documentation: Fixes for Lenovo X301 page - Fix lists markup - Some minor fixes in the text (e.g. lowercases) Change-Id: I812bdbeed6609c31f3428a3020fa4b32ebbb3445 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M Documentation/mainboard/lenovo/x301.md 1 file changed, 15 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38948/1 diff --git a/Documentation/mainboard/lenovo/x301.md b/Documentation/mainboard/lenovo/x301.md index 89b422f..b273fc5 100644 --- a/Documentation/mainboard/lenovo/x301.md +++ b/Documentation/mainboard/lenovo/x301.md @@ -22,25 +22,25 @@ what is done in the photo. The vendor IFD VSCC list contains: - -MACRONIX_MX25L6405 (0xc2, 0x2017) - -WINBOND_NEX_W25X64 (0xef, 0x3017) - -ATMEL_AT25DF641 (0x1f, 0x4800) +- MACRONIX_MX25L6405 (0xc2, 0x2017) +- WINBOND_NEX_W25X64 (0xef, 0x3017) +- ATMEL_AT25DF641 (0x1f, 0x4800) The general [flashing tutorial] has more details. Tested: - - CPU Core 2 Duo U9400 - - Slotted DIMM 4GiB*2 from samsung - - Camera - - pci-e slots - - sata and usb2 - - libgfxinit-based graphic init - - NVRAM options for North and South bridges - - Sound - - Thinkpad EC - - S3 - - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from - Linux payload (Heads) and Seabios. +- Core 2 Duo U9400 CPU +- Slotted DIMM 4GiB*2 from Samsung +- Camera +- PCI-e slots +- SATA and USB2 +- libgfxinit-based graphics init +- NVRAM options for North and South bridges +- Sound +- ThinkPad EC +- S3 +- Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from + Linux payload (Heads) and SeaBIOS. [flashing tutorial]: ../../flash_tutorial/ext_power.md -- To view, visit https://review.coreboot.org/c/coreboot/+/38948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I812bdbeed6609c31f3428a3020fa4b32ebbb3445 Gerrit-Change-Number: 38948 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu: Allow to configure microcode at pre-defined address
by Patrick Georgi (Code Review) 18 Feb '20

18 Feb '20

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38640 ) Change subject: cpu: Allow to configure microcode at pre-defined address ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/38640/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38640/6//COMMIT_MSG@7 PS6, Line 7: c > ah, now I understand what you meant. Sorry for being so tone-deaf. […] I think Arthur's proposal is to use our pre-CAR code for doing the µcode update and then (in the scenarios that need it) run FSP-T which doesn't have to do the updates anymore. That way, we get rid of the layout requirement. Doesn't that work? -- To view, visit https://review.coreboot.org/c/coreboot/+/38640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c02601a7ac64078e556e2032baeccaf27f77da2 Gerrit-Change-Number: 38640 Gerrit-PatchSet: 8 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 18 Feb 2020 19:47:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Andrey Petrov <anpetrov(a)fb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard: Add OCP Tioga Pass board
by build bot (Jenkins) (Code Review) 18 Feb '20

18 Feb '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38840 ) Change subject: mainboard: Add OCP Tioga Pass board ...................................................................... Patch Set 4: (5 comments) https://review.coreboot.org/c/coreboot/+/38840/4/src/mainboard/ocp/tiogapas… File src/mainboard/ocp/tiogapass/acpi_tables.c: https://review.coreboot.org/c/coreboot/+/38840/4/src/mainboard/ocp/tiogapas… PS4, Line 16: unsigned long acpi_fill_madt(unsigned long current) { open brace '{' following function definitions go on the next line https://review.coreboot.org/c/coreboot/+/38840/4/src/mainboard/ocp/tiogapas… PS4, Line 21: void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) { open brace '{' following function definitions go on the next line https://review.coreboot.org/c/coreboot/+/38840/4/src/mainboard/ocp/tiogapas… File src/mainboard/ocp/tiogapass/bootblock.c: https://review.coreboot.org/c/coreboot/+/38840/4/src/mainboard/ocp/tiogapas… PS4, Line 14: void bootblock_mainboard_early_init(void) { open brace '{' following function definitions go on the next line https://review.coreboot.org/c/coreboot/+/38840/4/src/mainboard/ocp/tiogapas… PS4, Line 23: pci_mmio_write_config32(PCH_DEV_LPC, 0x80, (1<<28) | (1<<16) | (1<<17) | (0 << 0) | (1 << 4)); line over 96 characters https://review.coreboot.org/c/coreboot/+/38840/4/src/mainboard/ocp/tiogapas… PS4, Line 28: if (CONFIG(BOOTBLOCK_CONSOLE)) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/38840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6c5da3c3856b035af5f2b3b80f0894f6fb81696 Gerrit-Change-Number: 38840 Gerrit-PatchSet: 4 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 18 Feb 2020 19:18:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: xeonsp: Initial Skylake-SP support
by build bot (Jenkins) (Code Review) 18 Feb '20

18 Feb '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38839 ) Change subject: xeonsp: Initial Skylake-SP support ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/38839/3/src/cpu/intel/xeonsp/cpu/s… File src/cpu/intel/xeonsp/cpu/skylake-sp/romstage.c: https://review.coreboot.org/c/coreboot/+/38839/3/src/cpu/intel/xeonsp/cpu/s… PS3, Line 14: m_cfg->PcdHsuartDevice=0; spaces required around that '=' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/38839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaccd8e0034abd5954e3169bf7e585b5f59fe1ead Gerrit-Change-Number: 38839 Gerrit-PatchSet: 3 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 18 Feb 2020 19:18:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard: Add OCP Tioga Pass board
by Andrey Petrov (Code Review) 18 Feb '20

18 Feb '20

Hello Jonathan Zhang, David Hendricks, Stefan Reinauer, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38840 to look at the new patch set (#4). Change subject: mainboard: Add OCP Tioga Pass board ...................................................................... mainboard: Add OCP Tioga Pass board This adds mainboard skeleton file set. Change-Id: Ic6c5da3c3856b035af5f2b3b80f0894f6fb81696 --- A src/mainboard/ocp/Kconfig A src/mainboard/ocp/Kconfig.name A src/mainboard/ocp/tiogapass/Kconfig A src/mainboard/ocp/tiogapass/Kconfig.name A src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/acpi_tables.c A src/mainboard/ocp/tiogapass/board.fmd A src/mainboard/ocp/tiogapass/board_info.txt A src/mainboard/ocp/tiogapass/bootblock.c A src/mainboard/ocp/tiogapass/devicetree.cb A src/mainboard/ocp/tiogapass/dsdt.asl A src/mainboard/ocp/tiogapass/romstage.c 12 files changed, 189 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/38840/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/38840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6c5da3c3856b035af5f2b3b80f0894f6fb81696 Gerrit-Change-Number: 38840 Gerrit-PatchSet: 4 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: xeonsp: Initial Skylake-SP support
by Andrey Petrov (Code Review) 18 Feb '20

18 Feb '20

Hello Patrick Rudolph, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38839 to look at the new patch set (#3). Change subject: xeonsp: Initial Skylake-SP support ...................................................................... xeonsp: Initial Skylake-SP support This adds very basic Skylake-SP support. Change-Id: Iaccd8e0034abd5954e3169bf7e585b5f59fe1ead --- M src/cpu/intel/xeonsp/Makefile.inc A src/cpu/intel/xeonsp/cpu/skylake-sp/Kconfig A src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc A src/cpu/intel/xeonsp/cpu/skylake-sp/chip.h A src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/pci_devs.h A src/cpu/intel/xeonsp/cpu/skylake-sp/romstage.c 6 files changed, 99 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/38839/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/38839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaccd8e0034abd5954e3169bf7e585b5f59fe1ead Gerrit-Change-Number: 38839 Gerrit-PatchSet: 3 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu: Add initial xeonsp support boilerplate
by Andrey Petrov (Code Review) 18 Feb '20

18 Feb '20

Hello Patrick Rudolph, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38838 to look at the new patch set (#3). Change subject: cpu: Add initial xeonsp support boilerplate ...................................................................... cpu: Add initial xeonsp support boilerplate This adds boilerplate code that is common across several Xeon SP processors. The idea is that common xeonsp code should go into cpu/intel/xeonsp/ and CPU-specific files and overrides should go into a subfolder. Change-Id: I24346b8a5c30342419db23b5f1adf27d4d0ebc5f Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> --- M src/cpu/intel/Kconfig M src/cpu/intel/Makefile.inc A src/cpu/intel/xeonsp/Kconfig A src/cpu/intel/xeonsp/Makefile.inc A src/cpu/intel/xeonsp/bootblock.c A src/cpu/intel/xeonsp/include/soc/cpu.h A src/cpu/intel/xeonsp/include/soc/gpe.h A src/cpu/intel/xeonsp/include/soc/gpio.h A src/cpu/intel/xeonsp/include/soc/iomap.h A src/cpu/intel/xeonsp/include/soc/pm.h A src/cpu/intel/xeonsp/include/soc/pmc.h A src/cpu/intel/xeonsp/include/soc/smbus.h A src/cpu/intel/xeonsp/include/soc/systemagent.h A src/cpu/intel/xeonsp/lpc.c A src/cpu/intel/xeonsp/model_xeonsp_init.c A src/cpu/intel/xeonsp/postcar.c A src/cpu/intel/xeonsp/ramstage.c A src/cpu/intel/xeonsp/romstage.c 18 files changed, 414 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/38838/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/38838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24346b8a5c30342419db23b5f1adf27d4d0ebc5f Gerrit-Change-Number: 38838 Gerrit-PatchSet: 3 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit February 2020