coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: lenovo/x230: introduce FHD variant
by Felix Singer (Code Review) 20 Feb '20

20 Feb '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 9: > Patch Set 9: > The firmware I would be happy to make public too, but it looks so disgusting that I don't feel comfortable sharing it right now. Any updates on this? I really would like to see the code open source. -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 9 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aleksei Kharlamov <derlafff(a)ya.ru> Gerrit-CC: Christian Herzog Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Holger Levsen <holger(a)layer-acht.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Matthias Wiedhalm Gerrit-CC: Pavel Kovalenko <su(a)nitrocaster.me> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-CC: Tomasz Jan Góralczyk Gerrit-Comment-Date: Thu, 20 Feb 2020 20:09:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Add PLATFORM_SUPPORTS_STM
by Name of user not set (Code Review) 20 Feb '20

20 Feb '20

cedarhouse1(a)comcast.net has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38837 ) Change subject: soc/intel: Add PLATFORM_SUPPORTS_STM ...................................................................... soc/intel: Add PLATFORM_SUPPORTS_STM Intel x86 processors that have VTx support also support the STM. This patch makes sure the STM option appears when any of these platforms are configured. Signed-off-by: Eugene D. Myers <edmyers(a)tycho.nsa.gov> Change-Id: I448600d6123de36a3402685c25d5c3aa8c4b3753 --- M src/cpu/intel/haswell/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/quark/Kconfig M src/soc/intel/tigerlake/Kconfig 10 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/38837/1 diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index a82198a..94c701c 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -20,6 +20,7 @@ select TSC_SYNC_MFENCE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select PARALLEL_MP + select PLATFORM_SUPPORTS_STM select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select NO_FIXED_XIP_ROM_SIZE diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 0d69da2..0dad1f6 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -50,6 +50,7 @@ select NO_XIP_EARLY_STAGES select PARALLEL_MP select PARALLEL_MP_AP_WORK + select PLATFORM_SUPPORTS_STM select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 1fd9c40..83fd4b1 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -22,6 +22,7 @@ select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP + select PLATFORM_SUPPORTS_STM select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select REG_SCRIPT diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 5b6a923..25d29f9 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -20,6 +20,7 @@ select HAVE_SMI_HANDLER select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP + select PLATFORM_SUPPORTS_STM select PCIEXP_ASPM select PCIEXP_CLK_PM select PCIEXP_COMMON_CLOCK diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 20219d3..e6111bc 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -24,6 +24,7 @@ select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select HAVE_USBDEBUG select IOAPIC + select PLATFORM_SUPPORTS_STM select REG_SCRIPT select PARALLEL_MP select RTC diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index d098785..75fda12 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -77,6 +77,7 @@ select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PARALLEL_MP_AP_WORK + select PLATFORM_SUPPORTS_STM select PLATFORM_USES_FSP2_0 select REG_SCRIPT select SMP diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index aed2beb..96b974c 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -36,6 +36,7 @@ select HAVE_SMI_HANDLER select CACHE_MRC_SETTINGS select PARALLEL_MP + select PLATFORM_SUPPORTS_STM select PCR_COMMON_IOSF_1_0 select SMP select INTEL_DESCRIPTOR_MODE_CAPABLE diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 15e895f..cfcdf8b 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -29,6 +29,7 @@ select MRC_SETTINGS_PROTECT select PARALLEL_MP select PARALLEL_MP_AP_WORK + select PLATFORM_SUPPORTS_STM select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 select REG_SCRIPT diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 099c7dd..9a84593 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -28,6 +28,7 @@ select ARCH_VERSTAGE_X86_32 select NO_MMCONF_SUPPORT select REG_SCRIPT + select PLATFORM_SUPPORTS_STM select PLATFORM_USES_FSP2_0 select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index cef1fd0..82e45aa 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -42,6 +42,7 @@ select MRC_SETTINGS_PROTECT select PARALLEL_MP select PARALLEL_MP_AP_WORK + select PLATFORM_SUPPORTS_STM select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 select REG_SCRIPT -- To view, visit https://review.coreboot.org/c/coreboot/+/38837 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I448600d6123de36a3402685c25d5c3aa8c4b3753 Gerrit-Change-Number: 38837 Gerrit-PatchSet: 1 Gerrit-Owner: cedarhouse1(a)comcast.net Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/stoneyridge: Remove TODO for file extensions
by Marshall Dawson (Code Review) 20 Feb '20

20 Feb '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39012 ) Change subject: soc/amd/stoneyridge: Remove TODO for file extensions ...................................................................... soc/amd/stoneyridge: Remove TODO for file extensions The comment is no longer relevant. Perhaps the intention had been to modify the names of the files delivered from AMD in order to simplify Makefile.inc. AMD firmware is distributed via the new amd_blobs repo and the filenames match the blobs as they are released. Multiple Family 15h devices are supported by this directory and their SMU Firmwares do not all follow identical naming convention. Keep the existing functionality and reword the comment. BUG=b:120118850 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: Ifbf8e2286f34bc37a6178c37f8c412ec51ee02c9 --- M src/soc/amd/stoneyridge/Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/39012/1 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index eb8af2d..0cc49c8 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -155,8 +155,8 @@ ###4 PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin -###8 - Check for SMU firmware named either *.sbin or *.csbin -### TODO: Remove *.sbin section after the blobs repo is updated. +###8 - Check for SMU firmware named either *.sbin or *.csbin. Both "signed" and +### "compressed signed" are used by generations supported by this file. SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware_$(FIRMWARE_TYPE).csbin SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware_$(FIRMWARE_TYPE)_FN.csbin ifeq ("$(wildcard $(SMUFWM_FILE))","") -- To view, visit https://review.coreboot.org/c/coreboot/+/39012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbf8e2286f34bc37a6178c37f8c412ec51ee02c9 Gerrit-Change-Number: 39012 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block: Move smihandler common functions into common ...
by Furquan Shaikh (Code Review) 20 Feb '20

20 Feb '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26138 ) Change subject: soc/intel/common/block: Move smihandler common functions into common code ...................................................................... Patch Set 42: (3 comments) https://review.coreboot.org/c/coreboot/+/26138/41/src/soc/intel/common/bloc… File src/soc/intel/common/block/smm/smihandler.c: https://review.coreboot.org/c/coreboot/+/26138/41/src/soc/intel/common/bloc… PS41, Line 67: __weak Why is this still kept weak? None of the SoCs provide their own implementation after this change. https://review.coreboot.org/c/coreboot/+/26138/41/src/soc/intel/common/bloc… PS41, Line 70: tco_sts So, there is a slight change in behavior now for APL. Previously, this function would do nothing, but now: a) It checks bit 8 in tco_sts, but that bit is marked reserved. As per EDS, it is RO and reads as 0, so I am guessing this has no side-effects? b) But, CONFIG(SPI_FLASH_SMM) could be true and so now this would always end up calling fast_spi_enable_wp(). Are you changing this intentionally? https://review.coreboot.org/c/coreboot/+/26138/41/src/soc/intel/common/bloc… PS41, Line 499: nit: extra blank line not required. -- To view, visit https://review.coreboot.org/c/coreboot/+/26138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03 Gerrit-Change-Number: 26138 Gerrit-PatchSet: 42 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 20 Feb 2020 16:36:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block: Move smihandler common functions into common ...
by Subrata Banik (Code Review) 20 Feb '20

20 Feb '20

Hello Aaron Durbin, Patrick Rudolph, Angel Pons, Aamir Bohra, Wonkyu Kim, Maulik V Vaghela, Jeremy Soller, Duncan Laurie, Paul Menzel, Shelley Chen, build bot (Jenkins), Hannah Williams, Furquan Shaikh, Patrick Georgi, Pratikkumar V Prajapati, V Sowmya, Lance Zhao, Krzysztof M Sywula, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/26138 to look at the new patch set (#42). Change subject: soc/intel/common/block: Move smihandler common functions into common code ...................................................................... soc/intel/common/block: Move smihandler common functions into common code This patch cleans soc/intel/{apl/cnl/skl/icl/tgl} by moving common soc code into common/block/smihandler.c BUG=b:78109109 TEST=Build and boot KBL/CNL/APL/ICL/TGL platform. Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/smihandler.c M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/common/block/include/intelblocks/smihandler.h M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/icelake/smihandler.c M src/soc/intel/skylake/smihandler.c M src/soc/intel/tigerlake/smihandler.c 7 files changed, 43 insertions(+), 178 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/26138/42 -- To view, visit https://review.coreboot.org/c/coreboot/+/26138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03 Gerrit-Change-Number: 26138 Gerrit-PatchSet: 42 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/apollolake: Display platform information
by Usha P (Code Review) 20 Feb '20

20 Feb '20

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Change in coreboot[master]: soc/intel/apollolake: Display platform information
by Usha P (Code Review) 20 Feb '20

20 Feb '20

Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38824 ) Change subject: soc/intel/apollolake: Display platform information ...................................................................... Patch Set 7: (5 comments) https://review.coreboot.org/c/coreboot/+/38824/4/src/soc/intel/apollolake/r… File src/soc/intel/apollolake/report_platform.c: https://review.coreboot.org/c/coreboot/+/38824/4/src/soc/intel/apollolake/r… PS4, Line 79: u32 i > Yes i have made all the counting variables `unsigned int`in the new patch set Done https://review.coreboot.org/c/coreboot/+/38824/6/src/soc/intel/apollolake/r… File src/soc/intel/apollolake/report_platform.c: https://review.coreboot.org/c/coreboot/+/38824/6/src/soc/intel/apollolake/r… PS6, Line 4: * Copyright (C) 2020 Intel Corporation. > Remove the dot at the end. Done https://review.coreboot.org/c/coreboot/+/38824/6/src/soc/intel/apollolake/r… PS6, Line 103: cpu_id, cpu_type, microcode_ver.hi); > Fits on one line? Done https://review.coreboot.org/c/coreboot/+/38824/6/src/soc/intel/apollolake/r… PS6, Line 106: aes_supported = (cpu_feature_flag & CPUID_AES) ? 1 : 0; > Sorry, I did not check. […] Done https://review.coreboot.org/c/coreboot/+/38824/6/src/soc/intel/apollolake/r… PS6, Line 172: report_igd_info(); > Can you make some parts of that common code? Yes. This will be taken care in the common code related patches. https://review.coreboot.org/c/coreboot/+/25810 is WIP patch which will handle the common part of report_platform.c code -- To view, visit https://review.coreboot.org/c/coreboot/+/38824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4edfeae7faee9f5f80698cf34b31fdcb066a813 Gerrit-Change-Number: 38824 Gerrit-PatchSet: 7 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 20 Feb 2020 13:47:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Usha P <usha.p(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/apollolake: Display platform information
by build bot (Jenkins) (Code Review) 20 Feb '20

20 Feb '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38824 ) Change subject: soc/intel/apollolake: Display platform information ...................................................................... Patch Set 7: (2 comments) https://review.coreboot.org/c/coreboot/+/38824/7/src/soc/intel/apollolake/r… File src/soc/intel/apollolake/report_platform.c: https://review.coreboot.org/c/coreboot/+/38824/7/src/soc/intel/apollolake/r… PS7, Line 81: const char * support = "Supported"; "foo * bar" should be "foo *bar" https://review.coreboot.org/c/coreboot/+/38824/7/src/soc/intel/apollolake/r… PS7, Line 82: const char * no_support = "Not Supported"; "foo * bar" should be "foo *bar" -- To view, visit https://review.coreboot.org/c/coreboot/+/38824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4edfeae7faee9f5f80698cf34b31fdcb066a813 Gerrit-Change-Number: 38824 Gerrit-PatchSet: 7 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 20 Feb 2020 13:36:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/apollolake: Display platform information
by Usha P (Code Review) 20 Feb '20

20 Feb '20

Hello Werner Zeh, Patrick Rudolph, Subrata Banik, Aamir Bohra, Rizwan Qureshi, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38824 to look at the new patch set (#7). Change subject: soc/intel/apollolake: Display platform information ...................................................................... soc/intel/apollolake: Display platform information This patch includes the change required to display Apollo Lake platform information which reports CPU, MCH, PCH and IGD information in romstage. BUG=None TEST= 1. Boot to OS on Bobba board. 2. Verified below info from CPU Console log in romstage CPU: Intel(R) Celeron(R) N4000 CPU @ 1.10GHz CPU: ID 706a1, Geminilake B0, ucode: 00000031 CPU: AES supported, TXT NOT supported, VT supported MCH: device id 31f0 (rev 03) is Geminilake PCH: device id 3197 (rev 03) is Geminilake IGD: device id 3185 (rev 03) is Geminilake EU12 Change-Id: Id4edfeae7faee9f5f80698cf34b31fdcb066a813 Signed-off-by: Usha P <usha.p(a)intel.com> --- M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/include/soc/romstage.h A src/soc/intel/apollolake/report_platform.c M src/soc/intel/apollolake/romstage.c 4 files changed, 173 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38824/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/38824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4edfeae7faee9f5f80698cf34b31fdcb066a813 Gerrit-Change-Number: 38824 Gerrit-PatchSet: 7 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 20 Feb '20

20 Feb '20

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Sridhar Siricilla, Rizwan Qureshi, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, V Sowmya, Nico Huber, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35402 to look at the new patch set (#65). Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... soc/intel/common/block/cse: Add boot partition related APIs The CSE region is logically divided into 3 boot partitions when redundancy is enabled. These boot partitions are represented by BP1, BP2 and BP3. In chrome platforms, CSE can boot from either BP1 or BP2. The CSE image layout appears as below.. ------------- -------------------- -------------------------- |CSE REGION | => | RO | RW | DATA | => | BP1 | BP2 + BP3 | DATA | ------------- -------------------- -------------------------- In order to support CSE FW update to RW region, below APIs help coreboot to get info about the boot partitions, and allows coreboot to set CSE to boot from required boot partition (either BP1(RO) or BP2). GET_BOOT_PARTITION_INFO - provides info on available partitions in the CSE region. The API provides info on boot partitions like start/end offsets of a partition within CSE region, and their version and partition status. SET_BOOT_PARTITION_INFO - Sets next boot partition to boot for CSE. With the HECI API, firmware can notify CSE to boot from BP1 or BP2 on next boot. BUG=b:145809764 Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/Makefile.inc A src/soc/intel/common/block/cse/cse_bp.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 496 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35402/65 -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 65 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit February 2020