coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support
by Srinidhi N Kaushik (Code Review) 22 Feb '20

22 Feb '20

Hello Raj Astekar, Patrick Rudolph, Subrata Banik, Nick Vaccaro, Wonkyu Kim, Ravishankar Sarawadi, build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38998 to look at the new patch set (#11). Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support ...................................................................... mb/intel/tglrvp: add Tiger Lake memory initialization support Update memory parameters based on memory type supported by Tiger lake RVP 1. Update dq/dqs mappings and rcomp data 2. Update spd data for Tiger lake LPDDR4 SAMSUNG/MICRON memory 3. Add SPD data bin files for supported memory types 4. Update other FSPM Upds as part of memory initialization BUG=none BRANCH=none TEST= build tglrvp flash and boot to kernel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e --- M src/mainboard/intel/tglrvp/board_id.h M src/mainboard/intel/tglrvp/romstage_fsp_params.c A src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex M src/mainboard/intel/tglrvp/spd/Makefile.inc A src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex A src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex M src/mainboard/intel/tglrvp/spd/spd.h M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc A src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c 10 files changed, 280 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/38998/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/38998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Gerrit-Change-Number: 38998 Gerrit-PatchSet: 11 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/intel/xeonsp: Add initial Skylake-SP support
by Andrey Petrov (Code Review) 21 Feb '20

21 Feb '20

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38839 ) Change subject: cpu/intel/xeonsp: Add initial Skylake-SP support ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/38839/8//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38839/8//COMMIT_MSG@7 PS8, Line 7: Initial Skylake-SP support > cpu/intel/xeonsp: Add initial Skylake-SP support Done -- To view, visit https://review.coreboot.org/c/coreboot/+/38839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaccd8e0034abd5954e3169bf7e585b5f59fe1ead Gerrit-Change-Number: 38839 Gerrit-PatchSet: 11 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 21 Feb 2020 22:29:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard: Add OCP Tioga Pass board
by build bot (Jenkins) (Code Review) 21 Feb '20

21 Feb '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38840 ) Change subject: mainboard: Add OCP Tioga Pass board ...................................................................... Patch Set 13: (1 comment) https://review.coreboot.org/c/coreboot/+/38840/13/src/mainboard/ocp/tiogapa… File src/mainboard/ocp/tiogapass/bootblock.c: https://review.coreboot.org/c/coreboot/+/38840/13/src/mainboard/ocp/tiogapa… PS13, Line 46: if (CONFIG(BOOTBLOCK_CONSOLE)) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/38840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6c5da3c3856b035af5f2b3b80f0894f6fb81696 Gerrit-Change-Number: 38840 Gerrit-PatchSet: 13 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Feb 2020 22:17:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu: Add initial xeonsp support boilerplate
by build bot (Jenkins) (Code Review) 21 Feb '20

21 Feb '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38838 ) Change subject: cpu: Add initial xeonsp support boilerplate ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/38838/11/src/cpu/intel/xeonsp/boot… File src/cpu/intel/xeonsp/bootblock.c: https://review.coreboot.org/c/coreboot/+/38838/11/src/cpu/intel/xeonsp/boot… PS11, Line 52: if (CONFIG(BOOTBLOCK_CONSOLE)) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/38838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24346b8a5c30342419db23b5f1adf27d4d0ebc5f Gerrit-Change-Number: 38838 Gerrit-PatchSet: 11 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 21 Feb 2020 22:17:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu: Add initial xeonsp support boilerplate
by Andrey Petrov (Code Review) 21 Feb '20

21 Feb '20

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38838 to look at the new patch set (#11). Change subject: cpu: Add initial xeonsp support boilerplate ...................................................................... cpu: Add initial xeonsp support boilerplate This adds boilerplate code that is common across several Xeon SP processors. The idea is that common xeonsp code should go into cpu/intel/xeonsp/ and CPU-specific files and overrides should go into a subfolder. Change-Id: I24346b8a5c30342419db23b5f1adf27d4d0ebc5f Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> --- M src/cpu/intel/Kconfig M src/cpu/intel/Makefile.inc A src/cpu/intel/xeonsp/Kconfig A src/cpu/intel/xeonsp/Makefile.inc A src/cpu/intel/xeonsp/bootblock.c A src/cpu/intel/xeonsp/include/soc/cpu.h A src/cpu/intel/xeonsp/include/soc/gpe.h A src/cpu/intel/xeonsp/include/soc/gpio.h A src/cpu/intel/xeonsp/include/soc/iomap.h A src/cpu/intel/xeonsp/include/soc/pm.h A src/cpu/intel/xeonsp/include/soc/pmc.h A src/cpu/intel/xeonsp/include/soc/smbus.h A src/cpu/intel/xeonsp/include/soc/systemagent.h A src/cpu/intel/xeonsp/lpc.c A src/cpu/intel/xeonsp/model_xeonsp_init.c A src/cpu/intel/xeonsp/postcar.c A src/cpu/intel/xeonsp/ramstage.c A src/cpu/intel/xeonsp/romstage.c 18 files changed, 486 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/38838/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/38838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24346b8a5c30342419db23b5f1adf27d4d0ebc5f Gerrit-Change-Number: 38838 Gerrit-PatchSet: 11 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu: Add initial xeonsp support boilerplate
by build bot (Jenkins) (Code Review) 21 Feb '20

21 Feb '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38838 ) Change subject: cpu: Add initial xeonsp support boilerplate ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/38838/10/src/cpu/intel/xeonsp/boot… File src/cpu/intel/xeonsp/bootblock.c: https://review.coreboot.org/c/coreboot/+/38838/10/src/cpu/intel/xeonsp/boot… PS10, Line 52: if (CONFIG(BOOTBLOCK_CONSOLE)) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/38838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24346b8a5c30342419db23b5f1adf27d4d0ebc5f Gerrit-Change-Number: 38838 Gerrit-PatchSet: 10 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 21 Feb 2020 21:06:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard: Add OCP Tioga Pass board
by build bot (Jenkins) (Code Review) 21 Feb '20

21 Feb '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38840 ) Change subject: mainboard: Add OCP Tioga Pass board ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/c/coreboot/+/38840/12/src/mainboard/ocp/tiogapa… File src/mainboard/ocp/tiogapass/bootblock.c: https://review.coreboot.org/c/coreboot/+/38840/12/src/mainboard/ocp/tiogapa… PS12, Line 46: if (CONFIG(BOOTBLOCK_CONSOLE)) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/38840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6c5da3c3856b035af5f2b3b80f0894f6fb81696 Gerrit-Change-Number: 38840 Gerrit-PatchSet: 12 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Feb 2020 21:06:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/xeonsp: Add initial Skylake-SP support
by Andrey Petrov (Code Review) 21 Feb '20

21 Feb '20

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38839 to look at the new patch set (#10). Change subject: cpu/intel/xeonsp: Add initial Skylake-SP support ...................................................................... cpu/intel/xeonsp: Add initial Skylake-SP support This adds very basic Skylake-SP support. TEST=bootblock works and prints on serial on OCP TiogaPass Change-Id: Iaccd8e0034abd5954e3169bf7e585b5f59fe1ead Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> --- M src/cpu/intel/Kconfig M src/cpu/intel/xeonsp/Makefile.inc A src/cpu/intel/xeonsp/cpu/skylake-sp/Kconfig A src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc A src/cpu/intel/xeonsp/cpu/skylake-sp/chip.h A src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/pci_devs.h A src/cpu/intel/xeonsp/cpu/skylake-sp/romstage.c 7 files changed, 115 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/38839/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/38839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaccd8e0034abd5954e3169bf7e585b5f59fe1ead Gerrit-Change-Number: 38839 Gerrit-PatchSet: 10 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu: Add initial xeonsp support boilerplate
by Andrey Petrov (Code Review) 21 Feb '20

21 Feb '20

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38838 to look at the new patch set (#10). Change subject: cpu: Add initial xeonsp support boilerplate ...................................................................... cpu: Add initial xeonsp support boilerplate This adds boilerplate code that is common across several Xeon SP processors. The idea is that common xeonsp code should go into cpu/intel/xeonsp/ and CPU-specific files and overrides should go into a subfolder. Change-Id: I24346b8a5c30342419db23b5f1adf27d4d0ebc5f Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> --- M src/cpu/intel/Kconfig M src/cpu/intel/Makefile.inc A src/cpu/intel/xeonsp/Kconfig A src/cpu/intel/xeonsp/Makefile.inc A src/cpu/intel/xeonsp/bootblock.c A src/cpu/intel/xeonsp/include/soc/cpu.h A src/cpu/intel/xeonsp/include/soc/gpe.h A src/cpu/intel/xeonsp/include/soc/gpio.h A src/cpu/intel/xeonsp/include/soc/iomap.h A src/cpu/intel/xeonsp/include/soc/pm.h A src/cpu/intel/xeonsp/include/soc/pmc.h A src/cpu/intel/xeonsp/include/soc/smbus.h A src/cpu/intel/xeonsp/include/soc/systemagent.h A src/cpu/intel/xeonsp/lpc.c A src/cpu/intel/xeonsp/model_xeonsp_init.c A src/cpu/intel/xeonsp/postcar.c A src/cpu/intel/xeonsp/ramstage.c A src/cpu/intel/xeonsp/romstage.c 18 files changed, 486 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/38838/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/38838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24346b8a5c30342419db23b5f1adf27d4d0ebc5f Gerrit-Change-Number: 38838 Gerrit-PatchSet: 10 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/mainboard/google: deduplicate create_coreboot_variant.sh
by Paul Fagerburg (Code Review) 21 Feb '20

21 Feb '20

Paul Fagerburg has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38979 ) Change subject: util/mainboard/google: deduplicate create_coreboot_variant.sh ...................................................................... util/mainboard/google: deduplicate create_coreboot_variant.sh create_coreboot_variant.sh (and the helper program kconfig.py) have moved to dev/contrib, so remove them from the coreboot repo. BUG=b:149410618 BRANCH=None TEST=N/A Cq-Depend: chromium:2052338 Signed-off-by: Paul Fagerburg <pfagerburg(a)chromium.org> Change-Id: Ie27f68bfd978be5e2b1a2f0789d574749825f6fc --- D util/mainboard/google/create_coreboot_variant.sh D util/mainboard/google/kconfig.py 2 files changed, 0 insertions(+), 234 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/38979/1 diff --git a/util/mainboard/google/create_coreboot_variant.sh b/util/mainboard/google/create_coreboot_variant.sh deleted file mode 100755 index dcbacb9..0000000 --- a/util/mainboard/google/create_coreboot_variant.sh +++ /dev/null @@ -1,94 +0,0 @@ -#!/bin/bash -# -# This file is part of the coreboot project. -# -# Copyright 2019 Google LLC. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -VERSION="2.0.0" -SCRIPT=$(basename -- "${0}") - -export LC_ALL=C - -if [[ "$#" -lt 3 ]]; then - echo "Usage: ${SCRIPT} base_name reference_name variant_name [bug_number]" - echo "e.g. ${SCRIPT} hatch hatch kohaku b:140261109" - echo "e.g. ${SCRIPT} zork trembyle dalboz" - echo "* Adds a new variant of the baseboard to Kconfig and Kconfig.name" - echo "* Copies the template files for the baseboard to the new variant" - exit 1 -fi - -# This is the name of the base board -# ${var,,} converts to all lowercase. -BASE="${1,,}" -# This is the name of the reference board that we're using to make the variant. -REFERENCE="${2,,}" -# This is the name of the variant that is being cloned. -# ${var,,} converts to all lowercase; ${var^^} is all uppercase. -VARIANT="${3,,}" -VARIANT_UPPER="${VARIANT^^}" - -# Assign BUG= text, or "None" if that parameter wasn't specified. -BUG=${4:-None} - -# This script lives in util/mainboard/google -# The template files are in util/mainboard/google/${BASE}/templates -# We need to create files in src/mainboard/google/${BASE}/variants/${VARIANT} -pushd "${BASH_SOURCE%/*}" || exit 1 -SRC=$(pwd) -popd || exit 1 -pushd "${SRC}/../../../src/mainboard/google/${BASE}" || { - echo "The baseboard directory for ${BASE} does not exist."; - exit 1; } - -# Make sure the variant doesn't already exist. -if [[ -e variants/${VARIANT} ]]; then - echo "variants/${VARIANT} already exists." - echo "Have you already created this variant?" - exit 1 -fi - -# Start a branch. Use YMD timestamp to avoid collisions. -DATE=$(date +%Y%m%d) -git checkout -b "coreboot_${VARIANT}_${DATE}" || exit 1 - -# Copy the template tree to the target. -mkdir -p "variants/${VARIANT}/" -cp -pr "${SRC}/${BASE}/template/." "variants/${VARIANT}/" -if [[ -e "variants/${VARIANT}/Kconfig" ]]; then - sed -i -e "s/BOARD_GOOGLE_TEMPLATE/BOARD_GOOGLE_${VARIANT_UPPER}/" \ - "variants/${VARIANT}/Kconfig" -fi -git add "variants/${VARIANT}/" - -# Now add the new variant to Kconfig and Kconfig.name -# These files are in the current directory, e.g. src/mainboard/google/hatch -"${SRC}/kconfig.py" --board "${BASE}" --variant "${VARIANT}" || exit 1 - -mv Kconfig.new Kconfig -mv Kconfig.name.new Kconfig.name - -git add Kconfig Kconfig.name - -# Now commit the files. -git commit -sm "${BASE}: Create ${VARIANT} variant - -Create the ${VARIANT} variant of the ${REFERENCE} reference -board by copying the template files to a new directory named -for the variant. - -(Auto-Generated by ${SCRIPT} version ${VERSION}). - -BUG=${BUG} -BRANCH=None -TEST=util/abuild/abuild -p none -t google/${BASE} -x -a -make sure the build includes GOOGLE_${VARIANT_UPPER}" diff --git a/util/mainboard/google/kconfig.py b/util/mainboard/google/kconfig.py deleted file mode 100755 index 1293f4a..0000000 --- a/util/mainboard/google/kconfig.py +++ /dev/null @@ -1,140 +0,0 @@ -#!/usr/bin/env python3 -# -*- coding: utf-8 -*- -"""Add a new variant to the Kconfig and Kconfig.name - -To start a new variant of an existing reference board, we need to -add the variant into the Kconfig and Kconfig.name files for the -reference board. In Kconfig, we have two sections that need additional -entries, MAINBOARD_PART_NUMBER and VARIANT_DIR. - -The MAINBOARD_PART_NUMBER and VARIANT_DIR just use various -capitalizations of the variant name to create the strings. - -Kconfig.name adds an entire section for the new variant, and all -of these use various capitalizations of the variant name. The strings -in this section are SOC-specific, so we'll need versions for each -SOC that we support. - -Copyright 2019 Google LLC. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; version 2 of the License. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. -""" - -from __future__ import print_function -import argparse -import sys - - -def main(): - parser = argparse.ArgumentParser( - description='Add strings to coreboot Kconfig for a new board variant') - parser.add_argument('--board', type=str, required=True, - help='Name of the reference board') - parser.add_argument('--variant', type=str, required=True, - help='Name of the board variant') - args = parser.parse_args() - - if args.board not in ['hatch', 'volteer', 'trembyle']: - print('Unsupported reference board "' + args.board + '"') - sys.exit(1) - - add_to_Kconfig(args.variant) - add_to_Kconfig_name(args.board, args.variant) - - -def add_to_Kconfig(variant_name): - """Add options for the variant to the Kconfig - - Open the Kconfig file and read it line-by-line. When we detect that we're - in one of the sections of interest, wait until we get a blank line - (signalling the end of that section), and then add our new line before - the blank line. The updated lines are written out to Kconfig.new in the - same directory as Kconfig. - - variant_name The name of the board variant, e.g. 'kohaku' - """ - # These are the part of the strings that we'll add to the sections - BOARD = 'BOARD_GOOGLE_' + variant_name.upper() - lowercase = variant_name.lower() - capitalized = lowercase.capitalize() - - # These flags track whether we're in a section where we need to add an option - in_mainboard_part_number = False - in_variant_dir = False - - inputname = 'Kconfig' - outputname = 'Kconfig.new' - with open(outputname, 'w') as outfile: - with open(inputname, 'r') as infile: - for rawline in infile: - line = rawline.rstrip('\r\n') - - # Are we in one of the sections of interest? - if line == 'config MAINBOARD_PART_NUMBER': - in_mainboard_part_number = True - if line == 'config VARIANT_DIR': - in_variant_dir = True - - # Are we at the end of a section, and if so, is it one of the - # sections of interest? - if line == '': - if in_mainboard_part_number: - print('\tdefault "' + capitalized + '" if ' + BOARD, file=outfile) - in_mainboard_part_number = False - if in_variant_dir: - print('\tdefault "' + lowercase + '" if ' + BOARD, file=outfile) - in_variant_dir = False - - print(line, file=outfile) - - -def add_to_Kconfig_name(refboard_name, variant_name): - """Add a config section for the variant to the Kconfig.name - - Kconfig.name is easier to modify than Kconfig; it only has a block at - the end with the new variant's details. - - refboard_name The name of the reference board, e.g. 'hatch' - We expect the caller to have checked that it is one we support - variant_name The name of the board variant, e.g. 'kohaku' - """ - # Board name for the config section - uppercase = variant_name.upper() - capitalized = variant_name.lower().capitalize() - - inputname = 'Kconfig.name' - outputname = 'Kconfig.name.new' - with open(outputname, 'w') as outfile: - with open(inputname, 'r') as infile: - # Copy all input lines to output - for rawline in infile: - line = rawline.rstrip('\r\n') - print(line, file=outfile) - - # Now add the new section - if refboard_name == 'hatch': - print('\nconfig ' + 'BOARD_GOOGLE_' + uppercase, file=outfile) - print('\tbool "-> ' + capitalized + '"', file=outfile) - print('\tselect BOARD_GOOGLE_BASEBOARD_HATCH', file=outfile) - print('\tselect BOARD_ROMSIZE_KB_16384', file=outfile) - - if refboard_name == 'volteer': - print('\nconfig ' + 'BOARD_GOOGLE_' + uppercase, file=outfile) - print('\tbool "-> ' + capitalized + '"', file=outfile) - print('\tselect BOARD_GOOGLE_BASEBOARD_VOLTEER', file=outfile) - - if refboard_name == 'trembyle': - print('\nconfig ' + 'BOARD_GOOGLE_' + uppercase, file=outfile) - print('\tbool "-> ' + capitalized + '"', file=outfile) - print('\tselect BOARD_GOOGLE_BASEBOARD_TREMBYLE', file=outfile) - - -if __name__ == '__main__': - main() -- To view, visit https://review.coreboot.org/c/coreboot/+/38979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie27f68bfd978be5e2b1a2f0789d574749825f6fc Gerrit-Change-Number: 38979 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit February 2020