coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/tigerlake: add Rcomp data structure
by Srinidhi N Kaushik (Code Review) 27 Feb '20

27 Feb '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39040 ) Change subject: soc/intel/tigerlake: add Rcomp data structure ...................................................................... soc/intel/tigerlake: add Rcomp data structure Add Rcomp data structure in meminit to support updating rcomp resistor and target values for DDR4 support. BUG=none BRANCH=none TEST= build tglrvp flash and boot to kernel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I3858cc56c838862fc61123c8b7dba11dbc40983c --- M src/soc/intel/tigerlake/include/soc/meminit_tgl.h 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/39040/1 diff --git a/src/soc/intel/tigerlake/include/soc/meminit_tgl.h b/src/soc/intel/tigerlake/include/soc/meminit_tgl.h old mode 100644 new mode 100755 index dd05418..c093304 --- a/src/soc/intel/tigerlake/include/soc/meminit_tgl.h +++ b/src/soc/intel/tigerlake/include/soc/meminit_tgl.h @@ -17,6 +17,7 @@ #define BITS_PER_BYTE 8 #define DQS_PER_CHANNEL 2 #define NUM_CHANNELS 8 +#define NUM_RCOMP_TARGETS 5 struct spd_by_pointer { size_t spd_data_len; @@ -61,6 +62,16 @@ uint8_t ect; }; +/* Rcomp configuration information */ +struct rcomp_cfg { + /* Rcomp Resistor */ + uint16_t rcomp_resistor; + + /* Rcomp Target */ + uint16_t rcomp_target[NUM_RCOMP_TARGETS]; + +}; + /* Initialize default memory configurations for dimm0-only lpddr4x */ void meminit_lpddr4x_dimm0(FSP_M_CONFIG *mem_cfg, const struct mb_lpddr4x_cfg *board_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/39040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3858cc56c838862fc61123c8b7dba11dbc40983c Gerrit-Change-Number: 39040 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/apollolake: Display platform information
by Subrata Banik (Code Review) 27 Feb '20

27 Feb '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38824 ) Change subject: soc/intel/apollolake: Display platform information ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/38824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4edfeae7faee9f5f80698cf34b31fdcb066a813 Gerrit-Change-Number: 38824 Gerrit-PatchSet: 8 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 27 Feb 2020 04:54:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/apollolake: Display platform information
by Usha P (Code Review) 27 Feb '20

27 Feb '20

Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38824 ) Change subject: soc/intel/apollolake: Display platform information ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/c/coreboot/+/38824/7/src/soc/intel/apollolake/r… File src/soc/intel/apollolake/report_platform.c: https://review.coreboot.org/c/coreboot/+/38824/7/src/soc/intel/apollolake/r… PS7, Line 81: const char * support = "Supported"; > "foo * bar" should be "foo *bar" Done https://review.coreboot.org/c/coreboot/+/38824/7/src/soc/intel/apollolake/r… PS7, Line 82: const char * no_support = "Not Supported"; > "foo * bar" should be "foo *bar" Done -- To view, visit https://review.coreboot.org/c/coreboot/+/38824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4edfeae7faee9f5f80698cf34b31fdcb066a813 Gerrit-Change-Number: 38824 Gerrit-PatchSet: 8 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 27 Feb 2020 04:52:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/apollolake: Display platform information
by Usha P (Code Review) 27 Feb '20

27 Feb '20

Hello Werner Zeh, Patrick Rudolph, Subrata Banik, Aamir Bohra, Rizwan Qureshi, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38824 to look at the new patch set (#8). Change subject: soc/intel/apollolake: Display platform information ...................................................................... soc/intel/apollolake: Display platform information This patch includes the change required to display Apollo Lake platform information which reports CPU, MCH, PCH and IGD information in romstage. BUG=None TEST= 1. Boot to OS on Bobba board. 2. Verified below info from CPU Console log in romstage CPU: Intel(R) Celeron(R) N4000 CPU @ 1.10GHz CPU: ID 706a1, Geminilake B0, ucode: 00000031 CPU: AES supported, TXT NOT supported, VT supported MCH: device id 31f0 (rev 03) is Geminilake PCH: device id 3197 (rev 03) is Geminilake IGD: device id 3185 (rev 03) is Geminilake EU12 Change-Id: Id4edfeae7faee9f5f80698cf34b31fdcb066a813 Signed-off-by: Usha P <usha.p(a)intel.com> --- M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/include/soc/romstage.h A src/soc/intel/apollolake/report_platform.c M src/soc/intel/apollolake/romstage.c 4 files changed, 173 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38824/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/38824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4edfeae7faee9f5f80698cf34b31fdcb066a813 Gerrit-Change-Number: 38824 Gerrit-PatchSet: 8 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sc7180: Add QUPv3 FW load & config
by Roja Rani Yarubandi (Code Review) 27 Feb '20

27 Feb '20

Roja Rani Yarubandi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35499 ) Change subject: sc7180: Add QUPv3 FW load & config ...................................................................... Patch Set 39: (4 comments) > Patch Set 39: > > (5 comments) Shared patches with Mike to post upstream https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/i… File src/soc/qualcomm/sc7180/include/soc/addressmap.h: https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/i… PS39, Line 32: 0x8C0000 > Please write all 8 digits (e.g. […] Done https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/i… File src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h: https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/i… PS39, Line 326: union proto_rx_trans_len rx_trans_len; > nit: I think these would look better if you wrote them with an inline unnamed union, actually... e. […] Done https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/q… File src/soc/qualcomm/sc7180/qupv3_config.c: https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/q… PS39, Line 52: clock_configure_dfsr(bus); > If the non-UART QUPs initialize their base clock here, I think it would make sense to do that for th […] Done https://review.coreboot.org/c/coreboot/+/35499/39/src/soc/qualcomm/sc7180/q… PS39, Line 174: qup_load_se_firmware > This is doing more than loading firmware (e.g. […] Merged two functions. -- To view, visit https://review.coreboot.org/c/coreboot/+/35499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d91dd10488931247f81a87b0bdcc598f4bceb31 Gerrit-Change-Number: 35499 Gerrit-PatchSet: 39 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Doug Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-CC: Satya Priya Kakitapalli <c_skakit(a)qualcomm.corp-partner.google.com> Gerrit-CC: Stephen Boyd <swboyd(a)chromium.org> Gerrit-Comment-Date: Thu, 27 Feb 2020 03:17:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Fix out-of-bounds read
by Alexandre Rebert (Code Review) 26 Feb '20

26 Feb '20

Alexandre Rebert has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39033 ) Change subject: libpayload: Fix out-of-bounds read ...................................................................... libpayload: Fix out-of-bounds read Fix an out-of-bounds read in the LZMA decoder which happens when the src buffer is too small to contain the 13-byte LZMA header. Change-Id: Ie442f82cd1abcf7fa18295e782cccf26a7d30079 Signed-off-by: Alex Rebert <alexandre.rebert(a)gmail.com> --- M payloads/libpayload/liblzma/lzma.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/39033/1 diff --git a/payloads/libpayload/liblzma/lzma.c b/payloads/libpayload/liblzma/lzma.c index 57a8b3a..132ae84 100644 --- a/payloads/libpayload/liblzma/lzma.c +++ b/payloads/libpayload/liblzma/lzma.c @@ -28,6 +28,11 @@ SizeT mallocneeds; unsigned char *scratchpad; + if (srcn < data_offset) { + printf("lzma: Input too small.") + return 0; + } + memcpy(properties, src, LZMA_PROPERTIES_SIZE); memcpy(&outSize, src + LZMA_PROPERTIES_SIZE, sizeof(outSize)); if (outSize > dstn) -- To view, visit https://review.coreboot.org/c/coreboot/+/39033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie442f82cd1abcf7fa18295e782cccf26a7d30079 Gerrit-Change-Number: 39033 Gerrit-PatchSet: 1 Gerrit-Owner: Alexandre Rebert <alexandre.rebert(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/razer: Add initial support for the Blade Stealth (late 2019) [ICL]
by Daniel Maslowski (Code Review) 26 Feb '20

26 Feb '20

Daniel Maslowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37565 ) Change subject: mb/razer: Add initial support for the Blade Stealth (late 2019) [ICL] ...................................................................... Patch Set 16: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/37565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5711cbcd69813832d9bacc9563f651ab8702554a Gerrit-Change-Number: 37565 Gerrit-PatchSet: 16 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christoph Pomaska <github(a)slrie.de> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Shaleen jain <shaleen(a)jain.sh> Gerrit-Comment-Date: Wed, 26 Feb 2020 21:04:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/51nb/x210: update devicetree
by Matt DeVillier (Code Review) 26 Feb '20

26 Feb '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39141 ) Change subject: mb/51nb/x210: update devicetree ...................................................................... mb/51nb/x210: update devicetree - Add USB ports for SD card reader, fingerprint reader, and internal port. - Enable PcieRpClkReqSupport on NVMe root port, correct values for ClkReq/ClkSrc. - Remove hotplug support from PCIe root port used for WiFi Derived from x210_test branch of HarryKipper's repo: https://github.com/harrykipper/coreboot Change-Id: Ib64629ada4726e5edc080608f71a51f56a9b747c Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> mb/51nb/x210: enable NVMe PCIe ClkReq support Derived from x210_test branch of HarryKipper's repo: https://github.com/harrykipper/coreboot Change-Id: I2254ae4ef74735144a65ac2e922a5b69e51c2bbe Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> mb/51nb/x210: Derived from x210_test branch of HarryKipper's repo: https://github.com/harrykipper/coreboot Change-Id: If444a5ad5563b28fca384cc2e5040572cb686de7 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/51nb/x210/devicetree.cb 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/39141/1 diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index c67f3a3..c91ddd3 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -171,17 +171,19 @@ register "PcieRpClkSrcNumber[3]" = "1" register "PcieRpAdvancedErrorReporting[3]" = "1" register "PcieRpLtrEnable[3]" = "1" - register "PcieRpHotPlug[3]" = "1" register "PcieRpEnable[8]" = "1" # NVMe controller - register "PcieRpClkReqSupport[8]" = "0" - register "PcieRpClkReqNumber[8]" = "2" - register "PcieRpClkSrcNumber[8]" = "2" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "4" + register "PcieRpClkSrcNumber[8]" = "4" register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) + register "usb2_ports[2]" = "USB2_PORT_FLEX(OC1)" # FPR + register "usb2_ports[3]" = "USB2_PORT_FLEX(OC1)" # SD + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC1)" # INT register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # webcam register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # WiFi PCIe port USB -- To view, visit https://review.coreboot.org/c/coreboot/+/39141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If444a5ad5563b28fca384cc2e5040572cb686de7 Gerrit-Change-Number: 39141 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: payloads/tianocore: Enable PS2 keyboard module
by Matt DeVillier (Code Review) 26 Feb '20

26 Feb '20

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38960 ) Change subject: payloads/tianocore: Enable PS2 keyboard module ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/38960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6d468809142a0049ce1648217d62b070229ad6b Gerrit-Change-Number: 38960 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 26 Feb 2020 18:42:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch: reindent comment
by Patrick Georgi (Code Review) 26 Feb '20

26 Feb '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39118 ) Change subject: mb/google/hatch: reindent comment ...................................................................... mb/google/hatch: reindent comment Change-Id: I8c721c7ccba4f87d4acb9dae74213a46151fe2ed Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/google/hatch/variants/puff/include/variant/ec.h 1 file changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/39118/1 diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h index 1283763..2c2e62d 100644 --- a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h @@ -54,11 +54,10 @@ /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE -/** +/* * Defines EC wake pin route. - * Note that GPE_EC_WAKE is defined, confusingly, as - * GPE_LAN_WAK which is GPD2/LAN_WAKE# on the PCH or - * as the line EC_PCH_WAKE_ODL on the schematic. + * Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE# + * on the PCH or as the line EC_PCH_WAKE_ODL on the schematic. */ #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE -- To view, visit https://review.coreboot.org/c/coreboot/+/39118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c721c7ccba4f87d4acb9dae74213a46151fe2ed Gerrit-Change-Number: 39118 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2020