coreboot-gerrit February 2020

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Change in coreboot[master]: mb/asrock/h110m: remove the wrong comment about SATA
by Angel Pons (Code Review) 28 Feb '20

28 Feb '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39119 ) Change subject: mb/asrock/h110m: remove the wrong comment about SATA ...................................................................... Patch Set 9: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/39119/9/src/mainboard/asrock/h110m… File src/mainboard/asrock/h110m/devicetree.cb: https://review.coreboot.org/c/coreboot/+/39119/9/src/mainboard/asrock/h110m… PS9, Line 183: Max # of SATA 6.0 Gb/s Ports for H110 - 4 I would prefer if the original comment was extended. The thing is that SATA4 and SATA5 exist on the mainboard, but H110 only has four ports (so they would not work). This is because the same PCB design is reused to make models with better PCHs. For example: SATA4 and SATA5 are located in the lower right corner of the board, but they are not populated. This is because the same PCB is used to make boards with better PCHs, which can have up to six SATA ports. However, the H110 PCH only has four SATA ports, which explains why two connectors are missing. -- To view, visit https://review.coreboot.org/c/coreboot/+/39119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0a24fab22ee082367b82b3e8ee7383f1f02a4ad Gerrit-Change-Number: 39119 Gerrit-PatchSet: 9 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 28 Feb 2020 09:46:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2052
by Ronak Kanabar (Code Review) 28 Feb '20

28 Feb '20

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39130 ) Change subject: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2052 ...................................................................... vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2052 The FSP-M/S headers added are generated as per FSP v2052. Change-Id: Icb911418a6f8fe573b8d097b519c433e8ea6bd73 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h 2 files changed, 102 insertions(+), 111 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/39130/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h index cce959c..4018ed0 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2019, Intel Corporation. All rights reserved. +Copyright (c) 2020, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -74,18 +74,20 @@ **/ UINT32 MemorySpdPtr00; -/** Offset 0x0050 - Reserved +/** Offset 0x0050 - Memory SPD Pointer Channel 0 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ - UINT8 Reserved2[4]; + UINT32 MemorySpdPtr01; /** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 0 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ UINT32 MemorySpdPtr10; -/** Offset 0x0058 - Reserved +/** Offset 0x0058 - Memory SPD Pointer Channel 1 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ - UINT8 Reserved3[4]; + UINT32 MemorySpdPtr11; /** Offset 0x005C - Dq Byte Map CH0 Dq byte mapping between CPU and DRAM, Channel 0: board-dependent @@ -132,7 +134,7 @@ /** Offset 0x0096 - Reserved **/ - UINT8 Reserved4[6]; + UINT8 Reserved2[6]; /** Offset 0x009C - Intel Enhanced Debug Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied @@ -148,7 +150,7 @@ /** Offset 0x00A4 - Reserved **/ - UINT8 Reserved5[6]; + UINT8 Reserved3[6]; /** Offset 0x00AA - Enable SMBus Enable/disable SMBus controller. @@ -175,7 +177,7 @@ /** Offset 0x00B0 - Reserved **/ - UINT8 Reserved6[2]; + UINT8 Reserved4[2]; /** Offset 0x00B2 - Enable DCI ModPHY Pwoer Gate Enable ModPHY Pwoer Gate when DCI is enabled @@ -185,7 +187,7 @@ /** Offset 0x00B3 - Reserved **/ - UINT8 Reserved7; + UINT8 Reserved5; /** Offset 0x00B4 - PCH Trace Hub Mode Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' @@ -196,7 +198,7 @@ /** Offset 0x00B5 - Reserved **/ - UINT8 Reserved8[47]; + UINT8 Reserved6[47]; /** Offset 0x00E4 - Disable VT-d 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) @@ -206,7 +208,7 @@ /** Offset 0x00E5 - Reserved **/ - UINT8 Reserved9[3]; + UINT8 Reserved7[3]; /** Offset 0x00E8 - Internal Graphics Pre-allocated Memory Size of memory preallocated for internal graphics. @@ -224,7 +226,7 @@ /** Offset 0x00EA - Reserved **/ - UINT8 Reserved10; + UINT8 Reserved8; /** Offset 0x00EB - Board Type MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile @@ -235,7 +237,7 @@ /** Offset 0x00EC - Reserved **/ - UINT8 Reserved11[2]; + UINT8 Reserved9[2]; /** Offset 0x00EE - SA GV System Agent dynamic frequency support and when enabled memory will be training @@ -246,7 +248,7 @@ /** Offset 0x00EF - Reserved **/ - UINT8 Reserved12[5]; + UINT8 Reserved10[5]; /** Offset 0x00F4 - Rank Margin Tool Enable/disable Rank Margin Tool. @@ -256,7 +258,7 @@ /** Offset 0x00F5 - Reserved **/ - UINT8 Reserved13[24]; + UINT8 Reserved11[24]; /** Offset 0x010D - Memory Reference Clock 100MHz, 133MHz. @@ -266,7 +268,7 @@ /** Offset 0x010E - Reserved **/ - UINT8 Reserved14[26]; + UINT8 Reserved12[26]; /** Offset 0x0128 - Enable Intel HD Audio (Azalia) 0: Disable, 1: Enable (Default) Azalia controller @@ -283,7 +285,7 @@ /** Offset 0x012A - Reserved **/ - UINT8 Reserved15[98]; + UINT8 Reserved13[98]; /** Offset 0x018C - Program GPIOs for LFP on DDI port-A device 0=Disabled,1(Default)=eDP, 2=MIPI DSI @@ -293,7 +295,7 @@ /** Offset 0x018D - Reserved **/ - UINT8 Reserved16[2]; + UINT8 Reserved14[2]; /** Offset 0x018F - Enable or disable HPD of DDI port B 0=Disable, 1(Default)=Enable @@ -309,7 +311,7 @@ /** Offset 0x0191 - Reserved **/ - UINT8 Reserved17[5]; + UINT8 Reserved15[5]; /** Offset 0x0196 - Enable or disable DDC of DDI port B 0=Disable, 1(Default)=Enable @@ -325,7 +327,7 @@ /** Offset 0x0198 - Reserved **/ - UINT8 Reserved18[165]; + UINT8 Reserved16[165]; /** Offset 0x023D - C6DRAM power gating feature This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM @@ -337,7 +339,7 @@ /** Offset 0x023E - Reserved **/ - UINT8 Reserved19[7]; + UINT8 Reserved17[7]; /** Offset 0x0245 - CPU ratio value CPU ratio value. Valid Range 0 to 63 @@ -346,7 +348,7 @@ /** Offset 0x0246 - Reserved **/ - UINT8 Reserved20[4]; + UINT8 Reserved18[4]; /** Offset 0x024A - Enable or Disable VMX Enable or Disable VMX; 0: Disable; 1: Enable. @@ -356,7 +358,7 @@ /** Offset 0x024B - Reserved **/ - UINT8 Reserved21[31]; + UINT8 Reserved19[31]; /** Offset 0x026A - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable @@ -366,7 +368,7 @@ /** Offset 0x026B - Reserved **/ - UINT8 Reserved22[5]; + UINT8 Reserved20[5]; /** Offset 0x0270 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -380,7 +382,7 @@ /** Offset 0x0278 - Reserved **/ - UINT8 Reserved23[543]; + UINT8 Reserved21[543]; /** Offset 0x0497 - Usage type for ClkSrc 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use @@ -395,7 +397,7 @@ /** Offset 0x04B7 - Reserved **/ - UINT8 Reserved24[5]; + UINT8 Reserved22[5]; /** Offset 0x04BC - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 @@ -418,7 +420,7 @@ /** Offset 0x04C2 - Reserved **/ - UINT8 Reserved25[22]; + UINT8 Reserved23[22]; /** Offset 0x04D8 - Early Command Training Enables/Disable Early Command Training @@ -428,7 +430,7 @@ /** Offset 0x04D9 - Reserved **/ - UINT8 Reserved26[2]; + UINT8 Reserved24[2]; /** Offset 0x04DB - Read MPR Training Enables/Disable Read MPR Training @@ -438,7 +440,7 @@ /** Offset 0x04DC - Reserved **/ - UINT8 Reserved27[7]; + UINT8 Reserved25[7]; /** Offset 0x04E3 - Dimm ODT Training Enables/Disable Dimm ODT Training @@ -454,7 +456,7 @@ /** Offset 0x04E5 - Reserved **/ - UINT8 Reserved28; + UINT8 Reserved26; /** Offset 0x04E6 - Write Slew Rate Training Enables/Disable Write Slew Rate Training @@ -482,7 +484,7 @@ /** Offset 0x04EA - Reserved **/ - UINT8 Reserved29[3]; + UINT8 Reserved27[3]; /** Offset 0x04ED - Read Voltage Centering 2D Enables/Disable Read Voltage Centering 2D @@ -492,7 +494,7 @@ /** Offset 0x04EE - Reserved **/ - UINT8 Reserved30[3]; + UINT8 Reserved28[3]; /** Offset 0x04F1 - Turn Around Timing Training Enables/Disable Turn Around Timing Training @@ -502,7 +504,7 @@ /** Offset 0x04F2 - Reserved **/ - UINT8 Reserved31[6]; + UINT8 Reserved29[6]; /** Offset 0x04F8 - Receive Enable Centering 1D Enables/Disable Receive Enable Centering 1D @@ -518,7 +520,7 @@ /** Offset 0x04FA - Reserved **/ - UINT8 Reserved32[60]; + UINT8 Reserved30[60]; /** Offset 0x0536 - RAPL PL 1 WindowX Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) @@ -532,7 +534,7 @@ /** Offset 0x0538 - Reserved **/ - UINT8 Reserved33[2]; + UINT8 Reserved31[2]; /** Offset 0x053A - RAPL PL 1 Power range[0;2^14-1]= [2047.875;0]in W, (224= Def) @@ -541,7 +543,7 @@ /** Offset 0x053C - Reserved **/ - UINT8 Reserved34[68]; + UINT8 Reserved32[68]; /** Offset 0x0580 - LpDdrDqDqsReTraining Enables/Disable LpDdrDqDqsReTraining @@ -551,7 +553,7 @@ /** Offset 0x0581 - Reserved **/ - UINT8 Reserved35[172]; + UINT8 Reserved33[172]; /** Offset 0x062D - Enable HD Audio Link Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. @@ -561,7 +563,7 @@ /** Offset 0x062E - Reserved **/ - UINT8 Reserved36[3]; + UINT8 Reserved34[3]; /** Offset 0x0631 - Enable HD Audio DMIC_N Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. @@ -570,7 +572,7 @@ /** Offset 0x0633 - Reserved **/ - UINT8 Reserved37[17]; + UINT8 Reserved35[17]; /** Offset 0x0644 - Enable HD Audio DSP Enable/disable HD Audio DSP feature. @@ -580,7 +582,7 @@ /** Offset 0x0645 - Reserved **/ - UINT8 Reserved38[11]; + UINT8 Reserved36[11]; /** Offset 0x0650 - Enable HD Audio SSP0 Link Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 @@ -594,7 +596,7 @@ /** Offset 0x065A - Reserved **/ - UINT8 Reserved39[7]; + UINT8 Reserved37[7]; /** Offset 0x0661 - Skip MBP HOB Test, 0: disable, 1: enable, Enable/Disable MOB HOB. @@ -604,7 +606,7 @@ /** Offset 0x0662 - Reserved **/ - UINT8 Reserved40[22]; + UINT8 Reserved38[22]; } FSP_M_CONFIG; /** Fsp M UPD Configuration diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h index d01ae6a..e8e8f1c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2019, Intel Corporation. All rights reserved. +Copyright (c) 2020, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -422,20 +422,9 @@ /** Offset 0x0384 - Reserved **/ - UINT8 Reserved14[6]; + UINT8 Reserved14[146]; -/** Offset 0x038A - HECI3 state - The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. - 0: disable, 1: enable - $EN_DIS -**/ - UINT8 Heci3Enabled; - -/** Offset 0x038B - Reserved -**/ - UINT8 Reserved15[141]; - -/** Offset 0x0418 - CdClock Frequency selection +/** Offset 0x0416 - CdClock Frequency selection 0: (Default) Auto (Max based on reference clock frequency), 1: 172.8 Mhz, 2: 180 Mhz, 3: 190 Mhz, 4: 307.2 Mhz, 5: 312 Mhz, 6: 552 Mhz, 7: 556.8 Mhz, 8: 648 Mhz, 9: 652.8 Mhz @@ -444,109 +433,109 @@ **/ UINT8 CdClock; -/** Offset 0x0419 - Enable/Disable PeiGraphicsPeimInit +/** Offset 0x0417 - Enable/Disable PeiGraphicsPeimInit Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit $EN_DIS **/ UINT8 PeiGraphicsPeimInit; -/** Offset 0x041A - Reserved +/** Offset 0x0418 - Reserved **/ - UINT8 Reserved16[160]; + UINT8 Reserved15[152]; -/** Offset 0x04BA - Skip Multi-Processor Initialization +/** Offset 0x04B0 - Skip Multi-Processor Initialization When this is skipped, boot loader must initialize processors before SilicionInit API. 0: Initialize; 1: Skip $EN_DIS **/ UINT8 SkipMpInit; -/** Offset 0x04BB - Reserved +/** Offset 0x04B1 - Reserved **/ - UINT8 Reserved17[9]; + UINT8 Reserved16[11]; -/** Offset 0x04C4 - CpuMpPpi +/** Offset 0x04BC - CpuMpPpi Pointer for CpuMpPpi **/ UINT32 CpuMpPpi; -/** Offset 0x04C8 - Reserved +/** Offset 0x04C0 - Reserved **/ - UINT8 Reserved18[86]; + UINT8 Reserved17[86]; -/** Offset 0x051E - RTC Cmos Memory Lock +/** Offset 0x0516 - RTC Cmos Memory Lock Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM. $EN_DIS **/ UINT8 RtcMemoryLock; -/** Offset 0x051F - Reserved +/** Offset 0x0517 - Reserved **/ - UINT8 Reserved19[24]; + UINT8 Reserved18[24]; -/** Offset 0x0537 - Enable PCIE RP Pm Sci +/** Offset 0x052F - Enable PCIE RP Pm Sci Indicate whether the root port power manager SCI is enabled. **/ UINT8 PcieRpPmSci[24]; -/** Offset 0x054F - Reserved +/** Offset 0x0547 - Reserved **/ - UINT8 Reserved20[24]; + UINT8 Reserved19[24]; -/** Offset 0x0567 - Enable PCIE RP Clk Req Detect +/** Offset 0x055F - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management. **/ UINT8 PcieRpClkReqDetect[24]; -/** Offset 0x057F - Reserved +/** Offset 0x0577 - Reserved **/ - UINT8 Reserved21[455]; + UINT8 Reserved20[455]; -/** Offset 0x0746 - PCH Pm Slp S3 Min Assert +/** Offset 0x073E - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. **/ UINT8 PchPmSlpS3MinAssert; -/** Offset 0x0747 - Reserved +/** Offset 0x073F - Reserved **/ - UINT8 Reserved22; + UINT8 Reserved21; -/** Offset 0x0748 - PCH Pm Slp Sus Min Assert +/** Offset 0x0740 - PCH Pm Slp Sus Min Assert SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. **/ UINT8 PchPmSlpSusMinAssert; -/** Offset 0x0749 - PCH Pm Slp A Min Assert +/** Offset 0x0741 - PCH Pm Slp A Min Assert SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. **/ UINT8 PchPmSlpAMinAssert; -/** Offset 0x074A - Reserved +/** Offset 0x0742 - Reserved **/ - UINT8 Reserved23[11]; + UINT8 Reserved22[11]; -/** Offset 0x0755 - PCH Sata Pwr Opt Enable +/** Offset 0x074D - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. $EN_DIS **/ UINT8 SataPwrOptEnable; -/** Offset 0x0756 - Reserved +/** Offset 0x074E - Reserved **/ - UINT8 Reserved24[146]; + UINT8 Reserved23[146]; -/** Offset 0x07E8 - USB2 Port Over Current Pin +/** Offset 0x07E0 - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. **/ UINT8 Usb2OverCurrentPin[16]; -/** Offset 0x07F8 - USB3 Port Over Current Pin +/** Offset 0x07F0 - USB3 Port Over Current Pin Describe the specific over current pin number of USB 3.0 Port N. **/ UINT8 Usb3OverCurrentPin[10]; -/** Offset 0x0802 - Enable 8254 Static Clock Gating +/** Offset 0x07FA - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support legacy OS using 8254 timer. Also enable this while S0ix is enabled. @@ -554,7 +543,7 @@ **/ UINT8 Enable8254ClockGating; -/** Offset 0x0803 - Enable 8254 Static Clock Gating On S3 +/** Offset 0x07FB - Enable 8254 Static Clock Gating On S3 This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming. @@ -562,21 +551,21 @@ **/ UINT8 Enable8254ClockGatingOnS3; -/** Offset 0x0804 - Reserved +/** Offset 0x07FC - Reserved **/ - UINT8 Reserved25[531]; + UINT8 Reserved24[511]; -/** Offset 0x0A17 - Enable/Disable IGFX PmSupport +/** Offset 0x09FB - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport $EN_DIS **/ UINT8 PmSupport; -/** Offset 0x0A18 - Reserved +/** Offset 0x09FC - Reserved **/ - UINT8 Reserved26[32]; + UINT8 Reserved25[32]; -/** Offset 0x0A38 - TCC Activation Offset +/** Offset 0x0A1C - TCC Activation Offset TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For SKL Y SKU, the recommended default for this policy is @@ -584,50 +573,50 @@ **/ UINT8 TccActivationOffset; -/** Offset 0x0A39 - Reserved +/** Offset 0x0A1D - Reserved **/ - UINT8 Reserved27[34]; + UINT8 Reserved26[34]; -/** Offset 0x0A5B - Enable or Disable CPU power states (C-states) +/** Offset 0x0A3F - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable $EN_DIS **/ UINT8 Cx; -/** Offset 0x0A5C - Reserved +/** Offset 0x0A40 - Reserved **/ - UINT8 Reserved28[74]; + UINT8 Reserved27[74]; -/** Offset 0x0AA6 - Platform Power Pmax +/** Offset 0x0A8A - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. Range 0-1024 Watts. Value of 800 = 100W **/ UINT16 PsysPmax; -/** Offset 0x0AA8 - Reserved +/** Offset 0x0A8C - Reserved **/ - UINT8 Reserved29[116]; + UINT8 Reserved28[116]; -/** Offset 0x0B1C - End of Post message +/** Offset 0x0B00 - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved **/ UINT8 EndOfPostMessage; -/** Offset 0x0B1D - Reserved +/** Offset 0x0B01 - Reserved **/ - UINT8 Reserved30[3]; + UINT8 Reserved29[3]; -/** Offset 0x0B20 - Unlock all GPIO pads +/** Offset 0x0B04 - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose. $EN_DIS **/ UINT8 PchUnlockGpioPads; -/** Offset 0x0B21 - Reserved +/** Offset 0x0B05 - Reserved **/ - UINT8 Reserved31[447]; + UINT8 Reserved30[451]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -642,11 +631,11 @@ **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0CE0 +/** Offset 0x0CC8 **/ - UINT8 UnusedUpdSpace37[6]; + UINT8 UnusedUpdSpace36[6]; -/** Offset 0x0CE6 +/** Offset 0x0CCE **/ UINT16 UpdTerminator; } FSPS_UPD; -- To view, visit https://review.coreboot.org/c/coreboot/+/39130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb911418a6f8fe573b8d097b519c433e8ea6bd73 Gerrit-Change-Number: 39130 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/google/hatch/puff: Toggle on TetonGlacierMode
by Edward O'Callaghan (Code Review) 28 Feb '20

28 Feb '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39041 ) Change subject: mainboard/google/hatch/puff: Toggle on TetonGlacierMode ...................................................................... mainboard/google/hatch/puff: Toggle on TetonGlacierMode Leverage in Puff to avoid diskswap variants. Later this could become part of the baseboard definition and hatch diskswap variants migrated over to use it as well. BUG=b:149171631 BRANCH=none TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration on Puff. Change-Id: Ie87f0823f28457db397d495d9f1629d85cfd5215 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/puff/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/39041/1 diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index 4ffbfed..cca2d41 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -2,6 +2,9 @@ # Enable heci communication register "HeciEnabled" = "1" + # Auto-switch between X4 NVMe and X2 NVMe. + register "TetonGlacierMode" = "1" + register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, @@ -166,6 +169,9 @@ # PCIe port 7 for LAN register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" + # PCIe port 11 (x2) for NVMe hybrid storage devices + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" @@ -281,6 +287,7 @@ end end # FSP requires func0 be enabled. device pci 1c.6 on end # RTL8111H Ethernet NIC (becomes RP1). + device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) device pci 1e.3 off end # GSPI #1 end -- To view, visit https://review.coreboot.org/c/coreboot/+/39041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie87f0823f28457db397d495d9f1629d85cfd5215 Gerrit-Change-Number: 39041 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/hatch: Enable TetonGlacierMode on Puff
by Edward O'Callaghan (Code Review) 28 Feb '20

28 Feb '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38846 ) Change subject: mainboard/hatch: Enable TetonGlacierMode on Puff ...................................................................... mainboard/hatch: Enable TetonGlacierMode on Puff Allow for reconfiguring the PCIe lanes at runtime. BUG=b:149171631 BRANCH=none TEST=none Change-Id: Id9a72161494db6a4da4abd3302b06df7c70634ab Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/puff/overridetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/38846/1 diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index 4ffbfed..09c109a 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -2,6 +2,9 @@ # Enable heci communication register "HeciEnabled" = "1" + # Auto-switch between X4 NVMe and X2 NVMe. + register "TetonGlacierMode" = "1" + register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, @@ -281,6 +284,7 @@ end end # FSP requires func0 be enabled. device pci 1c.6 on end # RTL8111H Ethernet NIC (becomes RP1). + device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) device pci 1e.3 off end # GSPI #1 end -- To view, visit https://review.coreboot.org/c/coreboot/+/38846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9a72161494db6a4da4abd3302b06df7c70634ab Gerrit-Change-Number: 38846 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: mainboard/google/hatch: Migrate hatch onto SKU ID helpers
by Edward O'Callaghan (Code Review) 28 Feb '20

28 Feb '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39019 ) Change subject: mainboard/google/hatch: Migrate hatch onto SKU ID helpers ...................................................................... mainboard/google/hatch: Migrate hatch onto SKU ID helpers Change-Id: I96e10010fd375b127f1e10387d6f7a839bc35fdd Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/mainboard.c M src/mainboard/google/hatch/variants/akemi/gpio.c M src/mainboard/google/hatch/variants/akemi/variant.c M src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/hatch/variants/dratini/variant.c M src/mainboard/google/hatch/variants/kindred/gpio.c M src/mainboard/google/hatch/variants/kindred/variant.c 8 files changed, 10 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/39019/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 783ec73..4d79066 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -130,4 +130,8 @@ select VBOOT_EARLY_EC_SYNC select VBOOT_LID_SWITCH +config EC_GOOGLE_CHROMEEC_SKU_ID_MAX + int + default 0xff # LEGACY SKU_ID space. + endif # BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/mainboard.c b/src/mainboard/google/hatch/mainboard.c index 5761b08..888acf7 100644 --- a/src/mainboard/google/hatch/mainboard.c +++ b/src/mainboard/google/hatch/mainboard.c @@ -21,36 +21,9 @@ #include <string.h> #include <stdint.h> -#define SKU_UNKNOWN 0xFFFFFFFF -#define SKU_MAX 255 - -uint32_t get_board_sku(void) -{ - static uint32_t sku_id = SKU_UNKNOWN; - - if (sku_id != SKU_UNKNOWN) - return sku_id; - - if (google_chromeec_cbi_get_sku_id(&sku_id)) - sku_id = SKU_UNKNOWN; - - return sku_id; -} - const char *smbios_system_sku(void) { - static char sku_str[7]; /* sku{0..255} */ - uint32_t sku_id = get_board_sku(); - - if ((sku_id == SKU_UNKNOWN) || (sku_id > SKU_MAX)) { - printk(BIOS_ERR, "%s: Unexpected SKU ID %u\n", - __func__, sku_id); - return ""; - } - - snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); - - return sku_str; + return google_chromeec_smbios_system_sku(); } const char *smbios_mainboard_manufacturer(void) diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c index cfc185e..5df011a 100644 --- a/src/mainboard/google/hatch/variants/akemi/gpio.c +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -136,7 +136,7 @@ const struct pad_config *override_gpio_table(size_t *num) { - uint32_t sku_id = get_board_sku(); + uint32_t sku_id = google_chromeec_get_board_sku(); /* For SSD SKU */ if ((sku_id == 2) || (sku_id == 4)) { *num = ARRAY_SIZE(ssd_sku_gpio_table); diff --git a/src/mainboard/google/hatch/variants/akemi/variant.c b/src/mainboard/google/hatch/variants/akemi/variant.c index 8440b5c..2965659 100644 --- a/src/mainboard/google/hatch/variants/akemi/variant.c +++ b/src/mainboard/google/hatch/variants/akemi/variant.c @@ -28,7 +28,7 @@ ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA); /* SKU ID 2 and 4 do not have eMMC, hence disable it. */ - sku_id = get_board_sku(); + sku_id = google_chromeec_get_board_sku(); if ((sku_id == 2) || (sku_id == 4)) { if (emmc_host == NULL) return; diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h index 9d1b91e..c780b97 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h @@ -44,9 +44,6 @@ /* Return ChromeOS gpio table and fill in number of entries. */ const struct cros_gpio *variant_cros_gpios(size_t *num); -/* Return board SKU */ -uint32_t get_board_sku(void); - /* Modify devictree settings during ramstage. */ void variant_devtree_update(void); diff --git a/src/mainboard/google/hatch/variants/dratini/variant.c b/src/mainboard/google/hatch/variants/dratini/variant.c index 3a51a55..8689113 100644 --- a/src/mainboard/google/hatch/variants/dratini/variant.c +++ b/src/mainboard/google/hatch/variants/dratini/variant.c @@ -20,7 +20,7 @@ const char *get_wifi_sar_cbfs_filename(void) { const char *filename = NULL; - uint32_t sku_id = get_board_sku(); + uint32_t sku_id = google_chromeec_get_board_sku(); switch (sku_id) { case SKU_21_DRAGONAIR: diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c index fbb47f9..37789e9 100644 --- a/src/mainboard/google/hatch/variants/kindred/gpio.c +++ b/src/mainboard/google/hatch/variants/kindred/gpio.c @@ -191,7 +191,7 @@ const struct pad_config *override_gpio_table(size_t *num) { - uint32_t sku_id = get_board_sku(); + uint32_t sku_id = google_chromeec_get_board_sku(); /* For SSD SKU */ if (sku_id == 1 || sku_id == 3 || sku_id == 23 || sku_id == 24) { *num = ARRAY_SIZE(ssd_sku_gpio_table); diff --git a/src/mainboard/google/hatch/variants/kindred/variant.c b/src/mainboard/google/hatch/variants/kindred/variant.c index 1e1d083..f264868 100644 --- a/src/mainboard/google/hatch/variants/kindred/variant.c +++ b/src/mainboard/google/hatch/variants/kindred/variant.c @@ -28,7 +28,7 @@ ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA); /* SKU ID 1/3/23/24 doesn't have a eMMC device, hence disable it. */ - sku_id = get_board_sku(); + sku_id = google_chromeec_get_board_sku(); if (sku_id == 1 || sku_id == 3 || sku_id == 23 || sku_id == 24) { if (emmc_host == NULL) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/39019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96e10010fd375b127f1e10387d6f7a839bc35fdd Gerrit-Change-Number: 39019 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: ec/google/chromeec: Introduce SKU_ID helpers
by Edward O'Callaghan (Code Review) 28 Feb '20

28 Feb '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39018 ) Change subject: ec/google/chromeec: Introduce SKU_ID helpers ...................................................................... ec/google/chromeec: Introduce SKU_ID helpers Change-Id: I805b25465a3b4ee3dc0cbda5feb9e9ea2493ff9e Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/ec/google/chromeec/Kconfig M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_boardid.c 3 files changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/39018/1 diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index b33864f..5616d94 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -100,6 +100,11 @@ hex default 0x0 +# set to 0xff for LEGACY +config EC_GOOGLE_CHROMEEC_SKU_ID_MAX + hex + default 0x7fffffff + config EC_GOOGLE_CHROMEEC_BOARDNAME depends on EC_GOOGLE_CHROMEEC string "Chrome EC board name for EC" diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 5ce375e..f5c2e1a 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -88,6 +88,9 @@ int google_chromeec_cbi_get_dram_part_num(char *buf, size_t bufsize); int google_chromeec_cbi_get_oem_name(char *buf, size_t bufsize); +uint32_t google_chromeec_get_board_sku(void); +const char *google_chromeec_smbios_system_sku(void); + /* MEC uses 0x800/0x804 as register/index pair, thus an 8-byte resource. */ #define MEC_EMI_BASE 0x800 #define MEC_EMI_SIZE 8 diff --git a/src/ec/google/chromeec/ec_boardid.c b/src/ec/google/chromeec/ec_boardid.c index 1307ce1..aa191c3 100644 --- a/src/ec/google/chromeec/ec_boardid.c +++ b/src/ec/google/chromeec/ec_boardid.c @@ -27,3 +27,35 @@ return id; } + +#define SKU_UNKNOWN 0xFFFFFFFF + +uint32_t google_chromeec_get_board_sku(void) +{ + static uint32_t sku_id = SKU_UNKNOWN; + + if (sku_id != SKU_UNKNOWN) + return sku_id; + + if (google_chromeec_cbi_get_sku_id(&sku_id)) + sku_id = SKU_UNKNOWN; + + return sku_id; +} + +const char *google_chromeec_smbios_system_sku(void) +{ + static char sku_str[7]; /* sku{0..255} */ + uint32_t sku_id = get_board_sku(); + + if ((sku_id == SKU_UNKNOWN) || + (sku_id > CONFIG_EC_GOOGLE_CHROMEEC_SKU_MAX)) { + printk(BIOS_ERR, "%s: Unexpected SKU ID %u\n", + __func__, sku_id); + return ""; + } + + snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); + + return sku_str; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/39018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I805b25465a3b4ee3dc0cbda5feb9e9ea2493ff9e Gerrit-Change-Number: 39018 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 29

Change in coreboot[master]: Jinlon: Configure GPP_E0 as output
by Rajat Jain (Code Review) 28 Feb '20

28 Feb '20

Rajat Jain has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39144 ) Change subject: Jinlon: Configure GPP_E0 as output ...................................................................... Jinlon: Configure GPP_E0 as output Configure GPP_E0 as output on Jinlon Change-Id: Iad640eed855b47e365da55fa994c6a3c4c38caf9 Signed-off-by: Rajat Jain <rajatja(a)google.com>. --- M src/mainboard/google/hatch/variants/jinlon/gpio.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/39144/1 diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 2bf97b1..c584d94 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -31,6 +31,8 @@ * using this pin, expose this pin to driver. */ PAD_CFG_GPO(GPP_C15, 1, DEEP), + /* E0 : View Angle Management */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), /* F3 : MEM_STRAP_3 */ PAD_CFG_GPI(GPP_F3, NONE, PLTRST), /* F10 : MEM_STRAP_2 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad640eed855b47e365da55fa994c6a3c4c38caf9 Gerrit-Change-Number: 39144 Gerrit-PatchSet: 1 Gerrit-Owner: Rajat Jain <rajatja(a)google.com> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: mb/google/dedede: Enable ESPI configure IO decode range for chrome EC
by Aamir Bohra (Code Review) 27 Feb '20

27 Feb '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39121 ) Change subject: mb/google/dedede: Enable ESPI configure IO decode range for chrome EC ...................................................................... mb/google/dedede: Enable ESPI configure IO decode range for chrome EC Configure below ESPI IO decode ranges: 1. 0x200-020F: EC host command range. 2. 0x800-0x8FF: EC host command args and params. 3. 0x900-0x9ff: EC memory map range. Change-Id: I1e450d6e45242180de715746b9852634de2669c6 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39121/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index c17620b..03fea79 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -19,6 +19,12 @@ register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_H" + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + # USB Port Configuration register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C0 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C1 -- To view, visit https://review.coreboot.org/c/coreboot/+/39121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e450d6e45242180de715746b9852634de2669c6 Gerrit-Change-Number: 39121 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

7 15

Change in coreboot[master]: mb/google/dedede: Enable display support
by Aamir Bohra (Code Review) 27 Feb '20

27 Feb '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39132 ) Change subject: mb/google/dedede: Enable display support ...................................................................... mb/google/dedede: Enable display support Changelist: 1. Enable Internal Gfx device. 2. Configure DDI0 for EDP. 3. Configure HPD and DDC suppport for DDI1/DDI2. 4. Configure HPD GPIOs. BUG=none TEST=Verify display on EDP panel Change-Id: Ia53428af549ba01ab539f9474a6e5e79b72dff5c Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c 2 files changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/39132/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 346a309..25ea419 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -72,6 +72,17 @@ # Enable EMMC HS400 mode register "ScsEmmcHs400Enabled" = "1" + # Display related UPDs + # Select eDP for port A + register "DdiPortAConfig" = "1" + + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -110,7 +121,7 @@ device domain 0 on device pci 00.0 on end # Host Bridge - device pci 02.0 off end # Integrated Graphics Device + device pci 02.0 on end # Integrated Graphics Device device pci 04.0 off end # SA Thermal device device pci 05.0 off end # IPU device pci 09.0 off end # Intel Trace Hub diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index fa975e7..b8ceae2 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -27,6 +27,8 @@ PAD_NC(GPP_A13, NONE), /* A14 : USB_OC3_N */ PAD_NC(GPP_A14, NONE), + /* A16 : EC_AP_USB_C0_HPD */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* A18 : USB_OC0_N */ PAD_NC(GPP_A18, NONE), @@ -40,6 +42,8 @@ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* B23 : EC_AP_USB_C1_HDMI_HPD */ + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1), /* C16 : AP_I2C_TRACKPAD_SDA_3V3 */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), -- To view, visit https://review.coreboot.org/c/coreboot/+/39132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia53428af549ba01ab539f9474a6e5e79b72dff5c Gerrit-Change-Number: 39132 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

7 13

Change in coreboot[master]: soc/intel/apl: disable NPK device in devicetree.cb
by Paul Menzel (Code Review) 27 Feb '20

27 Feb '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38814 ) Change subject: soc/intel/apl: disable NPK device in devicetree.cb ...................................................................... Patch Set 13: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/38814/13/src/soc/intel/apollolake/… File src/soc/intel/apollolake/romstage.c: https://review.coreboot.org/c/coreboot/+/38814/13/src/soc/intel/apollolake/… PS13, Line 295: #if CONFIG(SOC_INTEL_GLK) Can C if statement be used? -- To view, visit https://review.coreboot.org/c/coreboot/+/38814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910245d4ff35a6a0a9059fb6911d4426cdb999b6 Gerrit-Change-Number: 38814 Gerrit-PatchSet: 13 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Thu, 27 Feb 2020 17:20:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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