coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/xeon_sp: Enable SMI handler
by Rocky Phagura (Code Review) 12 Nov '20

12 Nov '20

Rocky Phagura has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46231 ) Change subject: soc/intel/xeon_sp: Enable SMI handler ...................................................................... Patch Set 26: > Patch Set 24: > > > Patch Set 24: > > > > (1 comment) > > > > Does the TCO, gnvs, and smbsus changes belong in this patch? Maybe explain in the commit message if they do. > > soc/intel/common has some dependencies which is what I suspect drove those changes. IDK if there is even TCO on these? GNVS is fully broken on this platform, but needs separate fixing (or actual implementing). No idea about smbus. > > I have some local improvements I want to push soon, like less skx/cpx boilerplate + proper IED handling. So maybe hold off on merging for a day or two? TCO is not used, but the common block code assumes the support is there. Hence, I had to put in the ifdef's. Regarding, smbus.h, it's required by common block SMM code also. -- To view, visit https://review.coreboot.org/c/coreboot/+/46231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Gerrit-Change-Number: 46231 Gerrit-PatchSet: 26 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 12 Nov 2020 05:29:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add PCH ID 0x5181
by Subrata Banik (Code Review) 12 Nov '20

12 Nov '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47474 ) Change subject: soc/intel/alderlake: Add PCH ID 0x5181 ...................................................................... soc/intel/alderlake: Add PCH ID 0x5181 List of changes: 1. Add new PCH ID 0x5181 into device/pci_ids.h 2. Update new PCH ID into common lpc.c 3. Add new PCH ID description into report_platform.c TEST=Able to build and boot ADLRVP with new PCH ID. Change-Id: I4343b7343876eb40c2955f6f4dd99d6446852dc0 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/common/block/lpc/lpc.c 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/47474/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 36c5dc6..675acc4 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2926,6 +2926,7 @@ #define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_29 0x7a1d #define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30 0x7a1e #define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31 0x7a1f +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32 0x5181 #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_0 0x7a80 #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_1 0x7a81 #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_2 0x7a82 diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 38e909c..f0d8f2b 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -78,6 +78,7 @@ { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_29, "Alderlake-P SKU" }, { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30, "Alderlake-P SKU" }, { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32, "Alderlake-P SKU" }, }; static struct { diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 28c030f..d11aa10 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -305,6 +305,7 @@ PCI_DEVICE_ID_INTEL_ADP_S_ESPI_29, PCI_DEVICE_ID_INTEL_ADP_S_ESPI_30, PCI_DEVICE_ID_INTEL_ADP_S_ESPI_31, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/47474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4343b7343876eb40c2955f6f4dd99d6446852dc0 Gerrit-Change-Number: 47474 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: mb/google/dedede/var/drawcia: Change elan USI touchscreen to level tr...
by Chen Wisley (Code Review) 12 Nov '20

12 Nov '20

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47292 ) Change subject: mb/google/dedede/var/drawcia: Change elan USI touchscreen to level trigger ...................................................................... mb/google/dedede/var/drawcia: Change elan USI touchscreen to level trigger Per elan request, change to level trigger to fix touchscreen function lost. BUG=none TEST=emerge-dedede coreboot Change-Id: I25953a26142eb7a66781fef9bb98c719bab6297f Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/47292/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 5942121..ff2a02a 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -199,7 +199,7 @@ chip drivers/i2c/hid register "generic.hid" = ""ELAN2513"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" register "generic.reset_delay_ms" = "20" -- To view, visit https://review.coreboot.org/c/coreboot/+/47292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25953a26142eb7a66781fef9bb98c719bab6297f Gerrit-Change-Number: 47292 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

3 13

Change in coreboot[master]: Delete soc/qualcomm/sdm845
by Julius Werner (Code Review) 12 Nov '20

12 Nov '20

Hello Patrick Georgi, Stefan Reinauer, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47428 to review the following change. Change subject: Delete soc/qualcomm/sdm845 ...................................................................... Delete soc/qualcomm/sdm845 Work on this SoC was abandoned and never finished. It's not really usable in its current state, so let's get rid of it. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I23453e3e47ac336ab61687004470e5e79172cafe --- D src/soc/qualcomm/sdm845/Kconfig D src/soc/qualcomm/sdm845/Makefile.inc D src/soc/qualcomm/sdm845/aop_load_reset.c D src/soc/qualcomm/sdm845/bootblock.c D src/soc/qualcomm/sdm845/cbmem.c D src/soc/qualcomm/sdm845/clock.c D src/soc/qualcomm/sdm845/gpio.c D src/soc/qualcomm/sdm845/include/soc/addressmap.h D src/soc/qualcomm/sdm845/include/soc/aop.h D src/soc/qualcomm/sdm845/include/soc/clock.h D src/soc/qualcomm/sdm845/include/soc/efuse.h D src/soc/qualcomm/sdm845/include/soc/gpio.h D src/soc/qualcomm/sdm845/include/soc/mmu.h D src/soc/qualcomm/sdm845/include/soc/qspi.h D src/soc/qualcomm/sdm845/include/soc/symbols.h D src/soc/qualcomm/sdm845/include/soc/usb.h D src/soc/qualcomm/sdm845/memlayout.ld D src/soc/qualcomm/sdm845/mmu.c D src/soc/qualcomm/sdm845/qclib.c D src/soc/qualcomm/sdm845/qspi.c D src/soc/qualcomm/sdm845/soc.c D src/soc/qualcomm/sdm845/spi.c D src/soc/qualcomm/sdm845/timer.c D src/soc/qualcomm/sdm845/uart_bitbang.c D src/soc/qualcomm/sdm845/usb.c M util/docker/coreboot.org-status/board-status.html/tohtml.sh D util/qualcomm/scripts/cmm/debug_cb_845.cmm 27 files changed, 0 insertions(+), 2,747 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/47428/1 diff --git a/src/soc/qualcomm/sdm845/Kconfig b/src/soc/qualcomm/sdm845/Kconfig deleted file mode 100644 index 2b9bef3..0000000 --- a/src/soc/qualcomm/sdm845/Kconfig +++ /dev/null @@ -1,36 +0,0 @@ - -config SOC_QUALCOMM_SDM845 - bool - default n - select ARCH_BOOTBLOCK_ARMV8_64 - select ARCH_RAMSTAGE_ARMV8_64 - select ARCH_ROMSTAGE_ARMV8_64 - select ARCH_VERSTAGE_ARMV8_64 - select GENERIC_GPIO_LIB - select ARM64_USE_ARCH_TIMER - select SOC_QUALCOMM_COMMON - select CACHE_MRC_SETTINGS - -if SOC_QUALCOMM_SDM845 - -config MEMLAYOUT_LD_FILE - string - default "src/soc/qualcomm/sdm845/memlayout.ld" - -config VBOOT - select VBOOT_SEPARATE_VERSTAGE - select VBOOT_RETURN_FROM_VERSTAGE - select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_STARTS_IN_BOOTBLOCK - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN - -config SDM845_QSPI - bool - default y if COMMON_CBFS_SPI_WRAPPER - prompt "Build Flash Using SPI-NOR" - -config BOOT_DEVICE_SPI_FLASH_BUS - int - default 16 - -endif diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc deleted file mode 100644 index 4449a69..0000000 --- a/src/soc/qualcomm/sdm845/Makefile.inc +++ /dev/null @@ -1,50 +0,0 @@ - -ifeq ($(CONFIG_SOC_QUALCOMM_SDM845),y) - -################################################################################ -bootblock-y += bootblock.c -bootblock-y += spi.c -bootblock-y += mmu.c -bootblock-y += timer.c -bootblock-y += gpio.c -bootblock-y += clock.c -bootblock-$(CONFIG_SDM845_QSPI) += qspi.c - -################################################################################ -verstage-y += spi.c -verstage-y += timer.c -verstage-y += gpio.c -verstage-y += clock.c -verstage-$(CONFIG_SDM845_QSPI) += qspi.c - -################################################################################ -romstage-y += spi.c -romstage-y += cbmem.c -romstage-y += timer.c -romstage-y += gpio.c -romstage-y += clock.c -romstage-$(CONFIG_SDM845_QSPI) += qspi.c -romstage-y += usb.c -romstage-y += ../common/qclib.c -romstage-y += qclib.c -romstage-y += ../common/mmu.c -romstage-y += mmu.c - -################################################################################ -ramstage-y += soc.c -ramstage-y += spi.c -ramstage-y += timer.c -ramstage-y += gpio.c -ramstage-y += clock.c -ramstage-$(CONFIG_SDM845_QSPI) += qspi.c -ramstage-y += usb.c -ramstage-y += gpio.c -ramstage-y += clock.c -ramstage-y += aop_load_reset.c - -################################################################################ - -CPPFLAGS_common += -Isrc/soc/qualcomm/sdm845/include -CPPFLAGS_common += -Isrc/soc/qualcomm/common/include - -endif diff --git a/src/soc/qualcomm/sdm845/aop_load_reset.c b/src/soc/qualcomm/sdm845/aop_load_reset.c deleted file mode 100644 index eb90f86..0000000 --- a/src/soc/qualcomm/sdm845/aop_load_reset.c +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cbfs.h> -#include <console/console.h> -#include <soc/mmu.h> -#include <soc/aop.h> -#include <soc/clock.h> - -void aop_fw_load_reset(void) -{ - bool aop_fw_entry; - - struct prog aop_fw_prog = - PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/aop"); - - if (prog_locate(&aop_fw_prog)) - die("SOC image: AOP_FW not found"); - - aop_fw_entry = selfload(&aop_fw_prog); - if (!aop_fw_entry) - die("SOC image: AOP load failed"); - - clock_reset_aop(); - - printk(BIOS_DEBUG, "\nSOC:AOP brought out of reset.\n"); -} diff --git a/src/soc/qualcomm/sdm845/bootblock.c b/src/soc/qualcomm/sdm845/bootblock.c deleted file mode 100644 index 9db015f..0000000 --- a/src/soc/qualcomm/sdm845/bootblock.c +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootblock_common.h> -#include <soc/mmu.h> -#include <soc/clock.h> -#include <soc/qspi.h> - -void bootblock_soc_init(void) -{ - clock_init(); - sdm845_mmu_init(); - quadspi_init(25 * MHz); -} diff --git a/src/soc/qualcomm/sdm845/cbmem.c b/src/soc/qualcomm/sdm845/cbmem.c deleted file mode 100644 index 4b9eb37..0000000 --- a/src/soc/qualcomm/sdm845/cbmem.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cbmem.h> - -void *cbmem_top_chipset(void) -{ - return (void *)((uintptr_t)4 * GiB); -} diff --git a/src/soc/qualcomm/sdm845/clock.c b/src/soc/qualcomm/sdm845/clock.c deleted file mode 100644 index 917d11f..0000000 --- a/src/soc/qualcomm/sdm845/clock.c +++ /dev/null @@ -1,218 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/mmio.h> -#include <types.h> -#include <commonlib/helpers.h> -#include <assert.h> -#include <soc/symbols.h> -#include <soc/clock.h> - -#define DIV(div) (2*div - 1) - -#define AOP_LOADED_SIGNAL_FLAG 0x11223344 - -struct clock_config qup_cfg[] = { - { - .hz = 7372800, - .src = SRC_GPLL0_EVEN_300MHZ, - .div = DIV(1), - .m = 384, - .n = 15625, - .d_2 = 15625, - }, - { - .hz = 19200*KHz, - .src = SRC_XO_19_2MHZ, - .div = DIV(1), - } -}; - -struct clock_config qspi_core_cfg[] = { - { - .hz = 19200*KHz, - .src = SRC_XO_19_2MHZ, - .div = DIV(0), - }, - { - .hz = 100*MHz, - .src = SRC_GPLL0_MAIN_600MHZ, - .div = DIV(6), - }, - { - .hz = 150*MHz, - .src = SRC_GPLL0_MAIN_600MHZ, - .div = DIV(4), - }, - { - .hz = 300*MHz, - .src = SRC_GPLL0_MAIN_600MHZ, - .div = DIV(2), - } -}; - -static int clock_configure_gpll0(void) -{ - /* Keep existing GPLL0 configuration, in RUN mode @600Mhz. */ - setbits32(&gcc->gpll0.user_ctl, - 1 << CLK_CTL_GPLL_PLLOUT_EVEN_SHFT | - 1 << CLK_CTL_GPLL_PLLOUT_MAIN_SHFT | - 1 << CLK_CTL_GPLL_PLLOUT_ODD_SHFT); - return 0; -} - -static int clock_configure_mnd(struct sdm845_clock *clk, uint32_t m, uint32_t n, - uint32_t d_2) -{ - setbits32(&clk->rcg.cfg, - RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); - - write32(&clk->m, m & CLK_CTL_RCG_MND_BMSK); - write32(&clk->n, ~(n-m) & CLK_CTL_RCG_MND_BMSK); - write32(&clk->d_2, ~(d_2) & CLK_CTL_RCG_MND_BMSK); - - return 0; -} - -static int clock_configure(struct sdm845_clock *clk, - struct clock_config *clk_cfg, - uint32_t hz, uint32_t num_perfs) -{ - uint32_t reg_val; - uint32_t idx; - - for (idx = 0; idx < num_perfs; idx++) - if (hz <= clk_cfg[idx].hz) - break; - - assert(hz == clk_cfg[idx].hz); - - reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | - (clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); - - /* Set clock config */ - write32(&clk->rcg.cfg, reg_val); - - if (clk_cfg[idx].m != 0) - clock_configure_mnd(clk, clk_cfg[idx].m, clk_cfg[idx].n, - clk_cfg[idx].d_2); - - /* Commit config to RCG*/ - setbits32(&clk->rcg.cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); - - return 0; -} - -static bool clock_is_off(u32 *cbcr_addr) -{ - return (read32(cbcr_addr) & CLK_CTL_CBC_CLK_OFF_BMSK); -} - -static int clock_enable_vote(void *cbcr_addr, void *vote_addr, - uint32_t vote_bit) -{ - - /* Set clock vote bit */ - setbits32(vote_addr, BIT(vote_bit)); - - /* Ensure clock is enabled */ - while (clock_is_off(cbcr_addr)) - ; - - return 0; -} - -static int clock_enable(void *cbcr_addr) -{ - - /* Set clock enable bit */ - setbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); - - /* Ensure clock is enabled */ - while (clock_is_off(cbcr_addr)) - ; - - return 0; -} - -void clock_reset_aop(void) -{ - /* Bring AOP out of RESET */ - uint32_t *mailbox; - mailbox = (uint32_t *)_aop_ss_msg_ram_drv15; - *mailbox = AOP_LOADED_SIGNAL_FLAG; -} - -void clock_configure_qspi(uint32_t hz) -{ - clock_configure((struct sdm845_clock *)&gcc->qspi_core, - qspi_core_cfg, hz, - ARRAY_SIZE(qspi_core_cfg)); - clock_enable(&gcc->qspi_cnoc_ahb_cbcr); - clock_enable(&gcc->qspi_core_cbcr); -} - -int clock_reset_bcr(void *bcr_addr, bool reset) -{ - struct sdm845_bcr *bcr = bcr_addr; - - if (reset) - setbits32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); - else - clrbits32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); - - return 0; -} - -void clock_configure_qup(int qup, uint32_t hz) -{ - int s = qup % QUP_WRAP0_S7; - struct sdm845_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? - (struct sdm845_qupv3_clock *)&gcc->qup_wrap0_s[s] : - (struct sdm845_qupv3_clock *)&gcc->qup_wrap1_s[s]; - clock_configure(&qup_clk->clk, qup_cfg, hz, ARRAY_SIZE(qup_cfg)); -} - -void clock_enable_qup(int qup) -{ - int s = qup % QUP_WRAP0_S7; - int clk_en_off = qup < QUP_WRAP1_S0 ? - QUPV3_WRAP0_CLK_ENA_S(s) : QUPV3_WRAP1_CLK_ENA_S(s); - struct sdm845_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? - &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; - - clock_enable_vote(&qup_clk->clk, &gcc->apcs_clk_br_en1, - clk_en_off); - -} - -void clock_init(void) -{ - - clock_configure_gpll0(); - - clock_enable_vote(&gcc->qup_wrap0_core_2x_cbcr, - &gcc->apcs_clk_br_en1, - QUPV3_WRAP0_CORE_2X_CLK_ENA); - clock_enable_vote(&gcc->qup_wrap0_core_cbcr, - &gcc->apcs_clk_br_en1, - QUPV3_WRAP0_CORE_CLK_ENA); - clock_enable_vote(&gcc->qup_wrap0_m_ahb_cbcr, - &gcc->apcs_clk_br_en1, - QUPV3_WRAP_0_M_AHB_CLK_ENA); - clock_enable_vote(&gcc->qup_wrap0_s_ahb_cbcr, - &gcc->apcs_clk_br_en1, - QUPV3_WRAP_0_S_AHB_CLK_ENA); - - clock_enable_vote(&gcc->qup_wrap1_core_2x_cbcr, - &gcc->apcs_clk_br_en1, - QUPV3_WRAP1_CORE_2X_CLK_ENA); - clock_enable_vote(&gcc->qup_wrap1_core_cbcr, - &gcc->apcs_clk_br_en1, - QUPV3_WRAP1_CORE_CLK_ENA); - clock_enable_vote(&gcc->qup_wrap1_m_ahb_cbcr, - &gcc->apcs_clk_br_en1, - QUPV3_WRAP_1_M_AHB_CLK_ENA); - clock_enable_vote(&gcc->qup_wrap1_s_ahb_cbcr, - &gcc->apcs_clk_br_en1, - QUPV3_WRAP_1_S_AHB_CLK_ENA); -} diff --git a/src/soc/qualcomm/sdm845/gpio.c b/src/soc/qualcomm/sdm845/gpio.c deleted file mode 100644 index 976e28a..0000000 --- a/src/soc/qualcomm/sdm845/gpio.c +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/mmio.h> -#include <types.h> -#include <gpio.h> - -void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, - uint32_t drive_str, uint32_t enable) -{ - uint32_t reg_val; - struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; - - reg_val = ((enable & GPIO_CFG_OE_BMSK) << GPIO_CFG_OE_SHFT) | - ((drive_str & GPIO_CFG_DRV_BMSK) << GPIO_CFG_DRV_SHFT) | - ((func & GPIO_CFG_FUNC_BMSK) << GPIO_CFG_FUNC_SHFT) | - ((pull & GPIO_CFG_PULL_BMSK) << GPIO_CFG_PULL_SHFT); - - write32(&regs->cfg, reg_val); -} - -void gpio_set(gpio_t gpio, int value) -{ - struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; - write32(&regs->in_out, (!!value) << GPIO_IO_OUT_SHFT); -} - -int gpio_get(gpio_t gpio) -{ - struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; - - return ((read32(&regs->in_out) >> GPIO_IO_IN_SHFT) & - GPIO_IO_IN_BMSK); -} - -void gpio_input_pulldown(gpio_t gpio) -{ - gpio_configure(gpio, GPIO_FUNC_DISABLE, - GPIO_PULL_DOWN, GPIO_2MA, GPIO_DISABLE); -} - -void gpio_input_pullup(gpio_t gpio) -{ - gpio_configure(gpio, GPIO_FUNC_DISABLE, - GPIO_PULL_UP, GPIO_2MA, GPIO_DISABLE); -} - -void gpio_input(gpio_t gpio) -{ - gpio_configure(gpio, GPIO_FUNC_DISABLE, - GPIO_NO_PULL, GPIO_2MA, GPIO_DISABLE); -} - -void gpio_output(gpio_t gpio, int value) -{ - gpio_set(gpio, value); - gpio_configure(gpio, GPIO_FUNC_DISABLE, - GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE); -} diff --git a/src/soc/qualcomm/sdm845/include/soc/addressmap.h b/src/soc/qualcomm/sdm845/include/soc/addressmap.h deleted file mode 100644 index aa80a14..0000000 --- a/src/soc/qualcomm/sdm845/include/soc/addressmap.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __SOC_QUALCOMM_SDM845_ADDRESS_MAP_H__ -#define __SOC_QUALCOMM_SDM845_ADDRESS_MAP_H__ - -#define QSPI_BASE 0x88DF000 -#define TLMM_EAST_TILE_BASE 0x03500000 -#define TLMM_NORTH_TILE_BASE 0x03900000 -#define TLMM_SOUTH_TILE_BASE 0x03D00000 -#define GCC_BASE 0x00100000 - -/* - * USB BASE ADDRESSES - */ -#define QFPROM_BASE 0x00780000 -#define QUSB_PRIM_PHY_BASE 0x088e2000 -#define QUSB_PRIM_PHY_DIG_BASE 0x088e2200 -#define QUSB_SEC_PHY_BASE 0x088e3000 -#define QUSB_SEC_PHY_DIG_BASE 0x088e3200 -#define QMP_PHY_QSERDES_COM_REG_BASE 0x088e9000 -#define QMP_PHY_QSERDES_TX_REG_BASE 0x088e9200 -#define QMP_PHY_QSERDES_RX_REG_BASE 0x088e9400 -#define QMP_PHY_PCS_REG_BASE 0x088e9c00 -#define QMP_UNIPHY_QSERDES_COM_REG_BASE 0x088eb000 -#define QMP_UNIPHY_QSERDES_TX_REG_BASE 0x088eb200 -#define QMP_UNIPHY_QSERDES_RX_REG_BASE 0x088eb400 -#define QMP_UNIPHY_PCS_REG_BASE 0x088eb800 -#define USB_HOST0_DWC3_BASE 0x0a60c100 -#define USB_HOST1_DWC3_BASE 0x0a80c100 - -#endif /* __SOC_QUALCOMM_SDM845_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sdm845/include/soc/aop.h b/src/soc/qualcomm/sdm845/include/soc/aop.h deleted file mode 100644 index 2f82747..0000000 --- a/src/soc/qualcomm/sdm845/include/soc/aop.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_QUALCOMM_SDM845_AOP_H__ -#define _SOC_QUALCOMM_SDM845_AOP_H__ - -void aop_fw_load_reset(void); - -#endif // _SOC_QUALCOMM_SDM845_AOP_H__ diff --git a/src/soc/qualcomm/sdm845/include/soc/clock.h b/src/soc/qualcomm/sdm845/include/soc/clock.h deleted file mode 100644 index 78d5dfd..0000000 --- a/src/soc/qualcomm/sdm845/include/soc/clock.h +++ /dev/null @@ -1,194 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <soc/addressmap.h> -#include <types.h> - -#ifndef __SOC_QUALCOMM_SDM845_CLOCK_H__ -#define __SOC_QUALCOMM_SDM845_CLOCK_H__ - -#define QUPV3_WRAP_0_M_AHB_CLK_ENA 6 -#define QUPV3_WRAP_0_S_AHB_CLK_ENA 7 -#define QUPV3_WRAP0_CORE_2X_CLK_ENA 9 -#define QUPV3_WRAP0_CORE_CLK_ENA 8 -#define QUPV3_WRAP1_CORE_2X_CLK_ENA 18 -#define QUPV3_WRAP1_CORE_CLK_ENA 19 -#define QUPV3_WRAP_1_M_AHB_CLK_ENA 20 -#define QUPV3_WRAP_1_S_AHB_CLK_ENA 21 -#define QUPV3_WRAP0_CLK_ENA_S(idx) (10 + idx) -#define QUPV3_WRAP1_CLK_ENA_S(idx) (22 + idx) - -#define GPLL0_EVEN_HZ (300*MHz) -#define GPLL0_MAIN_HZ (600*MHz) -#define QUP_WRAP_CORE_2X_19_2MHZ (19200*KHz) - -#define SRC_XO_19_2MHZ 0 -#define SRC_GPLL0_MAIN_600MHZ 1 -#define SRC_GPLL0_EVEN_300MHZ 6 - -#define AOP_RESET_SHFT 0 -#define RCG_MODE_DUAL_EDGE 2 - -struct sdm845_rcg { - u32 cmd; - u32 cfg; -}; - -struct sdm845_clock { - u32 cbcr; - struct sdm845_rcg rcg; - u32 m; - u32 n; - u32 d_2; -}; - -struct sdm845_qupv3_clock { - struct sdm845_clock clk; - u8 _res[0x130 - 0x18]; -}; - -struct sdm845_gpll { - u32 mode; - u32 l_val; - u32 cal_l_val; - u32 user_ctl; - u32 user_ctl_u; - u32 config_ctl; - u32 config_ctl_u; - u32 test_ctl; - u32 test_ctl_u; - u8 _res[0x1000 - 0x24]; -}; - -struct sdm845_gcc { - struct sdm845_gpll gpll0; - u8 _res0[0xf000 - 0x1000]; - u32 usb30_prim_bcr; - u8 _res1[0x10000 - 0xf004]; - u32 usb30_sec_bcr; - u8 _res2[0x12000 - 0x10004]; - u32 qusb2phy_prim_bcr; - u32 qusb2phy_sec_bcr; - u8 _res3[0x17000 - 0x12008]; - u32 qup_wrap0_bcr; - u32 qup_wrap0_m_ahb_cbcr; - u32 qup_wrap0_s_ahb_cbcr; - u32 qup_wrap0_core_cbcr; - u32 qup_wrap0_core_cdivr; - u32 qup_wrap0_core_2x_cbcr; - struct sdm845_rcg qup_wrap0_core_2x; - u8 _res4[0x17030 - 0x17020]; - struct sdm845_qupv3_clock qup_wrap0_s[8]; - u8 _res5[0x18000 - 0x179b0]; - u32 qup_wrap1_bcr; - u32 qup_wrap1_core_2x_cbcr; - u32 qup_wrap1_core_cbcr; - u32 qup_wrap1_m_ahb_cbcr; - u32 qup_wrap1_s_ahb_cbcr; - struct sdm845_qupv3_clock qup_wrap1_s[8]; - u32 qup_wrap1_core_cdivr; - u8 _res6[0x4B000 - 0x18998]; - u32 qspi_cnoc_ahb_cbcr; - u32 qspi_core_cbcr; - struct sdm845_rcg qspi_core; - u8 _res7[0x50000-0x4b010]; - u32 usb3_phy_prim_bcr; - u32 usb3phy_phy_prim_bcr; - u32 usb3_dp_phy_prim_bcr; - u32 usb3_phy_sec_bcr; - u32 usb3phy_phy_sec_bcr; - u8 _res8[0x5200c-0x50014]; - u32 apcs_clk_br_en1; - u8 _res9[0x1000000-0x52010]; -}; -check_member(sdm845_gcc, usb30_prim_bcr, 0xf000); -check_member(sdm845_gcc, usb30_sec_bcr, 0x10000); -check_member(sdm845_gcc, qusb2phy_prim_bcr, 0x12000); -check_member(sdm845_gcc, qusb2phy_sec_bcr, 0x12004); -check_member(sdm845_gcc, usb3phy_phy_prim_bcr, 0x50004); -check_member(sdm845_gcc, usb3_phy_prim_bcr, 0x50000); -check_member(sdm845_gcc, usb3_phy_sec_bcr, 0x5000c); -check_member(sdm845_gcc, usb3phy_phy_sec_bcr, 0x50010); -check_member(sdm845_gcc, apcs_clk_br_en1, 0x5200c); - -enum clk_ctl_gpll_user_ctl { - CLK_CTL_GPLL_PLLOUT_EVEN_BMSK = 0x2, - CLK_CTL_GPLL_PLLOUT_MAIN_SHFT = 0, - CLK_CTL_GPLL_PLLOUT_EVEN_SHFT = 1, - CLK_CTL_GPLL_PLLOUT_ODD_SHFT = 2 -}; - -enum clk_ctl_cfg_rcgr { - CLK_CTL_CFG_HW_CTL_BMSK = 0x100000, - CLK_CTL_CFG_HW_CTL_SHFT = 20, - CLK_CTL_CFG_MODE_BMSK = 0x3000, - CLK_CTL_CFG_MODE_SHFT = 12, - CLK_CTL_CFG_SRC_SEL_BMSK = 0x700, - CLK_CTL_CFG_SRC_SEL_SHFT = 8, - CLK_CTL_CFG_SRC_DIV_BMSK = 0x1F, - CLK_CTL_CFG_SRC_DIV_SHFT = 0 -}; - -enum clk_ctl_cmd_rcgr { - CLK_CTL_CMD_ROOT_OFF_BMSK = 0x80000000, - CLK_CTL_CMD_ROOT_OFF_SHFT = 31, - CLK_CTL_CMD_ROOT_EN_BMSK = 0x2, - CLK_CTL_CMD_ROOT_EN_SHFT = 1, - CLK_CTL_CMD_UPDATE_BMSK = 0x1, - CLK_CTL_CMD_UPDATE_SHFT = 0 -}; - -enum clk_ctl_cbcr { - CLK_CTL_CBC_CLK_OFF_BMSK = 0x80000000, - CLK_CTL_CBC_CLK_OFF_SHFT = 31, - CLK_CTL_CBC_CLK_EN_BMSK = 0x1, - CLK_CTL_CBC_CLK_EN_SHFT = 0 -}; - -enum clk_ctl_rcg_mnd { - CLK_CTL_RCG_MND_BMSK = 0xFFFF, - CLK_CTL_RCG_MND_SHFT = 0, -}; - -enum clk_ctl_bcr { - CLK_CTL_BCR_BLK_ARES_BMSK = 0x1, - CLK_CTL_BCR_BLK_ARES_SHFT = 0, -}; - -enum clk_qup { - QUP_WRAP0_S0, - QUP_WRAP0_S1, - QUP_WRAP0_S2, - QUP_WRAP0_S3, - QUP_WRAP0_S4, - QUP_WRAP0_S5, - QUP_WRAP0_S6, - QUP_WRAP0_S7, - QUP_WRAP1_S0, - QUP_WRAP1_S1, - QUP_WRAP1_S2, - QUP_WRAP1_S3, - QUP_WRAP1_S4, - QUP_WRAP1_S5, - QUP_WRAP1_S6, - QUP_WRAP1_S7 -}; - -struct clock_config { - uint32_t hz; - uint8_t src; - uint8_t div; - uint16_t m; - uint16_t n; - uint16_t d_2; -}; - -static struct sdm845_gcc *const gcc = (void *)GCC_BASE; - -void clock_init(void); -void clock_reset_aop(void); -void clock_configure_qspi(uint32_t hz); -int clock_reset_bcr(void *bcr_addr, bool reset); -void clock_configure_qup(int qup, uint32_t hz); -void clock_enable_qup(int qup); - -#endif // __SOC_QUALCOMM_SDM845_CLOCK_H__ diff --git a/src/soc/qualcomm/sdm845/include/soc/efuse.h b/src/soc/qualcomm/sdm845/include/soc/efuse.h deleted file mode 100644 index 112ffd3..0000000 --- a/src/soc/qualcomm/sdm845/include/soc/efuse.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __SOC_QUALCOMM_SDM845_EFUSE_ADDRESS_MAP_H__ -#define __SOC_QUALCOMM_SDM845_EFUSE_ADDRESS_MAP_H__ - -/** - * USB EFUSE registers - */ -struct qfprom_corr { - u8 rsvd[0x41E8 - 0x0]; - u32 qusb_hstx_trim_lsb; - u32 qusb_hstx_trim_msb; -}; - -check_member(qfprom_corr, qusb_hstx_trim_lsb, 0x41E8); -check_member(qfprom_corr, qusb_hstx_trim_msb, 0x41EC); -#endif /* __SOC_QUALCOMM_SDM845_EFUSE_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sdm845/include/soc/gpio.h b/src/soc/qualcomm/sdm845/include/soc/gpio.h deleted file mode 100644 index 04f92d6..0000000 --- a/src/soc/qualcomm/sdm845/include/soc/gpio.h +++ /dev/null @@ -1,339 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_QUALCOMM_SDM845_GPIO_H_ -#define _SOC_QUALCOMM_SDM845_GPIO_H_ - -#include <types.h> -#include <soc/addressmap.h> - -typedef struct { - u32 addr; -} gpio_t; - -#define TLMM_TILE_SIZE 0x00400000 -#define TLMM_GPIO_OFF_DELTA 0x00001000 -#define TLMM_GPIO_TILE_NUM 3 - -#define TLMM_GPIO_IN_OUT_OFF 0x4 -#define TLMM_GPIO_ID_STATUS_OFF 0x10 - -#define GPIO_FUNC_ENABLE 1 -#define GPIO_FUNC_DISABLE 0 - -/* GPIO TLMM: Direction */ -#define GPIO_INPUT 0 -#define GPIO_OUTPUT 1 - -/* GPIO TLMM: Pullup/Pulldown */ -#define GPIO_NO_PULL 0 -#define GPIO_PULL_DOWN 1 -#define GPIO_KEEPER 2 -#define GPIO_PULL_UP 3 - -/* GPIO TLMM: Drive Strength */ -#define GPIO_2MA 0 -#define GPIO_4MA 1 -#define GPIO_6MA 2 -#define GPIO_8MA 3 -#define GPIO_10MA 4 -#define GPIO_12MA 5 -#define GPIO_14MA 6 -#define GPIO_16MA 7 - -/* GPIO TLMM: Status */ -#define GPIO_DISABLE 0 -#define GPIO_ENABLE 1 - -/* GPIO TLMM: Mask */ -#define GPIO_CFG_PULL_BMSK 0x3 -#define GPIO_CFG_FUNC_BMSK 0xF -#define GPIO_CFG_DRV_BMSK 0x7 -#define GPIO_CFG_OE_BMSK 0x1 - -/* GPIO TLMM: Shift */ -#define GPIO_CFG_PULL_SHFT 0 -#define GPIO_CFG_FUNC_SHFT 2 -#define GPIO_CFG_DRV_SHFT 6 -#define GPIO_CFG_OE_SHFT 9 - -/* GPIO IO: Mask */ -#define GPIO_IO_IN_BMSK 0x1 -#define GPIO_IO_OUT_BMSK 0x1 - -/* GPIO IO: Shift */ -#define GPIO_IO_IN_SHFT 0 -#define GPIO_IO_OUT_SHFT 1 - -/* GPIO ID STATUS: Mask */ -#define GPIO_ID_STATUS_BMSK 0x1 - -/* GPIO MAX Valid # */ -#define GPIO_NUM_MAX 149 - -#define GPIO_FUNC_GPIO 0 - -#define GPIO(num) ((gpio_t){.addr = GPIO##num##_ADDR}) - -#define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7) \ -GPIO##index##_ADDR = TLMM_##tlmm##_TILE_BASE + index * TLMM_GPIO_OFF_DELTA, \ -GPIO##index##_FUNC_##func1 = 1, \ -GPIO##index##_FUNC_##func2 = 2, \ -GPIO##index##_FUNC_##func3 = 3, \ -GPIO##index##_FUNC_##func4 = 4, \ -GPIO##index##_FUNC_##func5 = 5, \ -GPIO##index##_FUNC_##func6 = 6, \ -GPIO##index##_FUNC_##func7 = 7 - -enum { - PIN(0, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(1, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(2, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(3, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(4, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(5, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(6, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(7, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(8, EAST, QUP_L4_0_CS, GP_PDM_MIRB, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(9, EAST, QUP_L5_0_CS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(10, EAST, MDP_VSYNC_P_MIRA, QUP_L6_0_CS, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(11, EAST, MDP_VSYNC_S_MIRA, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(12, SOUTH, MDP_VSYNC_E, RES_2, TSIF1_SYNC, RES_4, RES_5, - RES_6, RES_7), - PIN(13, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(14, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(15, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(16, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(17, SOUTH, CCI_I2C_SDA0, QUP_L0, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(18, SOUTH, CCI_I2C_SCL0, QUP_L1, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(19, SOUTH, CCI_I2C_SDA1, QUP_L2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(20, SOUTH, CCI_I2C_SCL1, QUP_L3, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(21, SOUTH, CCI_TIMER0, GCC_GP2_CLK_MIRB, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(22, SOUTH, CCI_TIMER1, GCC_GP3_CLK_MIRB, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(23, SOUTH, CCI_TIMER2, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(24, SOUTH, CCI_TIMER3, CCI_ASYNC_IN1, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(25, SOUTH, CCI_TIMER4, CCI_ASYNC_IN2, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(26, SOUTH, CCI_ASYNC_IN0, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(27, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(28, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(29, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(30, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(31, NORTH, QUP_L0, QUP_L2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(32, NORTH, QUP_L1, QUP_L3, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(33, NORTH, QUP_L2, QUP_L0, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(34, NORTH, QUP_L3, QUP_L1, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(35, SOUTH, PCI_E0_RST_N, QUP_L4_1_CS, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(36, SOUTH, PCI_E0_CLKREQN, QUP_L5_1_CS, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(37, SOUTH, QUP_L6_1_CS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(38, NORTH, USB_PHY_PS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(39, EAST, LPASS_SLIMBUS_DATA2, RES_2, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(40, SOUTH, SD_WRITE_PROTECT, TSIF1_ERROR, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(41, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(42, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(43, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(44, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(45, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(46, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(47, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(48, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(49, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(50, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(51, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(52, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(53, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(54, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(55, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(56, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(57, NORTH, QUA_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(58, NORTH, QUA_MI2S_SCK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(59, NORTH, QUA_MI2S_WS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(60, NORTH, QUA_MI2S_DATA0, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(61, NORTH, QUA_MI2S_DATA1, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(62, NORTH, QUA_MI2S_DATA2, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(63, NORTH, QUA_MI2S_DATA3, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(64, NORTH, PRI_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(65, NORTH, PRI_MI2S_SCK, QUP_L0, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(66, NORTH, PRI_MI2S_WS, QUP_L1, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(67, NORTH, PRI_MI2S_DATA0, QUP_L2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(68, NORTH, PRI_MI2S_DATA1, QUP_L3, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(69, EAST, SPKR_I2S_MCLK, AUDIO_REF_CLK, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(70, EAST, LPASS_SLIMBUS_CLK, SPKR_I2S_SCK, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(71, EAST, LPASS_SLIMBUS_DATA0, SPKR_I2S_DATA_OUT, RES_3, - RES_4, RES_5, RES_6, RES_7), - PIN(72, EAST, LPASS_SLIMBUS_DATA1, SPKR_I2S_WS, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(73, EAST, BTFM_SLIMBUS_DATA, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(74, EAST, BTFM_SLIMBUS_CLK, TER_MI2S_MCLK, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(75, EAST, TER_MI2S_SCK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(76, EAST, TER_MI2S_WS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(77, EAST, TER_MI2S_DATA0, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(78, EAST, TER_MI2S_DATA1, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(79, NORTH, SEC_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(80, NORTH, SEC_MI2S_SCK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(81, NORTH, SEC_MI2S_WS, QUP_L0, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(82, NORTH, SEC_MI2S_DATA0, QUP_L1, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(83, NORTH, SEC_MI2S_DATA1, QUP_L2, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(84, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(85, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(86, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(87, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(88, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(89, SOUTH, TSIF1_CLK, QUP_L0, QSPI_CS_N_1, RES_4, RES_5, - RES_6, RES_7), - PIN(90, SOUTH, TSIF1_EN, MDP_VSYNC0_OUT, QUP_L1, QSPI_CS_N_0, - MDP_VSYNC1_OUT, MDP_VSYNC2_OUT, MDP_VSYNC3_OUT), - PIN(91, SOUTH, TSIF1_DATA, SDC4_CMD, QUP_L2, QSPI_DATA, - RES_5, RES_6, RES_7), - PIN(92, SOUTH, TSIF2_ERROR, SDC4_DATA, QUP_L3, QSPI_DATA, - RES_5, RES_6, RES_7), - PIN(93, SOUTH, TSIF2_CLK, SDC4_CLK, QUP_L0, QSPI_DATA, - RES_5, RES_6, RES_7), - PIN(94, SOUTH, TSIF2_EN, SDC4_DATA, QUP_L1, QSPI_DATA, - RES_5, RES_6, RES_7), - PIN(95, SOUTH, TSIF2_DATA, SDC4_DATA, QUP_L2, QSPI_CLK, - RES_5, RES_6, RES_7), - PIN(96, SOUTH, TSIF2_SYNC, SDC4_DATA, QUP_L3, RES_4, - RES_5, RES_6, RES_7), - PIN(97, NORTH, RFFE6_CLK, GRFC37, MDP_VSYNC_P_MIRB, - RES_4, RES_5, RES_6, RES_7), - PIN(98, NORTH, RFFE6_DATA, MDP_VSYNC_S_MIRB, RES_3, - RES_4, RES_5, RES_6, RES_7), - PIN(99, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(100, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(101, NORTH, GRFC4, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(102, NORTH, PCI_E1_RST_N, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(103, NORTH, PCI_E1_CLKREQN, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(104, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(105, NORTH, UIM2_DATA, QUP_L0, QUP_L4_8_CS, RES_4, RES_5, - RES_6, RES_7), - PIN(106, NORTH, UIM2_CLK, QUP_L1, QUP_L5_8_CS, RES_4, RES_5, - RES_6, RES_7), - PIN(107, NORTH, UIM2_RESET, QUP_L2, QUP_L6_8_CS, RES_4, RES_5, - RES_6, RES_7), - PIN(108, NORTH, UIM2_PRESENT, QUP_L3, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(109, NORTH, UIM1_DATA, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(110, NORTH, UIM1_CLK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(111, NORTH, UIM1_RESET, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(112, NORTH, UIM1_PRESENT, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(113, NORTH, UIM_BATT_ALARM, EDP_HOT_PLUG_DETECT, RES_3, - RES_4, RES_5, RES_6, RES_7), - PIN(114, NORTH, GRFC8, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRE, - RES_5, RES_6, RES_7), - PIN(115, NORTH, GRFC9, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRF, - RES_5, RES_6, RES_7), - PIN(116, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(117, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(118, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(119, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(120, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(121, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(122, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(123, EAST, QUP_L4_9_CS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(124, EAST, QUP_L5_9_CS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(125, EAST, QUP_L6_9_CS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(126, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(127, NORTH, GRFC3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(128, NORTH, RES_1, RES_2, GPS_TX_AGGRESSOR_MIRB, RES_4, - RES_5, RES_6, RES_7), - PIN(129, NORTH, RES_1, RES_2, GPS_TX_AGGRESSOR_MIRC, RES_4, - RES_5, RES_6, RES_7), - PIN(130, NORTH, QLINK_REQUEST, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(131, NORTH, QLINK_ENABLE, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(132, NORTH, GRFC2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(133, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(134, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(135, NORTH, GRFC0, PA_INDICATOR_1_OR_2, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(136, NORTH, GRFC1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(137, NORTH, RFFE3_DATA, GRFC35, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(138, NORTH, RFFE3_CLK, GRFC32, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(139, NORTH, RFFE4_DATA, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(140, NORTH, RFFE4_CLK, GRFC36, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(141, NORTH, RFFE5_DATA, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(142, NORTH, RFFE5_CLK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(143, NORTH, GRFC5, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRD, - RES_5, RES_6, RES_7), - PIN(144, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(145, NORTH, RES_1, GPS_TX_AGGRESSOR_MIRA, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(146, NORTH, RFFE2_DATA, GRFC34, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(147, NORTH, RFFE2_CLK, GRFC33, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(148, NORTH, RFFE1_DATA, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(149, NORTH, RFFE1_CLK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), -}; - -struct tlmm_gpio { - uint32_t cfg; - uint32_t in_out; -}; - -void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, - uint32_t drive_str, uint32_t enable); - -#endif // _SOC_QUALCOMM_SDM845_GPIO_H_ diff --git a/src/soc/qualcomm/sdm845/include/soc/mmu.h b/src/soc/qualcomm/sdm845/include/soc/mmu.h deleted file mode 100644 index 868a6c8..0000000 --- a/src/soc/qualcomm/sdm845/include/soc/mmu.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_QUALCOMM_SDM845_MMU_H__ -#define _SOC_QUALCOMM_SDM845_MMU_H__ - -void sdm845_mmu_init(void); - -#endif // _SOC_QUALCOMM_SDM845_MMU_H_ diff --git a/src/soc/qualcomm/sdm845/include/soc/qspi.h b/src/soc/qualcomm/sdm845/include/soc/qspi.h deleted file mode 100644 index 5357e48..0000000 --- a/src/soc/qualcomm/sdm845/include/soc/qspi.h +++ /dev/null @@ -1,108 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> -#include <soc/addressmap.h> -#include <spi-generic.h> - -#ifndef __SOC_QUALCOMM_SDM845_QSPI_H__ -#define __SOC_QUALCOMM_SDM845_QSPI_H__ - -struct sdm845_qspi_regs { - u32 mstr_cfg; - u32 ahb_mstr_cfg; - u32 reserve_0; - u32 mstr_int_en; - u32 mstr_int_sts; - u32 pio_xfer_ctrl; - u32 pio_xfer_cfg; - u32 pio_xfer_sts; - u32 pio_dataout_1byte; - u32 pio_dataout_4byte; - u32 rd_fifo_cfg; - u32 rd_fifo_sts; - u32 rd_fifo_rst; - u32 reserve_1[3]; - u32 next_dma_desc_addr; - u32 current_dma_desc_addr; - u32 current_mem_addr; - u32 hw_version; - u32 rd_fifo[16]; -}; - -check_member(sdm845_qspi_regs, rd_fifo, 0x50); -static struct sdm845_qspi_regs * const sdm845_qspi = (void *) QSPI_BASE; - -// MSTR_CONFIG register - -#define TX_DATA_OE_DELAY_SHIFT 24 -#define TX_DATA_OE_DELAY_MASK (0x3 << TX_DATA_OE_DELAY_SHIFT) -#define TX_CS_N_DELAY_SHIFT 22 -#define TX_CS_N_DELAY_MASK (0x3 << TX_CS_N_DELAY_SHIFT) -#define TX_CLK_DELAY_SHIFT 20 -#define TX_CLK_DELAY_MASK (0x3 << TX_CLK_DELAY_SHIFT) -#define TX_DATA_DELAY_SHIFT 18 -#define TX_DATA_DELAY_MASK (0x3 << TX_DATA_DELAY_SHIFT) -#define LPA_BASE_SHIFT 14 -#define LPA_BASE_MASK (0xF << LPA_BASE_SHIFT) -#define SBL_EN BIT(13) -#define CHIP_SELECT_NUM BIT(12) -#define SPI_MODE_SHIFT 10 -#define SPI_MODE_MASK (0x3 << SPI_MODE_SHIFT) -#define BIG_ENDIAN_MODE BIT(9) -#define DMA_ENABLE BIT(8) -#define PIN_WPN BIT(7) -#define PIN_HOLDN BIT(6) -#define FB_CLK_EN BIT(4) -#define FULL_CYCLE_MODE BIT(3) - -// MSTR_INT_ENABLE and MSTR_INT_STATUS register - -#define DMA_CHAIN_DONE BIT(31) -#define TRANSACTION_DONE BIT(16) -#define WRITE_FIFO_OVERRUN BIT(11) -#define WRITE_FIFO_FULL BIT(10) -#define HRESP_FROM_NOC_ERR BIT(3) -#define RESP_FIFO_RDY BIT(2) -#define RESP_FIFO_NOT_EMPTY BIT(1) -#define RESP_FIFO_UNDERRUN BIT(0) - -// PIO_TRANSFER_CONFIG register - -#define TRANSFER_FRAGMENT BIT(8) -#define MULTI_IO_MODE_SHIFT 1 -#define MULTI_IO_MODE_MASK (0x7 << MULTI_IO_MODE_SHIFT) -#define TRANSFER_DIRECTION BIT(0) - -// PIO_TRANSFER_STATUS register - -#define WR_FIFO_BYTES_SHIFT 16 -#define WR_FIFO_BYTES_MASK (0xFFFF << WR_FIFO_BYTES_SHIFT) - -// RD_FIFO_CONFIG register - -#define CONTINUOUS_MODE BIT(0) - -// RD_FIFO_STATUS register - -#define FIFO_EMPTY BIT(11) -#define WR_CNTS_SHIFT 4 -#define WR_CNTS_MASK (0x7F << WR_CNTS_SHIFT) -#define RDY_64BYTE BIT(3) -#define RDY_32BYTE BIT(2) -#define RDY_16BYTE BIT(1) -#define FIFO_RDY BIT(0) - -// RD_FIFO_RESET register - -#define RESET_FIFO BIT(0) - -#define QSPI_MAX_PACKET_COUNT 0xFFC0 - -void quadspi_init(uint32_t hz); -int sdm845_claim_bus(const struct spi_slave *slave); -int sdm845_setup_bus(const struct spi_slave *slave); -void sdm845_release_bus(const struct spi_slave *slave); -int sdm845_xfer(const struct spi_slave *slave, const void *dout, - size_t out_bytes, void *din, size_t in_bytes); -int sdm845_xfer_dual(const struct spi_slave *slave, const void *dout, - size_t out_bytes, void *din, size_t in_bytes); -#endif /* __SOC_QUALCOMM_SDM845_QSPI_H__ */ diff --git a/src/soc/qualcomm/sdm845/include/soc/symbols.h b/src/soc/qualcomm/sdm845/include/soc/symbols.h deleted file mode 100644 index 64482c7..0000000 --- a/src/soc/qualcomm/sdm845/include/soc/symbols.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_QUALCOMM_SDM845_SYMBOLS_H_ -#define _SOC_QUALCOMM_SDM845_SYMBOLS_H_ - -#include <symbols.h> - -DECLARE_REGION(ssram) -DECLARE_REGION(bsram) -DECLARE_REGION(dram_reserved) -DECLARE_REGION(dcb); -DECLARE_REGION(pmic); -DECLARE_REGION(limits_cfg); -DECLARE_REGION(aop); -DECLARE_REGION(aop_ss_msg_ram_drv15); - -#endif // _SOC_QUALCOMM_SDM845_SYMBOLS_H_ diff --git a/src/soc/qualcomm/sdm845/include/soc/usb.h b/src/soc/qualcomm/sdm845/include/soc/usb.h deleted file mode 100644 index 5ce8f805c..0000000 --- a/src/soc/qualcomm/sdm845/include/soc/usb.h +++ /dev/null @@ -1,83 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> - -#ifndef _SDM845_USB_H_ -#define _SDM845_USB_H_ - -/* QSCRATCH_GENERAL_CFG register bit offset */ -#define PIPE_UTMI_CLK_SEL BIT(0) -#define PIPE3_PHYSTATUS_SW BIT(3) -#define PIPE_UTMI_CLK_DIS BIT(8) - -/* Global USB3 Control Registers */ -#define DWC3_GUSB3PIPECTL_DELAYP1TRANS BIT(18) -#define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX BIT(27) -#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) -#define DWC3_GCTL_PRTCAP_OTG 3 -#define DWC3_GCTL_PRTCAP_HOST 1 - -/* Global USB2 PHY Configuration Register */ -#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10) -#define DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) -#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3) -#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) -#define USBTRDTIM_UTMI_8_BIT 9 -#define UTMI_PHYIF_8_BIT 0 - -#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) -#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) -#define DWC3_GCTL_DISSCRAMBLE (1 << 3) -#define DWC3_GCTL_U2EXIT_LFPS (1 << 2) -#define DWC3_GCTL_DSBLCLKGTNG (1 << 0) - -#define PORT_TUNE1_MASK 0xf0 - -/* QUSB2PHY_PWR_CTRL1 register related bits */ -#define POWER_DOWN BIT(0) - -/* DEBUG_CTRL2 register value to program VSTATUS MUX for PHY status */ -#define DEBUG_CTRL2_MUX_PLL_LOCK_STATUS 0x4 - -/* STAT5 register bits */ -#define VSTATUS_PLL_LOCK_STATUS_MASK BIT(0) - -/* QUSB PHY register values */ -#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x03 -#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x7c -#define QUSB2PHY_PLL_CMODE 0x80 -#define QUSB2PHY_PLL_LOCK_DELAY 0x0a -#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0x19 -#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x40 -#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x20 -#define QUSB2PHY_PWR_CTRL2 0x21 -#define QUSB2PHY_IMP_CTRL1 0x0 -#define QUSB2PHY_IMP_CTRL2 0x58 -#define QUSB2PHY_PORT_TUNE1 0x30 -#define QUSB2PHY_PORT_TUNE2 0x29 -#define QUSB2PHY_PORT_TUNE3 0xca -#define QUSB2PHY_PORT_TUNE4 0x04 -#define QUSB2PHY_PORT_TUNE5 0x03 -#define QUSB2PHY_CHG_CTRL2 0x0 - -/* USB3PHY_PCIE_USB3_PCS_PCS_STATUS bit */ -#define USB3_PCS_PHYSTATUS BIT(6) - -struct usb_board_data { - /* Register values going to override from the boardfile */ - u32 pll_bias_control_2; - u32 imp_ctrl1; - u32 port_tune1; -}; - -struct qmp_phy_init_tbl { - u32 *address; - u32 val; -}; - -void setup_usb_host0(struct usb_board_data *data); -void setup_usb_host1(struct usb_board_data *data); -/* Call reset_ before setup_ */ -void reset_usb0(void); -void reset_usb1(void); - -#endif /* _SDM845_USB_H_ */ diff --git a/src/soc/qualcomm/sdm845/memlayout.ld b/src/soc/qualcomm/sdm845/memlayout.ld deleted file mode 100644 index 30b4920..0000000 --- a/src/soc/qualcomm/sdm845/memlayout.ld +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <memlayout.h> -#include <arch/header.ld> - -/* SYSTEM_IMEM : 0x14680000 - 0x146C0000 */ -#define SSRAM_START(addr) SYMBOL(ssram, addr) -#define SSRAM_END(addr) SYMBOL(essram, addr) - -/* BOOT_IMEM : 0x14800000 - 0x14980000 */ -#define BSRAM_START(addr) SYMBOL(bsram, addr) -#define BSRAM_END(addr) SYMBOL(ebsram, addr) - -/* AOP : 0x0B000000 - 0x0B100000 */ -#define AOPSRAM_START(addr) SYMBOL(aopsram, addr) -#define AOPSRAM_END(addr) SYMBOL(eaopsram, addr) - -/* AOPMSG : 0x0C300000 - 0x0C400000 */ -#define AOPMSG_START(addr) SYMBOL(aopmsg, addr) -#define AOPMSG_END(addr) SYMBOL(eaopmsg, addr) - -SECTIONS -{ - AOPSRAM_START(0x0B000000) - REGION(aop, 0x0B000000, 0x100000, 4096) - AOPSRAM_END(0x0B100000) - - AOPMSG_START(0x0C300000) - REGION(aop_ss_msg_ram_drv15, 0x0C3F0000, 0x400, 0x100) - AOPMSG_END(0x0C400000) - - SSRAM_START(0x14680000) - OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) - DMA_COHERENT(0x14699000, 8K) - REGION(qcsdi, 0x146AC000, 44K, 4K) - SSRAM_END(0x146C0000) - - BSRAM_START(0x14800000) - REGION(fw_reserved2, 0x14800000, 0x16000, 0x1000) - BOOTBLOCK(0x14816000, 40K) - TTB(0x14820000, 56K) - VBOOT2_WORK(0x1482E000, 12K) - STACK(0x14832000, 16K) - TIMESTAMP(0x14836000, 1K) - PRERAM_CBMEM_CONSOLE(0x14836400, 32K) - PRERAM_CBFS_CACHE(0x1483E400, 70K) - FMAP_CACHE(0x1484FC00, 2K) - REGION(bsram_unused, 0x14850400, 0x9DB00, 0x100) - REGION(ddr_information, 0x148EDF00, 256, 256) - REGION(limits_cfg, 0x148EE000, 4K, 4K) - REGION(qclib_serial_log, 0x148EF000, 4K, 4K) - REGION(ddr_training, 0x148F0000, 8K, 4K) - REGION(qclib, 0x148F2000, 512K, 4K) - REGION(dcb, 0x14972000, 16K, 4K) - REGION(pmic, 0x14976000, 40K, 4K) - BSRAM_END(0x14980000) - - DRAM_START(0x80000000) - /* Various hardware/software subsystems make use of this area */ - REGION(dram_reserved, 0x85000000, 0x1A800000, 0x1000) - POSTRAM_CBFS_CACHE(0x9F800000, 384K) - RAMSTAGE(0x9F860000, 2M) -} diff --git a/src/soc/qualcomm/sdm845/mmu.c b/src/soc/qualcomm/sdm845/mmu.c deleted file mode 100644 index 7af4f95..0000000 --- a/src/soc/qualcomm/sdm845/mmu.c +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <symbols.h> -#include <arch/mmu.h> -#include <arch/cache.h> -#include <soc/mmu.h> -#include <soc/mmu_common.h> -#include <soc/symbols.h> - -void sdm845_mmu_init(void) -{ - mmu_init(); - - mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), DEV_MEM); - mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM); - mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM); - mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent), - UNCACHED_RAM); - - mmu_enable(); -} - -void soc_mmu_dram_config_post_dram_init(void) -{ - mmu_config_range((void *)_aop, REGION_SIZE(aop), CACHED_RAM); -} diff --git a/src/soc/qualcomm/sdm845/qclib.c b/src/soc/qualcomm/sdm845/qclib.c deleted file mode 100644 index 5617139..0000000 --- a/src/soc/qualcomm/sdm845/qclib.c +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cbfs.h> -#include <fmap.h> -#include <soc/symbols.h> -#include <soc/qclib_common.h> - -int qclib_soc_blob_load(void) -{ - size_t size; - ssize_t ssize; - - /* Attempt to load PMICCFG Blob */ - size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg", - _pmic, REGION_SIZE(pmic), CBFS_TYPE_RAW); - if (!size) - return -1; - qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, size, 0); - - /* Attempt to load DCB Blob */ - size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/dcb", - _dcb, REGION_SIZE(dcb), CBFS_TYPE_RAW); - if (!size) - return -1; - qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, size, 0); - - /* Attempt to load Limits Config Blob */ - ssize = fmap_read_area(QCLIB_FR_LIMITS_CFG_DATA, _limits_cfg, - REGION_SIZE(limits_cfg)); - if (ssize < 0) - return -1; - qclib_add_if_table_entry(QCLIB_TE_LIMITS_CFG_DATA, - _limits_cfg, ssize, 0); - - return 0; -} diff --git a/src/soc/qualcomm/sdm845/qspi.c b/src/soc/qualcomm/sdm845/qspi.c deleted file mode 100644 index 8c98316..0000000 --- a/src/soc/qualcomm/sdm845/qspi.c +++ /dev/null @@ -1,293 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <spi-generic.h> -#include <spi_flash.h> -#include <arch/cache.h> -#include <device/mmio.h> -#include <soc/addressmap.h> -#include <soc/qspi.h> -#include <soc/gpio.h> -#include <soc/clock.h> -#include <symbols.h> -#include <assert.h> -#include <gpio.h> -#include <string.h> - -#define CACHE_LINE_SIZE 64 - -static int curr_desc_idx = -1; - -struct cmd_desc { - uint32_t data_address; - uint32_t next_descriptor; - uint32_t direction:1; - uint32_t multi_io_mode:3; - uint32_t reserved1:4; - uint32_t fragment:1; - uint32_t reserved2:7; - uint32_t length:16; - //------------------------// - uint32_t bounce_src; - uint32_t bounce_dst; - uint32_t bounce_length; - uint64_t padding[5]; -}; - -enum qspi_mode { - SDR_1BIT = 1, - SDR_2BIT = 2, - SDR_4BIT = 3, - DDR_1BIT = 5, - DDR_2BIT = 6, - DDR_4BIT = 7, -}; - -enum cs_state { - CS_DEASSERT, - CS_ASSERT -}; - -struct xfer_cfg { - enum qspi_mode mode; -}; - -enum bus_xfer_direction { - MASTER_READ = 0, - MASTER_WRITE = 1, -}; - -struct { - struct cmd_desc descriptors[3]; - uint8_t buffers[3][CACHE_LINE_SIZE]; -} *dma = (void *)_dma_coherent; - -static void dma_transfer_chain(struct cmd_desc *chain) -{ - uint32_t mstr_int_status; - - write32(&sdm845_qspi->mstr_int_sts, 0xFFFFFFFF); - write32(&sdm845_qspi->next_dma_desc_addr, (uint32_t)(uintptr_t) chain); - - while (1) { - mstr_int_status = read32(&sdm845_qspi->mstr_int_sts); - if (mstr_int_status & DMA_CHAIN_DONE) - break; - } -} - -static void flush_chain(void) -{ - struct cmd_desc *desc = &dma->descriptors[0]; - uint8_t *src; - uint8_t *dst; - - dma_transfer_chain(desc); - - while (desc) { - if (desc->direction == MASTER_READ) { - if (desc->bounce_length == 0) - dcache_invalidate_by_mva( - (void *)(uintptr_t) desc->data_address, - desc->length); - else { - src = (void *)(uintptr_t) desc->bounce_src; - dst = (void *)(uintptr_t) desc->bounce_dst; - memcpy(dst, src, desc->bounce_length); - } - } - desc = (void *)(uintptr_t) desc->next_descriptor; - } - curr_desc_idx = -1; -} - -static struct cmd_desc *allocate_descriptor(void) -{ - struct cmd_desc *current; - struct cmd_desc *next; - uint8_t index; - - current = (curr_desc_idx == -1) ? - NULL : &dma->descriptors[curr_desc_idx]; - - index = ++curr_desc_idx; - next = &dma->descriptors[index]; - - next->data_address = (uint32_t) (uintptr_t) dma->buffers[index]; - - next->next_descriptor = 0; - next->direction = MASTER_READ; - next->multi_io_mode = 0; - next->reserved1 = 0; - next->fragment = 0; - next->reserved2 = 0; - next->length = 0; - next->bounce_src = 0; - next->bounce_dst = 0; - next->bounce_length = 0; - - if (current) { - current->next_descriptor = (uint32_t)(uintptr_t) next; - current->fragment = 1; - } - - return next; -} - -static void cs_change(enum cs_state state) -{ - gpio_set(GPIO(90), state == CS_DEASSERT); -} - -static void configure_gpios(void) -{ - gpio_output(GPIO(90), 1); - - gpio_configure(GPIO(91), GPIO91_FUNC_QSPI_DATA, - GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE); - - gpio_configure(GPIO(92), GPIO92_FUNC_QSPI_DATA, - GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE); - - gpio_configure(GPIO(95), GPIO95_FUNC_QSPI_CLK, - GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE); -} - -static void queue_bounce_data(uint8_t *data, uint32_t data_bytes, - enum qspi_mode data_mode, bool write) -{ - struct cmd_desc *desc; - uint8_t *ptr; - - desc = allocate_descriptor(); - desc->direction = write; - desc->multi_io_mode = data_mode; - ptr = (void *)(uintptr_t) desc->data_address; - - if (write) { - memcpy(ptr, data, data_bytes); - } else { - desc->bounce_src = (uint32_t)(uintptr_t) ptr; - desc->bounce_dst = (uint32_t)(uintptr_t) data; - desc->bounce_length = data_bytes; - } - - desc->length = data_bytes; -} - -static void queue_direct_data(uint8_t *data, uint32_t data_bytes, - enum qspi_mode data_mode, bool write) -{ - struct cmd_desc *desc; - - desc = allocate_descriptor(); - desc->direction = write; - desc->multi_io_mode = data_mode; - desc->data_address = (uint32_t)(uintptr_t) data; - desc->length = data_bytes; - - if (write) - dcache_clean_by_mva(data, data_bytes); - else - dcache_invalidate_by_mva(data, data_bytes); -} - -static void queue_data(uint8_t *data, uint32_t data_bytes, - enum qspi_mode data_mode, bool write) -{ - uint8_t *aligned_ptr; - uint8_t *epilog_ptr; - uint32_t prolog_bytes, aligned_bytes, epilog_bytes; - - if (data_bytes == 0) - return; - - aligned_ptr = - (uint8_t *)ALIGN_UP((uintptr_t)data, CACHE_LINE_SIZE); - - prolog_bytes = MIN(data_bytes, aligned_ptr - data); - aligned_bytes = ALIGN_DOWN(data_bytes - prolog_bytes, CACHE_LINE_SIZE); - epilog_bytes = data_bytes - prolog_bytes - aligned_bytes; - - epilog_ptr = data + prolog_bytes + aligned_bytes; - - if (prolog_bytes) - queue_bounce_data(data, prolog_bytes, data_mode, write); - if (aligned_bytes) - queue_direct_data(aligned_ptr, aligned_bytes, data_mode, write); - if (epilog_bytes) - queue_bounce_data(epilog_ptr, epilog_bytes, data_mode, write); -} - -static void reg_init(void) -{ - uint32_t spi_mode; - uint32_t tx_data_oe_delay, tx_data_delay; - uint32_t mstr_config; - - spi_mode = 0; - - tx_data_oe_delay = 0; - tx_data_delay = 0; - - mstr_config = (tx_data_oe_delay << TX_DATA_OE_DELAY_SHIFT) | - (tx_data_delay << TX_DATA_DELAY_SHIFT) | (SBL_EN) | - (spi_mode << SPI_MODE_SHIFT) | - (PIN_HOLDN) | - (FB_CLK_EN) | - (DMA_ENABLE) | - (FULL_CYCLE_MODE); - - write32(&sdm845_qspi->mstr_cfg, mstr_config); - write32(&sdm845_qspi->ahb_mstr_cfg, 0xA42); - write32(&sdm845_qspi->mstr_int_en, 0x0); - write32(&sdm845_qspi->mstr_int_sts, 0xFFFFFFFF); - write32(&sdm845_qspi->rd_fifo_cfg, 0x0); - write32(&sdm845_qspi->rd_fifo_rst, RESET_FIFO); -} - -void quadspi_init(uint32_t hz) -{ - assert(dcache_line_bytes() == CACHE_LINE_SIZE); - clock_configure_qspi(hz * 4); - configure_gpios(); - reg_init(); -} - -int sdm845_claim_bus(const struct spi_slave *slave) -{ - cs_change(CS_ASSERT); - return 0; -} - -void sdm845_release_bus(const struct spi_slave *slave) -{ - cs_change(CS_DEASSERT); -} - -static int xfer(enum qspi_mode mode, const void *dout, size_t out_bytes, - void *din, size_t in_bytes) -{ - if ((out_bytes && !dout) || (in_bytes && !din) || - (in_bytes && out_bytes)) { - return -1; - } - - queue_data((uint8_t *) (out_bytes ? dout : din), - in_bytes | out_bytes, mode, !!out_bytes); - - flush_chain(); - - return 0; -} - -int sdm845_xfer(const struct spi_slave *slave, const void *dout, - size_t out_bytes, void *din, size_t in_bytes) -{ - return xfer(SDR_1BIT, dout, out_bytes, din, in_bytes); -} - -int sdm845_xfer_dual(const struct spi_slave *slave, const void *dout, - size_t out_bytes, void *din, size_t in_bytes) -{ - return xfer(SDR_2BIT, dout, out_bytes, din, in_bytes); -} diff --git a/src/soc/qualcomm/sdm845/soc.c b/src/soc/qualcomm/sdm845/soc.c deleted file mode 100644 index 07716e8..0000000 --- a/src/soc/qualcomm/sdm845/soc.c +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <symbols.h> -#include <device/device.h> -#include <soc/mmu.h> -#include <soc/mmu_common.h> -#include <soc/symbols.h> -#include <soc/aop.h> - -static void soc_read_resources(struct device *dev) -{ - ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB, - ddr_region->size / KiB); - reserved_ram_resource(dev, 1, (uintptr_t)_dram_reserved / KiB, - REGION_SIZE(dram_reserved) / KiB); -} - -static void soc_init(struct device *dev) -{ - aop_fw_load_reset(); -} - -static struct device_operations soc_ops = { - .read_resources = soc_read_resources, - .init = soc_init, -}; - -static void enable_soc_dev(struct device *dev) -{ - dev->ops = &soc_ops; -} - -struct chip_operations soc_qualcomm_sdm845_ops = { - CHIP_NAME("SOC Qualcomm SDM845") - .enable_dev = enable_soc_dev, -}; diff --git a/src/soc/qualcomm/sdm845/spi.c b/src/soc/qualcomm/sdm845/spi.c deleted file mode 100644 index 88314f4..0000000 --- a/src/soc/qualcomm/sdm845/spi.c +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <spi-generic.h> -#include <spi_flash.h> -#include <soc/qspi.h> - -static const struct spi_ctrlr spi_ctrlr = { - .claim_bus = sdm845_claim_bus, - .release_bus = sdm845_release_bus, - .xfer = sdm845_xfer, - .xfer_dual = sdm845_xfer_dual, - .max_xfer_size = QSPI_MAX_PACKET_COUNT, -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &spi_ctrlr, - .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, - .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/qualcomm/sdm845/timer.c b/src/soc/qualcomm/sdm845/timer.c deleted file mode 100644 index 19e466a..0000000 --- a/src/soc/qualcomm/sdm845/timer.c +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <delay.h> -#include <arch/lib_helpers.h> -#include <commonlib/helpers.h> - -void init_timer(void) -{ - raw_write_cntfrq_el0(19200*KHz); -} diff --git a/src/soc/qualcomm/sdm845/uart_bitbang.c b/src/soc/qualcomm/sdm845/uart_bitbang.c deleted file mode 100644 index 8d7138e..0000000 --- a/src/soc/qualcomm/sdm845/uart_bitbang.c +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/uart.h> -#include <gpio.h> - -#define UART_TX_PIN GPIO(4) - -static void set_tx(int line_state) -{ - gpio_set(UART_TX_PIN, line_state); -} - -void uart_init(unsigned int idx) -{ - gpio_output(UART_TX_PIN, 1); -} - -void uart_tx_byte(unsigned int idx, unsigned char data) -{ - uart_bitbang_tx_byte(data, set_tx); -} - -void uart_tx_flush(unsigned int idx) -{ - /* unnecessary, PIO Tx means transaction is over when tx_byte returns */ -} - -unsigned char uart_rx_byte(unsigned int idx) -{ - return 0; /* not implemented */ -} diff --git a/src/soc/qualcomm/sdm845/usb.c b/src/soc/qualcomm/sdm845/usb.c deleted file mode 100644 index 11c3edb..0000000 --- a/src/soc/qualcomm/sdm845/usb.c +++ /dev/null @@ -1,899 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <device/mmio.h> -#include <soc/usb.h> -#include <soc/clock.h> -#include <soc/addressmap.h> -#include <soc/efuse.h> -#include <timer.h> - -struct usb_qusb_phy_dig { - u8 rsvd1[16]; - u32 pwr_ctrl1; - u32 pwr_ctrl2; - u8 rsvd2[8]; - u32 imp_ctrl1; - u32 imp_ctrl2; - u8 rsvd3[20]; - u32 chg_ctrl2; - u32 tune1; - u32 tune2; - u32 tune3; - u32 tune4; - u32 tune5; - u8 rsvd4[44]; - u32 debug_ctrl2; - u8 rsvd5[28]; - u32 debug_stat5; -}; -check_member(usb_qusb_phy_dig, tune5, 0x50); -check_member(usb_qusb_phy_dig, debug_ctrl2, 0x80); -check_member(usb_qusb_phy_dig, debug_stat5, 0xA0); - -struct usb_qusb_phy_pll { - u8 rsvd0[4]; - u32 analog_controls_two; - u8 rsvd1[36]; - u32 cmode; - u8 rsvd2[132]; - u32 dig_tim; - u8 rsvd3[204]; - u32 lock_delay; - u8 rsvd4[4]; - u32 clock_inverters; - u8 rsvd5[4]; - u32 bias_ctrl_1; - u32 bias_ctrl_2; -}; -check_member(usb_qusb_phy_pll, cmode, 0x2C); -check_member(usb_qusb_phy_pll, bias_ctrl_2, 0x198); -check_member(usb_qusb_phy_pll, dig_tim, 0xB4); - -/* Only for QMP V3 PHY - QSERDES COM registers */ -struct usb3_phy_qserdes_com_reg_layout { - u8 _reserved1[16]; - u32 com_ssc_en_center; - u32 com_ssc_adj_per1; - u32 com_ssc_adj_per2; - u32 com_ssc_per1; - u32 com_ssc_per2; - u32 com_ssc_step_size1; - u32 com_ssc_step_size2; - u8 _reserved2[8]; - u32 com_bias_en_clkbuflr_en; - u32 com_sys_clk_enable1; - u32 com_sys_clk_ctrl; - u32 com_sysclk_buf_enable; - u32 com_pll_en; - u32 com_pll_ivco; - u8 _reserved3[20]; - u32 com_cp_ctrl_mode0; - u8 _reserved4[4]; - u32 com_pll_rctrl_mode0; - u8 _reserved5[4]; - u32 com_pll_cctrl_mode0; - u8 _reserved6[12]; - u32 com_sysclk_en_sel; - u8 _reserved7[8]; - u32 com_resetsm_ctrl2; - u32 com_lock_cmp_en; - u32 com_lock_cmp_cfg; - u32 com_lock_cmp1_mode0; - u32 com_lock_cmp2_mode0; - u32 com_lock_cmp3_mode0; - u8 _reserved8[12]; - u32 com_dec_start_mode0; - u8 _reserved9[4]; - u32 com_div_frac_start1_mode0; - u32 com_div_frac_start2_mode0; - u32 com_div_frac_start3_mode0; - u8 _reserved10[20]; - u32 com_integloop_gain0_mode0; - u32 com_integloop_gain1_mode0; - u8 _reserved11[16]; - u32 com_vco_tune_map; - u32 com_vco_tune1_mode0; - u32 com_vco_tune2_mode0; - u8 _reserved12[60]; - u32 com_clk_select; - u32 com_hsclk_sel; - u8 _reserved13[8]; - u32 com_coreclk_div_mode0; - u8 _reserved14[8]; - u32 com_core_clk_en; - u32 com_c_ready_status; - u32 com_cmn_config; - u32 com_cmn_rate_override; - u32 com_svs_mode_clk_sel; -}; -check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_en_center, 0x010); -check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per1, 0x014); -check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per2, 0x018); -check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per1, 0x01c); -check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per2, 0x020); -check_member(usb3_phy_qserdes_com_reg_layout, com_bias_en_clkbuflr_en, 0x034); -check_member(usb3_phy_qserdes_com_reg_layout, com_pll_ivco, 0x048); -check_member(usb3_phy_qserdes_com_reg_layout, com_cp_ctrl_mode0, 0x060); -check_member(usb3_phy_qserdes_com_reg_layout, com_sysclk_en_sel, 0x080); -check_member(usb3_phy_qserdes_com_reg_layout, com_resetsm_ctrl2, 0x08c); -check_member(usb3_phy_qserdes_com_reg_layout, com_dec_start_mode0, 0x0b0); -check_member(usb3_phy_qserdes_com_reg_layout, com_div_frac_start1_mode0, 0x0b8); -check_member(usb3_phy_qserdes_com_reg_layout, com_integloop_gain0_mode0, 0x0d8); -check_member(usb3_phy_qserdes_com_reg_layout, com_vco_tune_map, 0x0f0); -check_member(usb3_phy_qserdes_com_reg_layout, com_clk_select, 0x138); -check_member(usb3_phy_qserdes_com_reg_layout, com_coreclk_div_mode0, 0x148); -check_member(usb3_phy_qserdes_com_reg_layout, com_core_clk_en, 0x154); -check_member(usb3_phy_qserdes_com_reg_layout, com_svs_mode_clk_sel, 0x164); - -/* Only for QMP V3 PHY - TX registers */ -struct usb3_phy_qserdes_tx_reg_layout { - u8 _reserved1[68]; - u32 tx_res_code_lane_offset_tx; - u32 tx_res_code_lane_offset_rx; - u8 _reserved2[20]; - u32 tx_highz_drvr_en; - u8 _reserved3[40]; - u32 tx_lane_mode_1; - u8 _reserved4[20]; - u32 tx_rcv_detect_lvl_2; -}; -check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_tx, 0x044); -check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_rx, 0x048); -check_member(usb3_phy_qserdes_tx_reg_layout, tx_highz_drvr_en, 0x060); -check_member(usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_1, 0x08c); -check_member(usb3_phy_qserdes_tx_reg_layout, tx_rcv_detect_lvl_2, 0x0a4); - -/* Only for QMP V3 PHY - RX registers */ -struct usb3_phy_qserdes_rx_reg_layout { - u8 _reserved1[8]; - u32 rx_ucdr_fo_gain; - u32 rx_ucdr_so_gain_half; - u8 _reserved2[32]; - u32 rx_ucdr_fastlock_fo_gain; - u32 rx_ucdr_so_saturtn_and_en; - u8 _reserved3[12]; - u32 rx_ucdr_pi_cntrls; - u8 _reserved4[120]; - u32 rx_vga_cal_ctrl2; - u8 _reserved5[16]; - u32 rx_rx_equ_adap_ctrl2; - u32 rx_rx_equ_adap_ctrl3; - u32 rx_rx_equ_adap_ctrl4; - u8 _reserved6[24]; - u32 rx_rx_eq_offset_adap_ctrl1; - u32 rx_rx_offset_adap_ctrl2; - u32 rx_sigdet_enables; - u32 rx_sigdet_ctrl; - u8 _reserved7[4]; - u32 rx_sigdet_deglitch_ctrl; - u32 rx_rx_band; - u8 _reserved8[80]; - u32 rx_rx_mode_00; -}; -check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fo_gain, 0x008); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_gain_half, 0x00c); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fastlock_fo_gain, 0x030); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_saturtn_and_en, 0x034); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_pi_cntrls, 0x044); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_vga_cal_ctrl2, 0x0c0); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl2, 0x0d4); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl3, 0x0d8); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl4, 0x0dc); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_eq_offset_adap_ctrl1, 0x0f8); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_offset_adap_ctrl2, 0x0fc); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_enables, 0x100); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_ctrl, 0x104); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_deglitch_ctrl, 0x10c); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_band, 0x110); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_mode_00, 0x164); - -/* Only for QMP V3 PHY - PCS registers */ -struct usb3_phy_pcs_reg_layout { - u32 pcs_sw_reset; - u32 pcs_power_down_control; - u32 pcs_start_control; - u32 pcs_txmgn_v0; - u32 pcs_txmgn_v1; - u32 pcs_txmgn_v2; - u32 pcs_txmgn_v3; - u32 pcs_txmgn_v4; - u32 pcs_txmgn_ls; - u32 pcs_txdeemph_m6db_v0; - u32 pcs_txdeemph_m3p5db_v0; - u32 pcs_txdeemph_m6db_v1; - u32 pcs_txdeemph_m3p5db_v1; - u32 pcs_txdeemph_m6db_v2; - u32 pcs_txdeemph_m3p5db_v2; - u32 pcs_txdeemph_m6db_v3; - u32 pcs_txdeemph_m3p5db_v3; - u32 pcs_txdeemph_m6db_v4; - u32 pcs_txdeemph_m3p5db_v4; - u32 pcs_txdeemph_m6db_ls; - u32 pcs_txdeemph_m3p5db_ls; - u8 _reserved1[8]; - u32 pcs_rate_slew_cntrl; - u8 _reserved2[4]; - u32 pcs_power_state_config2; - u8 _reserved3[8]; - u32 pcs_rcvr_dtct_dly_p1u2_l; - u32 pcs_rcvr_dtct_dly_p1u2_h; - u32 pcs_rcvr_dtct_dly_u3_l; - u32 pcs_rcvr_dtct_dly_u3_h; - u32 pcs_lock_detect_config1; - u32 pcs_lock_detect_config2; - u32 pcs_lock_detect_config3; - u32 pcs_tsync_rsync_time; - u8 _reserved4[16]; - u32 pcs_pwrup_reset_dly_time_auxclk; - u8 _reserved5[12]; - u32 pcs_lfps_ecstart_eqtlock; - u8 _reserved6[4]; - u32 pcs_rxeqtraining_wait_time; - u32 pcs_rxeqtraining_run_time; - u8 _reserved7[4]; - u32 pcs_fll_ctrl1; - u32 pcs_fll_ctrl2; - u32 pcs_fll_cnt_val_l; - u32 pcs_fll_cnt_val_h_tol; - u32 pcs_fll_man_code; - u32 pcs_autonomous_mode_ctrl; - u8 _reserved8[152]; - u32 pcs_ready_status; - u8 _reserved9[96]; - u32 pcs_rx_sigdet_lvl; - u8 _reserved10[48]; - u32 pcs_refgen_req_config1; - u32 pcs_refgen_req_config2; -}; -check_member(usb3_phy_pcs_reg_layout, pcs_sw_reset, 0x000); -check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v0, 0x00c); -check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v1, 0x010); -check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v2, 0x014); -check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v3, 0x018); -check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v4, 0x01c); -check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_ls, 0x020); -check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v0, 0x024); -check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v0, 0x028); -check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v1, 0x02c); -check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v1, 0x030); -check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v2, 0x034); -check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v2, 0x038); -check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v3, 0x03c); -check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v3, 0x040); -check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v4, 0x044); -check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v4, 0x048); -check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_ls, 0x04c); -check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_ls, 0x050); -check_member(usb3_phy_pcs_reg_layout, pcs_rate_slew_cntrl, 0x05c); -check_member(usb3_phy_pcs_reg_layout, pcs_power_state_config2, 0x064); -check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_p1u2_l, 0x070); -check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_p1u2_h, 0x074); -check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_u3_l, 0x078); -check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_u3_h, 0x07c); -check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config1, 0x080); -check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config2, 0x084); -check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config3, 0x088); -check_member(usb3_phy_pcs_reg_layout, pcs_pwrup_reset_dly_time_auxclk, 0x0a0); -check_member(usb3_phy_pcs_reg_layout, pcs_rxeqtraining_wait_time, 0x0b8); -check_member(usb3_phy_pcs_reg_layout, pcs_fll_cnt_val_h_tol, 0x0d0); -check_member(usb3_phy_pcs_reg_layout, pcs_autonomous_mode_ctrl, 0x0d8); -check_member(usb3_phy_pcs_reg_layout, pcs_ready_status, 0x174); -check_member(usb3_phy_pcs_reg_layout, pcs_refgen_req_config2, 0x210); - -static struct usb3_phy_qserdes_com_reg_layout *const qserdes_com_reg_layout = - (void *)QMP_PHY_QSERDES_COM_REG_BASE; -static struct usb3_phy_qserdes_tx_reg_layout *const qserdes_tx_reg_layout = - (void *)QMP_PHY_QSERDES_TX_REG_BASE; -static struct usb3_phy_qserdes_rx_reg_layout *const qserdes_rx_reg_layout = - (void *)QMP_PHY_QSERDES_RX_REG_BASE; -static struct usb3_phy_pcs_reg_layout *const pcs_reg_layout = - (void *)QMP_PHY_PCS_REG_BASE; - -static struct usb3_phy_qserdes_com_reg_layout *const - uniphy_qserdes_com_reg_layout = - (void *)QMP_UNIPHY_QSERDES_COM_REG_BASE; -static struct usb3_phy_qserdes_tx_reg_layout - *const uniphy_qserdes_tx_reg_layout = - (void *)QMP_UNIPHY_QSERDES_TX_REG_BASE; -static struct usb3_phy_qserdes_rx_reg_layout - *const uniphy_qserdes_rx_reg_layout = - (void *)QMP_UNIPHY_QSERDES_RX_REG_BASE; -static struct usb3_phy_pcs_reg_layout *const uniphy_pcs_reg_layout = - (void *)QMP_UNIPHY_PCS_REG_BASE; - -struct usb_dwc3 { - u32 sbuscfg0; - u32 sbuscfg1; - u32 txthrcfg; - u32 rxthrcfg; - u32 ctl; - u32 pmsts; - u32 sts; - u32 uctl1; - u32 snpsid; - u32 gpio; - u32 uid; - u32 uctl; - u64 buserraddr; - u64 prtbimap; - u8 reserved1[32]; - u32 dbgfifospace; - u32 dbgltssm; - u32 dbglnmcc; - u32 dbgbmu; - u32 dbglspmux; - u32 dbglsp; - u32 dbgepinfo0; - u32 dbgepinfo1; - u64 prtbimap_hs; - u64 prtbimap_fs; - u8 reserved2[112]; - u32 usb2phycfg; - u8 reserved3[60]; - u32 usb2i2cctl; - u8 reserved4[60]; - u32 usb2phyacc; - u8 reserved5[60]; - u32 usb3pipectl; - u8 reserved6[60]; -}; -check_member(usb_dwc3, usb3pipectl, 0x1c0); - -static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { - {&qserdes_com_reg_layout->com_pll_ivco, 0x07}, - {&qserdes_com_reg_layout->com_sysclk_en_sel, 0x14}, - {&qserdes_com_reg_layout->com_bias_en_clkbuflr_en, 0x08}, - {&qserdes_com_reg_layout->com_clk_select, 0x30}, - {&qserdes_com_reg_layout->com_sys_clk_ctrl, 0x02}, - {&qserdes_com_reg_layout->com_resetsm_ctrl2, 0x08}, - {&qserdes_com_reg_layout->com_cmn_config, 0x16}, - {&qserdes_com_reg_layout->com_svs_mode_clk_sel, 0x01}, - {&qserdes_com_reg_layout->com_hsclk_sel, 0x80}, - {&qserdes_com_reg_layout->com_dec_start_mode0, 0x82}, - {&qserdes_com_reg_layout->com_div_frac_start1_mode0, 0xab}, - {&qserdes_com_reg_layout->com_div_frac_start2_mode0, 0xea}, - {&qserdes_com_reg_layout->com_div_frac_start3_mode0, 0x02}, - {&qserdes_com_reg_layout->com_cp_ctrl_mode0, 0x06}, - {&qserdes_com_reg_layout->com_pll_rctrl_mode0, 0x16}, - {&qserdes_com_reg_layout->com_pll_cctrl_mode0, 0x36}, - {&qserdes_com_reg_layout->com_integloop_gain1_mode0, 0x00}, - {&qserdes_com_reg_layout->com_integloop_gain0_mode0, 0x3f}, - {&qserdes_com_reg_layout->com_vco_tune2_mode0, 0x01}, - {&qserdes_com_reg_layout->com_vco_tune1_mode0, 0xc9}, - {&qserdes_com_reg_layout->com_coreclk_div_mode0, 0x0a}, - {&qserdes_com_reg_layout->com_lock_cmp3_mode0, 0x00}, - {&qserdes_com_reg_layout->com_lock_cmp2_mode0, 0x34}, - {&qserdes_com_reg_layout->com_lock_cmp1_mode0, 0x15}, - {&qserdes_com_reg_layout->com_lock_cmp_en, 0x04}, - {&qserdes_com_reg_layout->com_core_clk_en, 0x00}, - {&qserdes_com_reg_layout->com_lock_cmp_cfg, 0x00}, - {&qserdes_com_reg_layout->com_vco_tune_map, 0x00}, - {&qserdes_com_reg_layout->com_sysclk_buf_enable, 0x0a}, - {&qserdes_com_reg_layout->com_ssc_en_center, 0x01}, - {&qserdes_com_reg_layout->com_ssc_per1, 0x31}, - {&qserdes_com_reg_layout->com_ssc_per2, 0x01}, - {&qserdes_com_reg_layout->com_ssc_adj_per1, 0x00}, - {&qserdes_com_reg_layout->com_ssc_adj_per2, 0x00}, - {&qserdes_com_reg_layout->com_ssc_step_size1, 0x85}, - {&qserdes_com_reg_layout->com_ssc_step_size2, 0x07}, -}; - -static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { - {&qserdes_tx_reg_layout->tx_highz_drvr_en, 0x10}, - {&qserdes_tx_reg_layout->tx_rcv_detect_lvl_2, 0x12}, - {&qserdes_tx_reg_layout->tx_lane_mode_1, 0x16}, - {&qserdes_tx_reg_layout->tx_res_code_lane_offset_rx, 0x09}, - {&qserdes_tx_reg_layout->tx_res_code_lane_offset_tx, 0x06}, -}; - -static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { - {&qserdes_rx_reg_layout->rx_ucdr_fastlock_fo_gain, 0x0b}, - {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl2, 0x0f}, - {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl3, 0x4e}, - {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl4, 0x18}, - {&qserdes_rx_reg_layout->rx_rx_eq_offset_adap_ctrl1, 0x77}, - {&qserdes_rx_reg_layout->rx_rx_offset_adap_ctrl2, 0x80}, - {&qserdes_rx_reg_layout->rx_sigdet_ctrl, 0x03}, - {&qserdes_rx_reg_layout->rx_sigdet_deglitch_ctrl, 0x16}, - {&qserdes_rx_reg_layout->rx_ucdr_so_saturtn_and_en, 0x75}, - {&qserdes_rx_reg_layout->rx_ucdr_pi_cntrls, 0x80}, - {&qserdes_rx_reg_layout->rx_ucdr_fo_gain, 0x0a}, - {&qserdes_rx_reg_layout->rx_ucdr_so_gain_half, 0x06}, - {&qserdes_rx_reg_layout->rx_sigdet_enables, 0x00}, -}; - -static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { - /* FLL settings */ - {&pcs_reg_layout->pcs_fll_ctrl2, 0x83}, - {&pcs_reg_layout->pcs_fll_cnt_val_l, 0x09}, - {&pcs_reg_layout->pcs_fll_cnt_val_h_tol, 0xa2}, - {&pcs_reg_layout->pcs_fll_man_code, 0x40}, - {&pcs_reg_layout->pcs_fll_ctrl1, 0x02}, - - /* Lock Det settings */ - {&pcs_reg_layout->pcs_lock_detect_config1, 0xd1}, - {&pcs_reg_layout->pcs_lock_detect_config2, 0x1f}, - {&pcs_reg_layout->pcs_lock_detect_config3, 0x47}, - {&pcs_reg_layout->pcs_power_state_config2, 0x1b}, - - {&pcs_reg_layout->pcs_rx_sigdet_lvl, 0xba}, - {&pcs_reg_layout->pcs_txmgn_v0, 0x9f}, - {&pcs_reg_layout->pcs_txmgn_v1, 0x9f}, - {&pcs_reg_layout->pcs_txmgn_v2, 0xb7}, - {&pcs_reg_layout->pcs_txmgn_v3, 0x4e}, - {&pcs_reg_layout->pcs_txmgn_v4, 0x65}, - {&pcs_reg_layout->pcs_txmgn_ls, 0x6b}, - {&pcs_reg_layout->pcs_txdeemph_m6db_v0, 0x15}, - {&pcs_reg_layout->pcs_txdeemph_m3p5db_v0, 0x0d}, - {&pcs_reg_layout->pcs_txdeemph_m6db_v1, 0x15}, - {&pcs_reg_layout->pcs_txdeemph_m3p5db_v1, 0x0d}, - {&pcs_reg_layout->pcs_txdeemph_m6db_v2, 0x15}, - {&pcs_reg_layout->pcs_txdeemph_m3p5db_v2, 0x0d}, - {&pcs_reg_layout->pcs_txdeemph_m6db_v3, 0x15}, - {&pcs_reg_layout->pcs_txdeemph_m3p5db_v3, 0x1d}, - {&pcs_reg_layout->pcs_txdeemph_m6db_v4, 0x15}, - {&pcs_reg_layout->pcs_txdeemph_m3p5db_v4, 0x0d}, - {&pcs_reg_layout->pcs_txdeemph_m6db_ls, 0x15}, - {&pcs_reg_layout->pcs_txdeemph_m3p5db_ls, 0x0d}, - {&pcs_reg_layout->pcs_rate_slew_cntrl, 0x02}, - {&pcs_reg_layout->pcs_pwrup_reset_dly_time_auxclk, 0x04}, - {&pcs_reg_layout->pcs_tsync_rsync_time, 0x44}, - {&pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_l, 0xe7}, - {&pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_h, 0x03}, - {&pcs_reg_layout->pcs_rcvr_dtct_dly_u3_l, 0x40}, - {&pcs_reg_layout->pcs_rcvr_dtct_dly_u3_h, 0x00}, - {&pcs_reg_layout->pcs_rxeqtraining_wait_time, 0x75}, - {&pcs_reg_layout->pcs_lfps_ecstart_eqtlock, 0x86}, - {&pcs_reg_layout->pcs_rxeqtraining_run_time, 0x13}, -}; - -static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = { - {&uniphy_qserdes_com_reg_layout->com_pll_ivco, 0x07}, - {&uniphy_qserdes_com_reg_layout->com_sysclk_en_sel, 0x14}, - {&uniphy_qserdes_com_reg_layout->com_bias_en_clkbuflr_en, 0x04}, - {&uniphy_qserdes_com_reg_layout->com_clk_select, 0x30}, - {&uniphy_qserdes_com_reg_layout->com_sys_clk_ctrl, 0x02}, - {&uniphy_qserdes_com_reg_layout->com_resetsm_ctrl2, 0x08}, - {&uniphy_qserdes_com_reg_layout->com_cmn_config, 0x06}, - {&uniphy_qserdes_com_reg_layout->com_svs_mode_clk_sel, 0x01}, - {&uniphy_qserdes_com_reg_layout->com_hsclk_sel, 0x80}, - {&uniphy_qserdes_com_reg_layout->com_dec_start_mode0, 0x82}, - {&uniphy_qserdes_com_reg_layout->com_div_frac_start1_mode0, 0xab}, - {&uniphy_qserdes_com_reg_layout->com_div_frac_start2_mode0, 0xea}, - {&uniphy_qserdes_com_reg_layout->com_div_frac_start3_mode0, 0x02}, - {&uniphy_qserdes_com_reg_layout->com_cp_ctrl_mode0, 0x06}, - {&uniphy_qserdes_com_reg_layout->com_pll_rctrl_mode0, 0x16}, - {&uniphy_qserdes_com_reg_layout->com_pll_cctrl_mode0, 0x36}, - {&uniphy_qserdes_com_reg_layout->com_integloop_gain1_mode0, 0x00}, - {&uniphy_qserdes_com_reg_layout->com_integloop_gain0_mode0, 0x3f}, - {&uniphy_qserdes_com_reg_layout->com_vco_tune2_mode0, 0x01}, - {&uniphy_qserdes_com_reg_layout->com_vco_tune1_mode0, 0xc9}, - {&uniphy_qserdes_com_reg_layout->com_coreclk_div_mode0, 0x0a}, - {&uniphy_qserdes_com_reg_layout->com_lock_cmp3_mode0, 0x00}, - {&uniphy_qserdes_com_reg_layout->com_lock_cmp2_mode0, 0x34}, - {&uniphy_qserdes_com_reg_layout->com_lock_cmp1_mode0, 0x15}, - {&uniphy_qserdes_com_reg_layout->com_lock_cmp_en, 0x04}, - {&uniphy_qserdes_com_reg_layout->com_core_clk_en, 0x00}, - {&uniphy_qserdes_com_reg_layout->com_lock_cmp_cfg, 0x00}, - {&uniphy_qserdes_com_reg_layout->com_vco_tune_map, 0x00}, - {&uniphy_qserdes_com_reg_layout->com_sysclk_buf_enable, 0x0a}, - {&uniphy_qserdes_com_reg_layout->com_ssc_en_center, 0x01}, - {&uniphy_qserdes_com_reg_layout->com_ssc_per1, 0x31}, - {&uniphy_qserdes_com_reg_layout->com_ssc_per2, 0x01}, - {&uniphy_qserdes_com_reg_layout->com_ssc_adj_per1, 0x00}, - {&uniphy_qserdes_com_reg_layout->com_ssc_adj_per2, 0x00}, - {&uniphy_qserdes_com_reg_layout->com_ssc_step_size1, 0x85}, - {&uniphy_qserdes_com_reg_layout->com_ssc_step_size2, 0x07}, -}; - -static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = { - {&uniphy_qserdes_tx_reg_layout->tx_highz_drvr_en, 0x10}, - {&uniphy_qserdes_tx_reg_layout->tx_rcv_detect_lvl_2, 0x12}, - {&uniphy_qserdes_tx_reg_layout->tx_lane_mode_1, 0xc6}, - {&uniphy_qserdes_tx_reg_layout->tx_res_code_lane_offset_rx, 0x06}, - {&uniphy_qserdes_tx_reg_layout->tx_res_code_lane_offset_tx, 0x06}, -}; - -static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = { - {&uniphy_qserdes_rx_reg_layout->rx_vga_cal_ctrl2, 0x0c}, - {&uniphy_qserdes_rx_reg_layout->rx_rx_mode_00, 0x50}, - {&uniphy_qserdes_rx_reg_layout->rx_ucdr_fastlock_fo_gain, 0x0b}, - {&uniphy_qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl2, 0x0e}, - {&uniphy_qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl3, 0x4e}, - {&uniphy_qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl4, 0x18}, - {&uniphy_qserdes_rx_reg_layout->rx_rx_eq_offset_adap_ctrl1, 0x77}, - {&uniphy_qserdes_rx_reg_layout->rx_rx_offset_adap_ctrl2, 0x80}, - {&uniphy_qserdes_rx_reg_layout->rx_sigdet_ctrl, 0x03}, - {&uniphy_qserdes_rx_reg_layout->rx_sigdet_deglitch_ctrl, 0x1c}, - {&uniphy_qserdes_rx_reg_layout->rx_ucdr_so_saturtn_and_en, 0x75}, - {&uniphy_qserdes_rx_reg_layout->rx_ucdr_pi_cntrls, 0x80}, - {&uniphy_qserdes_rx_reg_layout->rx_ucdr_fo_gain, 0x0a}, - {&uniphy_qserdes_rx_reg_layout->rx_ucdr_so_gain_half, 0x06}, - {&uniphy_qserdes_rx_reg_layout->rx_sigdet_enables, 0x00}, -}; - -static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { - /* FLL settings */ - {&uniphy_pcs_reg_layout->pcs_fll_ctrl2, 0x83}, - {&uniphy_pcs_reg_layout->pcs_fll_cnt_val_l, 0x09}, - {&uniphy_pcs_reg_layout->pcs_fll_cnt_val_h_tol, 0xa2}, - {&uniphy_pcs_reg_layout->pcs_fll_man_code, 0x40}, - {&uniphy_pcs_reg_layout->pcs_fll_ctrl1, 0x02}, - - /* Lock Det settings */ - {&uniphy_pcs_reg_layout->pcs_lock_detect_config1, 0xd1}, - {&uniphy_pcs_reg_layout->pcs_lock_detect_config2, 0x1f}, - {&uniphy_pcs_reg_layout->pcs_lock_detect_config3, 0x47}, - {&uniphy_pcs_reg_layout->pcs_power_state_config2, 0x1b}, - - {&uniphy_pcs_reg_layout->pcs_rx_sigdet_lvl, 0xba}, - {&uniphy_pcs_reg_layout->pcs_txmgn_v0, 0x9f}, - {&uniphy_pcs_reg_layout->pcs_txmgn_v1, 0x9f}, - {&uniphy_pcs_reg_layout->pcs_txmgn_v2, 0xb5}, - {&uniphy_pcs_reg_layout->pcs_txmgn_v3, 0x4c}, - {&uniphy_pcs_reg_layout->pcs_txmgn_v4, 0x64}, - {&uniphy_pcs_reg_layout->pcs_txmgn_ls, 0x6a}, - {&uniphy_pcs_reg_layout->pcs_txdeemph_m6db_v0, 0x15}, - {&uniphy_pcs_reg_layout->pcs_txdeemph_m3p5db_v0, 0x0d}, - {&uniphy_pcs_reg_layout->pcs_txdeemph_m6db_v1, 0x15}, - {&uniphy_pcs_reg_layout->pcs_txdeemph_m3p5db_v1, 0x0d}, - {&uniphy_pcs_reg_layout->pcs_txdeemph_m6db_v2, 0x15}, - {&uniphy_pcs_reg_layout->pcs_txdeemph_m3p5db_v2, 0x0d}, - {&uniphy_pcs_reg_layout->pcs_txdeemph_m6db_v3, 0x15}, - {&uniphy_pcs_reg_layout->pcs_txdeemph_m3p5db_v3, 0x1d}, - {&uniphy_pcs_reg_layout->pcs_txdeemph_m6db_v4, 0x15}, - {&uniphy_pcs_reg_layout->pcs_txdeemph_m3p5db_v4, 0x0d}, - {&uniphy_pcs_reg_layout->pcs_txdeemph_m6db_ls, 0x15}, - {&uniphy_pcs_reg_layout->pcs_txdeemph_m3p5db_ls, 0x0d}, - {&uniphy_pcs_reg_layout->pcs_rate_slew_cntrl, 0x02}, - {&uniphy_pcs_reg_layout->pcs_pwrup_reset_dly_time_auxclk, 0x04}, - {&uniphy_pcs_reg_layout->pcs_tsync_rsync_time, 0x44}, - {&uniphy_pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_l, 0xe7}, - {&uniphy_pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_h, 0x03}, - {&uniphy_pcs_reg_layout->pcs_rcvr_dtct_dly_u3_l, 0x40}, - {&uniphy_pcs_reg_layout->pcs_rcvr_dtct_dly_u3_h, 0x00}, - {&uniphy_pcs_reg_layout->pcs_rxeqtraining_wait_time, 0x75}, - {&uniphy_pcs_reg_layout->pcs_lfps_ecstart_eqtlock, 0x86}, - {&uniphy_pcs_reg_layout->pcs_rxeqtraining_run_time, 0x13}, - {&uniphy_pcs_reg_layout->pcs_refgen_req_config1, 0x21}, - {&uniphy_pcs_reg_layout->pcs_refgen_req_config2, 0x60}, -}; - -struct usb_dwc3_cfg { - struct usb_dwc3 *usb_host_dwc3; - struct usb_qusb_phy_pll *qusb_phy_pll; - struct usb_qusb_phy_dig *qusb_phy_dig; - /* Init sequence for QMP PHY blocks - serdes, tx, rx, pcs */ - const struct qmp_phy_init_tbl *serdes_tbl; - int serdes_tbl_num; - const struct qmp_phy_init_tbl *tx_tbl; - int tx_tbl_num; - const struct qmp_phy_init_tbl *rx_tbl; - int rx_tbl_num; - const struct qmp_phy_init_tbl *pcs_tbl; - int pcs_tbl_num; - struct usb3_phy_pcs_reg_layout *qmp_pcs_reg; - - u32 *usb3_bcr; - u32 *qusb2phy_bcr; - u32 *gcc_usb3phy_bcr_reg; - u32 *gcc_qmpphy_bcr_reg; - struct usb_board_data *board_data; - u32 efuse_offset; -}; - -static struct usb_dwc3_cfg usb_port0 = { - .usb_host_dwc3 = (void *)USB_HOST0_DWC3_BASE, - .qusb_phy_pll = (void *)QUSB_PRIM_PHY_BASE, - .qusb_phy_dig = (void *)QUSB_PRIM_PHY_DIG_BASE, - .serdes_tbl = qmp_v3_usb3_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), - .tx_tbl = qmp_v3_usb3_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), - .rx_tbl = qmp_v3_usb3_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), - .pcs_tbl = qmp_v3_usb3_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), - .qmp_pcs_reg = (void *)QMP_PHY_PCS_REG_BASE, - .usb3_bcr = &gcc->usb30_prim_bcr, - .qusb2phy_bcr = &gcc->qusb2phy_prim_bcr, - .gcc_usb3phy_bcr_reg = &gcc->usb3_dp_phy_prim_bcr, - .gcc_qmpphy_bcr_reg = &gcc->usb3_phy_prim_bcr, - .efuse_offset = 25, -}; -static struct usb_dwc3_cfg usb_port1 = { - .usb_host_dwc3 = (void *)USB_HOST1_DWC3_BASE, - .qusb_phy_pll = (void *)QUSB_SEC_PHY_BASE, - .qusb_phy_dig = (void *)QUSB_SEC_PHY_DIG_BASE, - .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl), - .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl), - .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl), - .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl), - .qmp_pcs_reg = (void *)QMP_UNIPHY_PCS_REG_BASE, - .usb3_bcr = &gcc->usb30_sec_bcr, - .qusb2phy_bcr = &gcc->qusb2phy_sec_bcr, - .gcc_usb3phy_bcr_reg = &gcc->usb3phy_phy_sec_bcr, - .gcc_qmpphy_bcr_reg = &gcc->usb3_phy_sec_bcr, - .efuse_offset = 30, -}; - -static struct qfprom_corr * const qfprom_corr_efuse = (void *)QFPROM_BASE; - -static void reset_usb(struct usb_dwc3_cfg *dwc3) -{ - /* Assert Core reset */ - clock_reset_bcr(dwc3->usb3_bcr, 1); - - /* Assert QUSB PHY reset */ - clock_reset_bcr(dwc3->qusb2phy_bcr, 1); - - /* Assert QMP PHY reset */ - clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 1); - clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 1); -} - -void reset_usb0(void) -{ - /* Before Resetting PHY, put Core in Reset */ - printk(BIOS_INFO, "Starting DWC3 and PHY resets for USB(0)\n"); - - reset_usb(&usb_port0); -} - -void reset_usb1(void) -{ - /* Before Resetting PHY, put Core in Reset */ - printk(BIOS_INFO, "Starting DWC3 and PHY resets for USB(1)\n"); - - reset_usb(&usb_port1); -} -/* - * Update board specific PHY tuning override values that specified from - * board file. - */ -static void qusb2_phy_override_phy_params(struct usb_dwc3_cfg *dwc3) -{ - /* Override preemphasis value */ - write32(&dwc3->qusb_phy_dig->tune1, - dwc3->board_data->port_tune1); - - /* Override BIAS_CTRL_2 to reduce the TX swing overshooting. */ - write32(&dwc3->qusb_phy_pll->bias_ctrl_2, - dwc3->board_data->pll_bias_control_2); - - /* Override IMP_RES_OFFSET value */ - write32(&dwc3->qusb_phy_dig->imp_ctrl1, - dwc3->board_data->imp_ctrl1); -} - -/* - * Fetches HS Tx tuning value from efuse register and sets the - * QUSB2PHY_PORT_TUNE1/2 register. - * For error case, skip setting the value and use the default value. - */ -static void qusb2_phy_set_tune_param(struct usb_dwc3_cfg *dwc3) -{ - /* - * Efuse registers 4 bit value specifies tuning for HSTX - * output current in TUNE1 Register. Hence Extract 4 bits from - * EFUSE at correct position. - */ - - const int efuse_bits = 4; - int bit_pos = dwc3->efuse_offset; - - u32 bit_mask = (1 << efuse_bits) - 1; - u32 tune_val = - (read32(&qfprom_corr_efuse->qusb_hstx_trim_lsb) >> bit_pos) - & bit_mask; - - if (bit_pos + efuse_bits > 32) { - /* - * Value split between two EFUSE registers, - * get the second part. - */ - int done_bits = 32 - bit_pos; - - bit_mask = (1 << (efuse_bits - done_bits)) - 1; - tune_val |= - (read32(&qfprom_corr_efuse->qusb_hstx_trim_msb) & - bit_mask) << done_bits; - } - - /* - * if efuse reg is updated (i.e non-zero) then use it to program - * tune parameters. - */ - if (tune_val) - clrsetbits32(&dwc3->qusb_phy_dig->tune1, - PORT_TUNE1_MASK, tune_val << 4); -} - -static void tune_phy(struct usb_dwc3_cfg *dwc3, struct usb_qusb_phy_dig *phy) -{ - write32(&phy->pwr_ctrl2, QUSB2PHY_PWR_CTRL2); - /* IMP_CTRL1: Control the impedance reduction */ - write32(&phy->imp_ctrl1, QUSB2PHY_IMP_CTRL1); - /* IMP_CTRL2: Impedance offset/mapping slope */ - write32(&phy->imp_ctrl2, QUSB2PHY_IMP_CTRL1); - write32(&phy->chg_ctrl2, QUSB2PHY_IMP_CTRL2); - /* - * TUNE1: Sets HS Impedance to approx 45 ohms - * then override with efuse value. - */ - write32(&phy->tune1, QUSB2PHY_PORT_TUNE1); - /* TUNE2: Tuning for HS Disconnect Level */ - write32(&phy->tune2, QUSB2PHY_PORT_TUNE2); - /* TUNE3: Tune squelch range */ - write32(&phy->tune3, QUSB2PHY_PORT_TUNE3); - /* TUNE4: Sets EOP_DLY(Squelch rising edge to linestate falling edge) */ - write32(&phy->tune4, QUSB2PHY_PORT_TUNE4); - write32(&phy->tune5, QUSB2PHY_PORT_TUNE5); - - if (dwc3->board_data) { - /* Override board specific PHY tuning values */ - qusb2_phy_override_phy_params(dwc3); - - /* Set efuse value for tuning the PHY */ - qusb2_phy_set_tune_param(dwc3); - } -} - -static void hs_qusb_phy_init(struct usb_dwc3_cfg *dwc3) -{ - /* PWR_CTRL: set the power down bit to disable the PHY */ - setbits32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); - - write32(&dwc3->qusb_phy_pll->analog_controls_two, - QUSB2PHY_PLL_ANALOG_CONTROLS_TWO); - write32(&dwc3->qusb_phy_pll->clock_inverters, - QUSB2PHY_PLL_CLOCK_INVERTERS); - write32(&dwc3->qusb_phy_pll->cmode, - QUSB2PHY_PLL_CMODE); - write32(&dwc3->qusb_phy_pll->lock_delay, - QUSB2PHY_PLL_LOCK_DELAY); - write32(&dwc3->qusb_phy_pll->dig_tim, - QUSB2PHY_PLL_DIGITAL_TIMERS_TWO); - write32(&dwc3->qusb_phy_pll->bias_ctrl_1, - QUSB2PHY_PLL_BIAS_CONTROL_1); - write32(&dwc3->qusb_phy_pll->bias_ctrl_2, - QUSB2PHY_PLL_BIAS_CONTROL_2); - - tune_phy(dwc3, dwc3->qusb_phy_dig); - - /* PWR_CTRL1: Clear the power down bit to enable the PHY */ - clrbits32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); - - write32(&dwc3->qusb_phy_dig->debug_ctrl2, - DEBUG_CTRL2_MUX_PLL_LOCK_STATUS); - - /* - * DEBUG_STAT5: wait for 160uS for PLL lock; - * vstatus[0] changes from 0 to 1. - */ - long lock_us = wait_us(160, read32(&dwc3->qusb_phy_dig->debug_stat5) & - VSTATUS_PLL_LOCK_STATUS_MASK); - if (!lock_us) - printk(BIOS_ERR, "ERROR: QUSB PHY PLL LOCK fails\n"); - else - printk(BIOS_DEBUG, "QUSB PHY initialized and locked in %ldus\n", - lock_us); -} - -static void qcom_qmp_phy_configure(const struct qmp_phy_init_tbl tbl[], - int num) -{ - int i; - const struct qmp_phy_init_tbl *t = tbl; - - if (!t) - return; - - for (i = 0; i < num; i++, t++) - write32(t->address, t->val); -} - -static void ss_qmp_phy_init(struct usb_dwc3_cfg *dwc3) -{ - /* power up USB3 PHY */ - write32(&dwc3->qmp_pcs_reg->pcs_power_down_control, 0x01); - - /* Serdes configuration */ - qcom_qmp_phy_configure(dwc3->serdes_tbl, dwc3->serdes_tbl_num); - /* Tx, Rx, and PCS configurations */ - qcom_qmp_phy_configure(dwc3->tx_tbl, dwc3->tx_tbl_num); - qcom_qmp_phy_configure(dwc3->rx_tbl, dwc3->rx_tbl_num); - qcom_qmp_phy_configure(dwc3->pcs_tbl, dwc3->pcs_tbl_num); - - /* perform software reset of PCS/Serdes */ - write32(&dwc3->qmp_pcs_reg->pcs_sw_reset, 0x00); - /* start PCS/Serdes to operation mode */ - write32(&dwc3->qmp_pcs_reg->pcs_start_control, 0x03); - - /* - * Wait for PHY initialization to be done - * PCS_STATUS: wait for 1ms for PHY STATUS; - * SW can continuously check for PHYSTATUS = 1.b0. - */ - long lock_us = wait_us(1000, - !(read32(&dwc3->qmp_pcs_reg->pcs_ready_status) & - USB3_PCS_PHYSTATUS)); - if (!lock_us) - printk(BIOS_ERR, "ERROR: QMP PHY PLL LOCK fails:\n"); - else - printk(BIOS_DEBUG, "QMP PHY initialized and locked in %ldus\n", - lock_us); -} - -static void setup_dwc3(struct usb_dwc3 *dwc3) -{ - /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */ - clrsetbits32(&dwc3->usb3pipectl, - DWC3_GUSB3PIPECTL_DELAYP1TRANS, - DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX); - - /* - * Configure USB phy interface of DWC3 core. - * 1. Select UTMI+ PHY with 16-bit interface. - * 2. Set USBTRDTIM to the corresponding value - * according to the UTMI+ PHY interface. - */ - clrsetbits32(&dwc3->usb2phycfg, - (DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK | - DWC3_GUSB2PHYCFG_PHYIF_MASK), - (DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | - DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT))); - - clrsetbits32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | - DWC3_GCTL_DISSCRAMBLE), - DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG); - - /* configure controller in Host mode */ - clrsetbits32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), - DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST)); - printk(BIOS_SPEW, "Configure USB in Host mode\n"); -} - -/* Initialization of DWC3 Core and PHY */ -static void setup_usb_host(struct usb_dwc3_cfg *dwc3, - struct usb_board_data *board_data) -{ - dwc3->board_data = board_data; - - /* Clear core reset. */ - clock_reset_bcr(dwc3->usb3_bcr, 0); - - /* Clear QUSB PHY reset. */ - clock_reset_bcr(dwc3->qusb2phy_bcr, 0); - - /* Initialize QUSB PHY */ - hs_qusb_phy_init(dwc3); - - /* Clear QMP PHY resets. */ - clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 0); - clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 0); - - /* Initialize QMP PHY */ - ss_qmp_phy_init(dwc3); - - setup_dwc3(dwc3->usb_host_dwc3); - - printk(BIOS_INFO, "DWC3 and PHY setup finished\n"); -} - -void setup_usb_host0(struct usb_board_data *board_data) -{ - printk(BIOS_INFO, "Setting up USB HOST0 controller.\n"); - setup_usb_host(&usb_port0, board_data); -} - -void setup_usb_host1(struct usb_board_data *board_data) -{ - printk(BIOS_INFO, "Setting up USB HOST1 controller.\n"); - setup_usb_host(&usb_port1, board_data); -} diff --git a/util/docker/coreboot.org-status/board-status.html/tohtml.sh b/util/docker/coreboot.org-status/board-status.html/tohtml.sh index 2606af4..98bbc94 100755 --- a/util/docker/coreboot.org-status/board-status.html/tohtml.sh +++ b/util/docker/coreboot.org-status/board-status.html/tohtml.sh @@ -443,9 +443,6 @@ QUALCOMM_QCS405) cpu_nice="Qualcomm QCS405"; socket_nice="—";; - QUALCOMM_SDM845) - cpu_nice="Qualcomm SDM845"; - socket_nice="—";; ROCKCHIP_RK3288) cpu_nice="Rockchip RK3288"; socket_nice="—";; diff --git a/util/qualcomm/scripts/cmm/debug_cb_845.cmm b/util/qualcomm/scripts/cmm/debug_cb_845.cmm deleted file mode 100644 index 696f1c0..0000000 --- a/util/qualcomm/scripts/cmm/debug_cb_845.cmm +++ /dev/null @@ -1,113 +0,0 @@ -;============================================================================ -;## SPDX-License-Identifier: GPL-2.0-only -;============================================================================ -; Name: -; debug_cb_845.cmm -; -; Description: -; Debug coreboot 845 front-end -;============================================================================ - -;============================================================================ -; CMM script variables -;============================================================================ - -LOCAL &TargetPkg - -GLOBAL &BBEntryAddr // Bootblock Entry -GLOBAL &BBExitAddr // Bootblock Exit to Xbl-Sec -GLOBAL &VEREntryAddr // Verstage Entry -GLOBAL &ROMEntryAddr // Romstage Entry -GLOBAL &QCLEntryAddr // QCLstage Entry -GLOBAL &RAMEntryAddr // Ramstage Entry -GLOBAL &BL31EntryAddr // BL31 Entry -GLOBAL &DCEntryAddr // Depthcharge Entry -GLOBAL &KernelEntryAddr // Kernel Entry - -GLOBAL &PreRamConsoleAddr -GLOBAL &RamConsoleAddr -GLOBAL &PreRamCbfsCache -GLOBAL &VBoot2Work -GLOBAL &Stack -GLOBAL &Ttb -GLOBAL &Timestamp -GLOBAL &CbmemTop -GLOBAL &PostRamCbfsCache - -GLOBAL &CBTablePtr - -;============================================================================ - -;--------------------------------------------------- -; Entry point -;--------------------------------------------------- -ENTRY &ImageName - - // Later these can be parameterized - &TargetPkg="Sdm845Pkg" - - // These settings come from .../src/soc/qualcomm/sdm845/include/soc/memlayout.ld - &BBEntryAddr=0x14816000 - &VEREntryAddr=0x14680000 - &ROMEntryAddr=0x14680000 - &QCLEntryAddr=0x1485AC00 - &RAMEntryAddr=0x9F860000 - &BL31EntryAddr=0x06820000 - &DCEntryAddr=0xB0104800 - &KernelEntryAddr=0x90080000 - - &PreRamConsoleAddr=0x14836400 - &VBoot2Work=0x1482E000 - &Stack=0x14832000 - &Ttb=0x1481E000 - &Timestamp=0x14836000 - &PreRamCbfsCache=0x1483E400 - &CbmemTop=0x280000000 - &PostRamCbfsCache=0x9F800000 - // End of memlayout.ld settings - - // Common commands irrespective of &Mode - PATH - &CwDir=os.pwd() - PATH + &CwDir - - // position at top of coreboot tree - // find depth count for source loading - cd ..\..\..\.. - &srcpath=os.pwd() - - b.sel PROGRAM onchip - sys.u - - b.d /all - - go &BBEntryAddr - wait !run() - -;--------------------------------------------------- -; Setup area and log -;--------------------------------------------------- - area.clear - area.reset - area.create CB_Logs 1000. 8192. - area.select CB_Logs - - winclear - b.d /all - - if FILE.EXIST("C:\TEMP\WIN.CMM") - do C:\TEMP\WIN.CMM - - area.view CB_Logs - - PRINT %String "Source Path: &srcpath" - - symbol.sourcepath.setbasedir &srcpath\src - - // Make parsing simple, upper-case parameters - &ImageName=STRING.UPR("&ImageName") - PRINT "&ImageName" - - DO debug_cb_common.cmm &TargetPkg &srcpath &xblsrcpath &ImageName - - enddo -- To view, visit https://review.coreboot.org/c/coreboot/+/47428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23453e3e47ac336ab61687004470e5e79172cafe Gerrit-Change-Number: 47428 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: Delete mainboard/google/cheza
by Julius Werner (Code Review) 12 Nov '20

12 Nov '20

Hello Patrick Georgi, Stefan Reinauer, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47427 to review the following change. Change subject: Delete mainboard/google/cheza ...................................................................... Delete mainboard/google/cheza Work on this mainboard was abandoned and never finished. It's not really usable in its current state, so let's get rid of it. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I4cd2e2cd0ee69d9846472653a942fa074e2b924d --- M Documentation/security/vboot/list_vboot.md D payloads/libpayload/configs/config.cheza D src/mainboard/google/cheza/Kconfig D src/mainboard/google/cheza/Kconfig.name D src/mainboard/google/cheza/Makefile.inc D src/mainboard/google/cheza/board.h D src/mainboard/google/cheza/board_info.txt D src/mainboard/google/cheza/boardid.c D src/mainboard/google/cheza/bootblock.c D src/mainboard/google/cheza/chromeos.c D src/mainboard/google/cheza/chromeos.fmd D src/mainboard/google/cheza/devicetree.cb D src/mainboard/google/cheza/mainboard.c D src/mainboard/google/cheza/reset.c D src/mainboard/google/cheza/romstage.c 15 files changed, 0 insertions(+), 293 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/47427/1 diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md index 30083f0..c0ccfce 100644 --- a/Documentation/security/vboot/list_vboot.md +++ b/Documentation/security/vboot/list_vboot.md @@ -20,7 +20,6 @@ - Tricky (Dell Chromebox 3010) - Zako (HP Chromebox G1) - Butterfly (HP Pavilion Chromebook 14) -- Cheza - Banon (Acer Chromebook 15 (CB3-532)) - Celes (Samsung Chromebook 3) - Cyan (Acer Chromebook R11 (C738T)) diff --git a/payloads/libpayload/configs/config.cheza b/payloads/libpayload/configs/config.cheza deleted file mode 100644 index 5f60392..0000000 --- a/payloads/libpayload/configs/config.cheza +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_LP_CHROMEOS=y -CONFIG_LP_ARCH_ARM64=y -CONFIG_LP_TIMER_ARM64_ARCH=y diff --git a/src/mainboard/google/cheza/Kconfig b/src/mainboard/google/cheza/Kconfig deleted file mode 100644 index 3f3f756..0000000 --- a/src/mainboard/google/cheza/Kconfig +++ /dev/null @@ -1,46 +0,0 @@ - -config BOARD_GOOGLE_CHEZA_COMMON # Umbrella option to be selected by variants - def_bool n - -if BOARD_GOOGLE_CHEZA_COMMON - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_16384 - select COMMON_CBFS_SPI_WRAPPER - select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_RTC - select EC_GOOGLE_CHROMEEC_SPI - select RTC - select SOC_QUALCOMM_SDM845 - select SPI_FLASH - select SPI_FLASH_WINBOND - select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_TPM2 - select MAINBOARD_HAS_SPI_TPM_CR50 - -config VBOOT - select EC_GOOGLE_CHROMEEC_SWITCHES - select VBOOT_VBNV_FLASH - -config MAINBOARD_DIR - string - default "google/cheza" - -config DRIVER_TPM_SPI_BUS - hex - default 0x5 - -config EC_GOOGLE_CHROMEEC_SPI_BUS - hex - default 0xa - -########################################################## -#### Update below when adding a new derivative board. #### -########################################################## - -config MAINBOARD_PART_NUMBER - string - default "Cheza" if BOARD_GOOGLE_CHEZA - -endif # BOARD_GOOGLE_CHEZA_COMMON diff --git a/src/mainboard/google/cheza/Kconfig.name b/src/mainboard/google/cheza/Kconfig.name deleted file mode 100644 index fbfe4c9..0000000 --- a/src/mainboard/google/cheza/Kconfig.name +++ /dev/null @@ -1,4 +0,0 @@ - -config BOARD_GOOGLE_CHEZA - bool "Cheza" - select BOARD_GOOGLE_CHEZA_COMMON diff --git a/src/mainboard/google/cheza/Makefile.inc b/src/mainboard/google/cheza/Makefile.inc deleted file mode 100644 index 949d775..0000000 --- a/src/mainboard/google/cheza/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -bootblock-y += boardid.c -bootblock-y += chromeos.c -bootblock-y += bootblock.c -bootblock-y += reset.c - -verstage-y += boardid.c -verstage-y += chromeos.c -verstage-y += reset.c - -romstage-y += boardid.c -romstage-y += chromeos.c -romstage-y += romstage.c -romstage-y += reset.c - -ramstage-y += boardid.c -ramstage-y += chromeos.c -ramstage-y += mainboard.c -ramstage-y += reset.c diff --git a/src/mainboard/google/cheza/board.h b/src/mainboard/google/cheza/board.h deleted file mode 100644 index 0207537..0000000 --- a/src/mainboard/google/cheza/board.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H -#define __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H - -#include <gpio.h> -#include <soc/gpio.h> - -#define GPIO_EC_IN_RW GPIO(11) -#define GPIO_AP_EC_INT GPIO(122) -#define GPIO_AP_SUSPEND GPIO(126) -#define GPIO_WP_STATE GPIO(128) -#define GPIO_H1_AP_INT GPIO(129) - -void setup_chromeos_gpios(void); - -#endif /* ! __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H */ diff --git a/src/mainboard/google/cheza/board_info.txt b/src/mainboard/google/cheza/board_info.txt deleted file mode 100644 index 5e6e3b2..0000000 --- a/src/mainboard/google/cheza/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Vendor name: Google -Board name: Cheza Qualcomm SDM845 reference board -Category: eval -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/google/cheza/boardid.c b/src/mainboard/google/cheza/boardid.c deleted file mode 100644 index 2a36846..0000000 --- a/src/mainboard/google/cheza/boardid.c +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <boardid.h> -#include <gpio.h> - -uint32_t board_id(void) -{ - const gpio_t pins[] = {[2] = GPIO(51), [1] = GPIO(62), [0] = GPIO(38)}; - static uint32_t id = UNDEFINED_STRAPPING_ID; - - if (id == UNDEFINED_STRAPPING_ID) - id = gpio_base2_value(pins, ARRAY_SIZE(pins)); - - return id; -} - -uint32_t ram_code(void) -{ - const gpio_t pins[] = {[1] = GPIO(147), [0] = GPIO(146)}; - static uint32_t id = UNDEFINED_STRAPPING_ID; - - if (id == UNDEFINED_STRAPPING_ID) - id = gpio_base2_value(pins, ARRAY_SIZE(pins)); - - return id; -} - -uint32_t sku_id(void) -{ - const gpio_t pins[] = {[1] = GPIO(113), [0] = GPIO(79)}; - static uint32_t id = UNDEFINED_STRAPPING_ID; - - if (id == UNDEFINED_STRAPPING_ID) - id = gpio_base2_value(pins, ARRAY_SIZE(pins)); - - return id; -} diff --git a/src/mainboard/google/cheza/bootblock.c b/src/mainboard/google/cheza/bootblock.c deleted file mode 100644 index 05e53a6..0000000 --- a/src/mainboard/google/cheza/bootblock.c +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootblock_common.h> -#include "board.h" - -void bootblock_mainboard_init(void) -{ - setup_chromeos_gpios(); -} diff --git a/src/mainboard/google/cheza/chromeos.c b/src/mainboard/google/cheza/chromeos.c deleted file mode 100644 index cb01091..0000000 --- a/src/mainboard/google/cheza/chromeos.c +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <boot/coreboot_tables.h> -#include <bootmode.h> -#include "board.h" - -int get_write_protect_state(void) -{ - return !gpio_get(GPIO_WP_STATE); -} - -void setup_chromeos_gpios(void) -{ - gpio_input_pullup(GPIO_EC_IN_RW); - gpio_input_pullup(GPIO_AP_EC_INT); - gpio_output(GPIO_AP_SUSPEND, 1); - gpio_input(GPIO_WP_STATE); - gpio_input_pullup(GPIO_H1_AP_INT); -} - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = { - {GPIO_EC_IN_RW.addr, ACTIVE_LOW, gpio_get(GPIO_EC_IN_RW), - "EC in RW"}, - {GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT), - "EC interrupt"}, - {GPIO_H1_AP_INT.addr, ACTIVE_LOW, gpio_get(GPIO_H1_AP_INT), - "TPM interrupt"}, - }; - - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} diff --git a/src/mainboard/google/cheza/chromeos.fmd b/src/mainboard/google/cheza/chromeos.fmd deleted file mode 100644 index 23d2d87..0000000 --- a/src/mainboard/google/cheza/chromeos.fmd +++ /dev/null @@ -1,42 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -FLASH@0x0 8M { - WP_RO 4M { - RO_SECTION 0x184000 { - BOOTBLOCK 96K - COREBOOT(CBFS) - #TODO: Move FMAP to 2M or 3M once FSG can be smaller - FMAP@0x180000 0x1000 - GBB 0x2f00 - RO_FRID 0x100 - } - RO_VPD(PRESERVE) 16K - RO_DDR_TRAINING(PRESERVE) 8K - RO_LIMITS_CFG(PRESERVE) 4K - RO_FSG(PRESERVE) - } - - RW_VPD(PRESERVE) 32K - RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K - RW_LIMITS_CFG(PRESERVE) 4K - RW_ELOG(PRESERVE) 4K - RW_SHARED 4K { - SHARED_DATA - } - - RW_SECTION_A 1280K { - VBLOCK_A 8K - FW_MAIN_A(CBFS) - RW_FWID_A 256 - } - - - RW_SECTION_B 1280K { - VBLOCK_B 8K - FW_MAIN_B(CBFS) - RW_FWID_B 256 - } - - RW_LEGACY(CBFS) -} diff --git a/src/mainboard/google/cheza/devicetree.cb b/src/mainboard/google/cheza/devicetree.cb deleted file mode 100644 index 717653b..0000000 --- a/src/mainboard/google/cheza/devicetree.cb +++ /dev/null @@ -1,5 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -chip soc/qualcomm/sdm845 - device cpu_cluster 0 on end -end diff --git a/src/mainboard/google/cheza/mainboard.c b/src/mainboard/google/cheza/mainboard.c deleted file mode 100644 index e2d02de..0000000 --- a/src/mainboard/google/cheza/mainboard.c +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <gpio.h> -#include <soc/usb.h> - -static struct usb_board_data usb1_board_data = { - .pll_bias_control_2 = 0x28, - .imp_ctrl1 = 0x08, - .port_tune1 = 0x20, -}; - -static void setup_usb(void) -{ - /* - * Primary USB is used only for DP functionality on cheza platform. - * Hence Setting up only Secondary USB DWC3 controller. - */ - setup_usb_host1(&usb1_board_data); - - gpio_output(GPIO(120), 1); /* Deassert HUB_RST_L to enable hub. */ -} - -static void mainboard_init(struct device *dev) -{ - setup_usb(); -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = &mainboard_init; -} - -struct chip_operations mainboard_ops = { - .name = CONFIG_MAINBOARD_PART_NUMBER, - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/google/cheza/reset.c b/src/mainboard/google/cheza/reset.c deleted file mode 100644 index 9b5810f..0000000 --- a/src/mainboard/google/cheza/reset.c +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <ec/google/chromeec/ec.h> -#include <reset.h> - -/* Can't do a "real" reset before the PMIC is initialized in QcLib (romstage), - but this works well enough for our purposes. */ -void do_board_reset(void) -{ - google_chromeec_reboot(0, EC_REBOOT_COLD, 0); -} diff --git a/src/mainboard/google/cheza/romstage.c b/src/mainboard/google/cheza/romstage.c deleted file mode 100644 index e4f72a6..0000000 --- a/src/mainboard/google/cheza/romstage.c +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/stages.h> -#include <soc/usb.h> -#include <soc/qclib_common.h> - -static void prepare_usb(void) -{ - /* - * Do DWC3 core and phy reset. Kick these resets - * off early so they get at least 1ms to settle. - */ - reset_usb1(); -} - -void platform_romstage_main(void) -{ - prepare_usb(); - - /* QCLib: DDR init & train */ - qclib_load_and_run(); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/47427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cd2e2cd0ee69d9846472653a942fa074e2b924d Gerrit-Change-Number: 47427 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: libpayload/usb: Fix printf format string mismatches in debug messages
by Caveh Jalali (Code Review) 12 Nov '20

12 Nov '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45024 ) Change subject: libpayload/usb: Fix printf format string mismatches in debug messages ...................................................................... Patch Set 3: question for the reviewers: should we reflow the affected areas to fit within 96 columns to keep buildbot happy? i'm not convinced that aggressively splitting format strings improves this patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/45024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4dc70baefb3cd82fcc915cc2e7f68719cf6870cc Gerrit-Change-Number: 45024 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 12 Nov 2020 00:05:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: libpayload/usb: Fix printf format string mismatches in debug messages
by build bot (Jenkins) (Code Review) 12 Nov '20

12 Nov '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45024 ) Change subject: libpayload/usb: Fix printf format string mismatches in debug messages ...................................................................... Patch Set 3: (10 comments) https://review.coreboot.org/c/coreboot/+/45024/3/payloads/libpayload/driver… File payloads/libpayload/drivers/usb/ehci.c: https://review.coreboot.org/c/coreboot/+/45024/3/payloads/libpayload/driver… PS3, Line 55: usb_debug("|:| Alt. Next qTD [0x%08"PRIx32"] |:|\n", td->alt_next_qtd); line over 96 characters https://review.coreboot.org/c/coreboot/+/45024/3/payloads/libpayload/driver… PS3, Line 57: usb_debug("|:| | Bytes to Transfer |[%05"PRId32"] |:|\n", (td->token & QTD_TOTAL_LEN_MASK) >> 16); line over 96 characters https://review.coreboot.org/c/coreboot/+/45024/3/payloads/libpayload/driver… PS3, Line 282: if (0) usb_debug("\nmoving from %p to %p\n", cur, phys_to_virt(cur->next_qtd)); trailing statements should be on next line https://review.coreboot.org/c/coreboot/+/45024/3/payloads/libpayload/driver… File payloads/libpayload/drivers/usb/ohci.c: https://review.coreboot.org/c/coreboot/+/45024/3/payloads/libpayload/driver… PS3, Line 72: usb_debug("|:| Current Buffer Pointer [0x%08"PRIx32"] |:|\n", cur->current_buffer_pointer); line over 96 characters https://review.coreboot.org/c/coreboot/+/45024/3/payloads/libpayload/driver… PS3, Line 76: usb_debug("|:| Current Buffer End [0x%08"PRIx32"] |:|\n", cur->buffer_end); line over 96 characters https://review.coreboot.org/c/coreboot/+/45024/3/payloads/libpayload/driver… PS3, Line 93: usb_debug("| O | Function Address | [%04"PRIx32"] |\n", cur->config & 0x7F); line over 96 characters https://review.coreboot.org/c/coreboot/+/45024/3/payloads/libpayload/driver… PS3, Line 471: usb_debug("ohci_control(): doing transfer with %x. first_td at %"PRIxPTR"\n", Prefer using '"%s...", __func__' to using 'ohci_control', this function's name, in a string https://review.coreboot.org/c/coreboot/+/45024/3/payloads/libpayload/driver… PS3, Line 509: usb_debug("bulk: %x bytes from %p, finalize: %x, maxpacketsize: %x\n", dalen, src, finalize, ep->maxpacketsize); line over 96 characters https://review.coreboot.org/c/coreboot/+/45024/3/payloads/libpayload/driver… File payloads/libpayload/drivers/usb/uhci.c: https://review.coreboot.org/c/coreboot/+/45024/3/payloads/libpayload/driver… PS3, Line 82: usb_debug("|:| O | PID CODE | [%04"PRIx32"] |:|\n", td->token & 0xFF); line over 96 characters https://review.coreboot.org/c/coreboot/+/45024/3/payloads/libpayload/driver… PS3, Line 83: usb_debug("|:| K | Endpoint | [%04"PRIx32"] |:|\n", (td->token & TD_EP_MASK) >> TD_EP_SHIFT); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/45024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4dc70baefb3cd82fcc915cc2e7f68719cf6870cc Gerrit-Change-Number: 45024 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 11 Nov 2020 23:57:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/zork: Add func fpmcu_needs_delay
by Martin Roth (Code Review) 12 Nov '20

12 Nov '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47369 ) Change subject: mb/google/zork: Add func fpmcu_needs_delay ...................................................................... mb/google/zork: Add func fpmcu_needs_delay This adds a function to tell if boards need an extra delay for the FPMCU's reset logic. BUG=b:171837716 TEST=Boot on early board, see extra delay BRANCH=Zork Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I60eec69aff0715b23fdf8ec695674f708fb37bcc --- M src/mainboard/google/zork/variants/baseboard/helpers.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/variants/berknip/variant.c M src/mainboard/google/zork/variants/morphius/variant.c 4 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/47369/1 diff --git a/src/mainboard/google/zork/variants/baseboard/helpers.c b/src/mainboard/google/zork/variants/baseboard/helpers.c index 624d1b2..2fc2bde 100644 --- a/src/mainboard/google/zork/variants/baseboard/helpers.c +++ b/src/mainboard/google/zork/variants/baseboard/helpers.c @@ -155,5 +155,9 @@ /* Default to no fingerprint sensor */ return 0; } + +__weak int fpmcu_needs_delay(void) +{ + /* Default to no delay */ return 0; } diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 4ba7843..054094a 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -33,6 +33,9 @@ /* Return 1 if the board has a fingerprint sensor. Return 0 otherwise */ int variant_has_fingerprint(void); +/* Return 1 if the board has an FPMCU that needs an extra delay. Return 0 otherwise. */ +int fpmcu_needs_delay(void); + /* Modify devictree settings during ramstage. */ void variant_devtree_update(void); /* Update audio configuration in devicetree during ramstage. */ diff --git a/src/mainboard/google/zork/variants/berknip/variant.c b/src/mainboard/google/zork/variants/berknip/variant.c index aba5527..714063b 100644 --- a/src/mainboard/google/zork/variants/berknip/variant.c +++ b/src/mainboard/google/zork/variants/berknip/variant.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> void variant_devtree_update(void) { @@ -20,3 +21,17 @@ { return 1; } + +int fpmcu_needs_delay(void) +{ + uint32_t board_version; + + if (google_chromeec_cbi_get_board_version(&board_version)) + board_version = 1; + + /* The FPMCU on early boards needs an extra delay */ + if (board_version <= 3) + return 1; + + return 0; +} diff --git a/src/mainboard/google/zork/variants/morphius/variant.c b/src/mainboard/google/zork/variants/morphius/variant.c index 2e7ed8a..bf61396 100644 --- a/src/mainboard/google/zork/variants/morphius/variant.c +++ b/src/mainboard/google/zork/variants/morphius/variant.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> void variant_devtree_update(void) { @@ -20,3 +21,17 @@ /* All Morphius SKUs have a fingerprint sensor */ return 1; } + +int fpmcu_needs_delay(void) +{ + uint32_t board_version; + + if (google_chromeec_cbi_get_board_version(&board_version)) + board_version = 1; + + /* The FPMCU on early boards needs an extra delay */ + if (board_version <= 4) + return 1; + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60eec69aff0715b23fdf8ec695674f708fb37bcc Gerrit-Change-Number: 47369 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: mb/google/zork: Add func to determine fingerprint gpio init
by Martin Roth (Code Review) 12 Nov '20

12 Nov '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47309 ) Change subject: mb/google/zork: Add func to determine fingerprint gpio init ...................................................................... mb/google/zork: Add func to determine fingerprint gpio init Because fingerprint sensor isn't a CBI field, it needs to be determined by board and SKU. Berknip is the only board that some SKUs have a fingerprint sensor and others don't. BUG=b:171837716 TEST=Verify that morphius fingerprint sensor works and Berknip SKU_0 does not show fingerprint as an option. BRANCH=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Ia5200e3bcfe3a2beac9b3b6d7803aeac9dfc59e6 --- M src/mainboard/google/zork/variants/baseboard/helpers.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/variants/berknip/Makefile.inc M src/mainboard/google/zork/variants/berknip/variant.c M src/mainboard/google/zork/variants/morphius/Makefile.inc M src/mainboard/google/zork/variants/morphius/variant.c 6 files changed, 54 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/47309/1 diff --git a/src/mainboard/google/zork/variants/baseboard/helpers.c b/src/mainboard/google/zork/variants/baseboard/helpers.c index 7071035..4ef222c 100644 --- a/src/mainboard/google/zork/variants/baseboard/helpers.c +++ b/src/mainboard/google/zork/variants/baseboard/helpers.c @@ -149,3 +149,11 @@ { return extract_field(FW_CONFIG_MASK_DB_INDEX, FW_CONFIG_DB_INDEX_SHIFT); } + +__weak int variant_init_fingerprint(void) +{ + /* Default to no fingerprint sensor */ + printk(BIOS_DEBUG, "Default gpio_init_fingerprint to disabled.\n"); + + return 0; +} diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 5c040d3..61c8b3c 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -36,6 +36,9 @@ */ const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ); +/* Determine whether to init fingerprint sensor or not */ +int variant_init_fingerprint(void); + /* Modify devictree settings during ramstage. */ void variant_devtree_update(void); /* Update audio configuration in devicetree during ramstage. */ diff --git a/src/mainboard/google/zork/variants/berknip/Makefile.inc b/src/mainboard/google/zork/variants/berknip/Makefile.inc index 51d19fe..a478eb3 100644 --- a/src/mainboard/google/zork/variants/berknip/Makefile.inc +++ b/src/mainboard/google/zork/variants/berknip/Makefile.inc @@ -4,3 +4,6 @@ ramstage-y += gpio.c ramstage-y += variant.c + +bootblock-y += gpio.c +bootblock-y += variant.c diff --git a/src/mainboard/google/zork/variants/berknip/variant.c b/src/mainboard/google/zork/variants/berknip/variant.c index 092ff26..ec31cbc 100644 --- a/src/mainboard/google/zork/variants/berknip/variant.c +++ b/src/mainboard/google/zork/variants/berknip/variant.c @@ -1,16 +1,33 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> void variant_devtree_update(void) { struct soc_amd_picasso_config *cfg; - cfg = config_of_soc(); + if (ENV_RAMSTAGE) { + cfg = (struct soc_amd_picasso_config *)config_of_soc(); - /* - * Enable eMMC if eMMC bit is set in FW_CONFIG or device is unprovisioned. - */ - if (!(variant_has_emmc() || boot_is_factory_unprovisioned())) - cfg->emmc_config.timing = SD_EMMC_DISABLE; + /* + * Enable eMMC if eMMC bit is set in FW_CONFIG or device is unprovisioned. + */ + if (!(variant_has_emmc() || boot_is_factory_unprovisioned())) + cfg->emmc_config.timing = SD_EMMC_DISABLE; + } +} + +#define BERKNIP_SKU0_ID 0x5A030020 + +/* Identify which SKUs have fingerprint */ +int variant_init_fingerprint(void) +{ + uint32_t sku; + if (google_chromeec_cbi_get_sku_id(&sku) == 0) { + if (sku == BERKNIP_SKU0_ID) + return 0; + } + + return 1; } diff --git a/src/mainboard/google/zork/variants/morphius/Makefile.inc b/src/mainboard/google/zork/variants/morphius/Makefile.inc index 51d19fe..a478eb3 100644 --- a/src/mainboard/google/zork/variants/morphius/Makefile.inc +++ b/src/mainboard/google/zork/variants/morphius/Makefile.inc @@ -4,3 +4,6 @@ ramstage-y += gpio.c ramstage-y += variant.c + +bootblock-y += gpio.c +bootblock-y += variant.c diff --git a/src/mainboard/google/zork/variants/morphius/variant.c b/src/mainboard/google/zork/variants/morphius/variant.c index 092ff26..ab2adba 100644 --- a/src/mainboard/google/zork/variants/morphius/variant.c +++ b/src/mainboard/google/zork/variants/morphius/variant.c @@ -6,11 +6,19 @@ { struct soc_amd_picasso_config *cfg; - cfg = config_of_soc(); + if (ENV_RAMSTAGE) { + cfg = (struct soc_amd_picasso_config *)config_of_soc(); - /* - * Enable eMMC if eMMC bit is set in FW_CONFIG or device is unprovisioned. - */ - if (!(variant_has_emmc() || boot_is_factory_unprovisioned())) - cfg->emmc_config.timing = SD_EMMC_DISABLE; + /* + * Enable eMMC if eMMC bit is set in FW_CONFIG or device is unprovisioned. + */ + if (!(variant_has_emmc() || boot_is_factory_unprovisioned())) + cfg->emmc_config.timing = SD_EMMC_DISABLE; + } +} + +int variant_init_fingerprint(void) +{ + /* All Morphius SKUs have a fingerprint sensor */ + return 1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/47309 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5200e3bcfe3a2beac9b3b6d7803aeac9dfc59e6 Gerrit-Change-Number: 47309 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 16

Change in coreboot[master]: soc/intel/denverton_ns: Generate ACPI DMAR Table
by Angel Pons (Code Review) 11 Nov '20

11 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25446 ) Change subject: soc/intel/denverton_ns: Generate ACPI DMAR Table ...................................................................... Patch Set 23: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/25446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I263b03b96280599266d4c5e193583ecdfe9697b7 Gerrit-Change-Number: 25446 Gerrit-PatchSet: 23 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Comment-Date: Wed, 11 Nov 2020 22:58:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2020