coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/denverton_ns: Generate ACPI DMAR Table
by Julien Viard de Galbert (Code Review) 11 Nov '20

11 Nov '20

Hello build bot (Jenkins), David Guckian, Patrick Georgi, Paul Menzel, Vanessa Eusebio, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/25446 to look at the new patch set (#23). Change subject: soc/intel/denverton_ns: Generate ACPI DMAR Table ...................................................................... soc/intel/denverton_ns: Generate ACPI DMAR Table - Write ACPI DMAR Table if VT-d is enabled. - The entries are defined to follow FSP settings. Change-Id: I263b03b96280599266d4c5e193583ecdfe9697b7 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/include/soc/acpi.h M src/soc/intel/denverton_ns/include/soc/iomap.h M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/denverton_ns/include/soc/systemagent.h M src/soc/intel/denverton_ns/systemagent.c 6 files changed, 78 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/25446/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/25446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I263b03b96280599266d4c5e193583ecdfe9697b7 Gerrit-Change-Number: 25446 Gerrit-PatchSet: 23 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/denverton_ns: Generate ACPI DMAR Table
by Julien Viard de Galbert (Code Review) 11 Nov '20

11 Nov '20

Julien Viard de Galbert has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25446 ) Change subject: soc/intel/denverton_ns: Generate ACPI DMAR Table ...................................................................... Patch Set 22: (5 comments) Wow by the time I got there most of the code was already fixed, thanks community! https://review.coreboot.org/c/coreboot/+/25446/4/src/soc/intel/denverton_ns… File src/soc/intel/denverton_ns/acpi.c: https://review.coreboot.org/c/coreboot/+/25446/4/src/soc/intel/denverton_ns… PS4, Line 367: /* reusing drdh functions for rmrr. : * Should be Device Scope? : * IE remove _drhd */ > If you make the suggested changes I put in the other patch, then you can change this to call acpi_cr […] The suggestion has been implemented already by now... thanks! https://review.coreboot.org/c/coreboot/+/25446/18/src/soc/intel/denverton_n… File src/soc/intel/denverton_ns/acpi.c: https://review.coreboot.org/c/coreboot/+/25446/18/src/soc/intel/denverton_n… PS18, Line 339: MCH_VTBAR_MASK; > nit: this would fit in 96 chars Done https://review.coreboot.org/c/coreboot/+/25446/18/src/soc/intel/denverton_n… PS18, Line 354: fsp > FSP Done https://review.coreboot.org/c/coreboot/+/25446/18/src/soc/intel/denverton_n… PS18, Line 359: drdh > DRHD Ack https://review.coreboot.org/c/coreboot/+/25446/4/src/soc/intel/denverton_ns… File src/soc/intel/denverton_ns/include/soc/systemagent.h: https://review.coreboot.org/c/coreboot/+/25446/4/src/soc/intel/denverton_ns… PS4, Line 80: 0xfffff000 > I mean 0x7ffffff000... […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/25446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I263b03b96280599266d4c5e193583ecdfe9697b7 Gerrit-Change-Number: 25446 Gerrit-PatchSet: 22 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Comment-Date: Wed, 11 Nov 2020 22:54:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jay Talbott <JayTalbott(a)sysproconsulting.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: Generate ACPI DMAR Table
by build bot (Jenkins) (Code Review) 11 Nov '20

11 Nov '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25446 ) Change subject: soc/intel/denverton_ns: Generate ACPI DMAR Table ...................................................................... Patch Set 22: (1 comment) https://review.coreboot.org/c/coreboot/+/25446/22/src/soc/intel/denverton_n… File src/soc/intel/denverton_ns/acpi.c: https://review.coreboot.org/c/coreboot/+/25446/22/src/soc/intel/denverton_n… PS22, Line 279: printk(BIOS_DEBUG, "DEFVTBAR:0x%Lx\n", vtbar); %Lx is non-standard C, use %llx -- To view, visit https://review.coreboot.org/c/coreboot/+/25446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I263b03b96280599266d4c5e193583ecdfe9697b7 Gerrit-Change-Number: 25446 Gerrit-PatchSet: 22 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Comment-Date: Wed, 11 Nov 2020 22:52:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: Generate ACPI DMAR Table
by Julien Viard de Galbert (Code Review) 11 Nov '20

11 Nov '20

Hello build bot (Jenkins), David Guckian, Patrick Georgi, Paul Menzel, Vanessa Eusebio, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/25446 to look at the new patch set (#22). Change subject: soc/intel/denverton_ns: Generate ACPI DMAR Table ...................................................................... soc/intel/denverton_ns: Generate ACPI DMAR Table - Write ACPI DMAR Table if VT-d is enabled. - The entries are defined to follow FSP settings. Change-Id: I263b03b96280599266d4c5e193583ecdfe9697b7 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/include/soc/acpi.h M src/soc/intel/denverton_ns/include/soc/iomap.h M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/denverton_ns/include/soc/systemagent.h M src/soc/intel/denverton_ns/systemagent.c 6 files changed, 78 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/25446/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/25446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I263b03b96280599266d4c5e193583ecdfe9697b7 Gerrit-Change-Number: 25446 Gerrit-PatchSet: 22 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/denverton_ns: Initialize thermal configuration
by Angel Pons (Code Review) 11 Nov '20

11 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25439 ) Change subject: soc/intel/denverton_ns: Initialize thermal configuration ...................................................................... Patch Set 21: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/25439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e1b924154256f8f82ded3d0fa155b3e836d9375 Gerrit-Change-Number: 25439 Gerrit-PatchSet: 21 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Steve Mooney Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Comment-Date: Wed, 11 Nov 2020 22:48:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: Initialize thermal configuration
by Julien Viard de Galbert (Code Review) 11 Nov '20

11 Nov '20

Julien Viard de Galbert has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25439 ) Change subject: soc/intel/denverton_ns: Initialize thermal configuration ...................................................................... Patch Set 21: (4 comments) As suggested by Jay Talbott, denverton has the feature always available, no need to check the cpuid(1) result, this simplifies the code ;) https://review.coreboot.org/c/coreboot/+/25439/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/25439/4//COMMIT_MSG@8 PS4, Line 8: > Add few lines info/detail on, why this code change required and what kind of problem we are solving […] When I started this, the denverton port was just the code drop by Intel to test FSP, it's missing a lot of initialization. So it's not fixing a problem it's just enabling features of the SoC. https://review.coreboot.org/c/coreboot/+/25439/3/src/soc/intel/denverton_ns… File src/soc/intel/denverton_ns/cpu.c: https://review.coreboot.org/c/coreboot/+/25439/3/src/soc/intel/denverton_ns… PS3, Line 81: msr.lo = 0; : msr.hi = 0; > Already set above, right? yes thanks https://review.coreboot.org/c/coreboot/+/25439/4/src/soc/intel/denverton_ns… File src/soc/intel/denverton_ns/cpu.c: https://review.coreboot.org/c/coreboot/+/25439/4/src/soc/intel/denverton_ns… PS4, Line 84: (1 << 29) > Is there a macro for this bit? […] Right the feature bit should always be set ... I don't remember where I found the general algorithm either other soc code or generic intel doc ... I simplified the code and added macros. https://review.coreboot.org/c/coreboot/+/25439/13/src/soc/intel/denverton_n… File src/soc/intel/denverton_ns/cpu.c: https://review.coreboot.org/c/coreboot/+/25439/13/src/soc/intel/denverton_n… PS13, Line 82: msr.lo &= (1 << 3); /* Clear TM enable */ > Ping Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/25439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e1b924154256f8f82ded3d0fa155b3e836d9375 Gerrit-Change-Number: 25439 Gerrit-PatchSet: 21 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Steve Mooney Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Comment-Date: Wed, 11 Nov 2020 22:16:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Steve Mooney Comment-In-Reply-To: Jay Talbott <JayTalbott(a)sysproconsulting.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes
by Julien Viard de Galbert (Code Review) 11 Nov '20

11 Nov '20

Julien Viard de Galbert has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25436 ) Change subject: mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes ...................................................................... Patch Set 20: (1 comment) Updated, thanks to new commit hook and rules ! https://review.coreboot.org/c/coreboot/+/25436/18/src/mainboard/scaleway/ta… File src/mainboard/scaleway/tagada/hsio.c: https://review.coreboot.org/c/coreboot/+/25436/18/src/mainboard/scaleway/ta… PS18, Line 23: BL_HSIO_INFORMATION *config) > Many of these fit in one line I think clang-format in the commit hook fixed it for me ;) -- To view, visit https://review.coreboot.org/c/coreboot/+/25436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3ed97fc2b54d4974ec0b41b9f207fe3d49d2cce Gerrit-Change-Number: 25436 Gerrit-PatchSet: 20 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 11 Nov 2020 22:14:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: Enable MC Exception
by Julien Viard de Galbert (Code Review) 11 Nov '20

11 Nov '20

Julien Viard de Galbert has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25434 ) Change subject: soc/intel/denverton_ns: Enable MC Exception ...................................................................... Patch Set 19: (2 comments) This one should be okay now. https://review.coreboot.org/c/coreboot/+/25434/3/src/soc/intel/denverton_ns… File src/soc/intel/denverton_ns/cpu.c: https://review.coreboot.org/c/coreboot/+/25434/3/src/soc/intel/denverton_ns… PS3, Line 63: /* TODO install a fallback MC handler for each core in case OS does : not provide one. Is it really needed ? */ > What would the fallback MC handler do if an MC occurred? No idea, to be honest I remember reading this in the BiosWriterGuide I no longer have access to... https://review.coreboot.org/c/coreboot/+/25434/12/src/soc/intel/denverton_n… File src/soc/intel/denverton_ns/cpu.c: https://review.coreboot.org/c/coreboot/+/25434/12/src/soc/intel/denverton_n… PS12, Line 65: needed ? > Ping Removed the space. -- To view, visit https://review.coreboot.org/c/coreboot/+/25434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9773c61d06bb6c68612e498a35b5ad22cd5a8a6e Gerrit-Change-Number: 25434 Gerrit-PatchSet: 19 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <d.guckian20(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Comment-Date: Wed, 11 Nov 2020 22:13:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jay Talbott <JayTalbott(a)sysproconsulting.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: Enable MC Exception
by Julien Viard de Galbert (Code Review) 11 Nov '20

11 Nov '20

Hello Felix Singer, build bot (Jenkins), Patrick Georgi, David Guckian, Paul Menzel, Vanessa Eusebio, Angel Pons, Mimoja, Patrick Rudolph, David Guckian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/25434 to look at the new patch set (#19). Change subject: soc/intel/denverton_ns: Enable MC Exception ...................................................................... soc/intel/denverton_ns: Enable MC Exception Change-Id: I9773c61d06bb6c68612e498a35b5ad22cd5a8a6e Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/denverton_ns/cpu.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/25434/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/25434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9773c61d06bb6c68612e498a35b5ad22cd5a8a6e Gerrit-Change-Number: 25434 Gerrit-PatchSet: 19 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <d.guckian20(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes
by Julien Viard de Galbert (Code Review) 11 Nov '20

11 Nov '20

Hello build bot (Jenkins), Patrick Georgi, Paul Menzel, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/25436 to look at the new patch set (#21). Change subject: mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes ...................................................................... mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes Change-Id: Ic3ed97fc2b54d4974ec0b41b9f207fe3d49d2cce Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- A src/mainboard/scaleway/tagada/gpio_defs.h M src/mainboard/scaleway/tagada/hsio.c M src/mainboard/scaleway/tagada/hsio.h 3 files changed, 89 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/25436/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/25436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3ed97fc2b54d4974ec0b41b9f207fe3d49d2cce Gerrit-Change-Number: 25436 Gerrit-PatchSet: 21 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2020