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Change in coreboot[master]: util/inteltool: add missing special function pads for CNL-LP
by Michael Niewöhner (Code Review)
11 Nov '20
11 Nov '20
Michael Niewöhner has submitted this change. (
https://review.coreboot.org/c/coreboot/+/45201
) Change subject: util/inteltool: add missing special function pads for CNL-LP ...................................................................... util/inteltool: add missing special function pads for CNL-LP Add the missing special function gpio pad groups for CNL-LP. The groups and names are documented in the PCH EDS, in Linux (linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places. Also, see soc/intel/tigerlake for reference. Change-Id: I0509552da6ffad395c2b89df1676e1903c783695 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on:
https://review.coreboot.org/c/coreboot/+/45201
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M util/inteltool/gpio_names/cannonlake_lp.h 1 file changed, 166 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved diff --git a/util/inteltool/gpio_names/cannonlake_lp.h b/util/inteltool/gpio_names/cannonlake_lp.h index 27d820c..af14c1f 100644 --- a/util/inteltool/gpio_names/cannonlake_lp.h +++ b/util/inteltool/gpio_names/cannonlake_lp.h @@ -276,7 +276,12 @@ "GPD9", "SLP_WLAN#", "GPD10", "SLP_S5#", "GPD11", "LANPHYPC", + "SLP_LAN_B", "SLP_LAN#", + "SLP_SUS_B", "SLP_SUS#", + "WAKE_B", "WAKE#", + "DRAM_RESET_B", "DRAM_RESET#", }; + const struct gpio_group cannonlake_pch_lp_group_gpd = { .display = "------- GPIO Group GPD -------", .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_gpd_names) / 2, @@ -284,11 +289,156 @@ .pad_names = cannonlake_pch_lp_group_gpd_names, }; +const char *const cannonlake_pch_lp_group_vgpio_names[] = { + "CNV_BTEN", "n/a", "n/a", "n/a", + "CNV_GNEN", "n/a", "n/a", "n/a", + "CNV_WFEN", "n/a", "n/a", "n/a", + "CNV_WCEN", "n/a", "n/a", "n/a", + "CNV_BT_HOST_WAKE_B", "n/a", "n/a", "n/a", + "CNV_BT_IF_SELECT", "n/a", "n/a", "n/a", + "vCNV_BT_UART_TXD", "ISH UART0", "SIo UART2", "n/a", + "vCNV_BT_UART_RXD", "ISH UART0", "SIo UART2", "n/a", + "vCNV_BT_UART_CTS_B", "ISH UART0", "SIo UART2", "n/a", + "vCNV_BT_UART_RTS_B", "ISH UART0", "SIo UART2", "n/a", + "vCNV_MFUART1_TXD", "ISH UART0", "SIo UART2", "n/a", + "vCNV_MFUART1_RXD", "ISH UART0", "SIo UART2", "n/a", + "vCNV_MFUART1_CTS_B", "ISH UART0", "SIo UART2", "n/a", + "vCNV_MFUART1_RTS_B", "ISH UART0", "SIo UART2", "n/a", + "vCNV_GNSS_UART_TXD", "n/a", "n/a", "n/a", + "vCNV_GNSS_UART_RXD", "n/a", "n/a", "n/a", + "vCNV_GNSS_UART_CTS_B", "n/a", "n/a", "n/a", + "vCNV_GNSS_UART_RTS_B", "n/a", "n/a", "n/a", + "vUART0_TXD", "mapped", "n/a", "n/a", + "vUART0_RXD", "mapped", "n/a", "n/a", + "vUART0_CTS_B", "mapped", "n/a", "n/a", + "vUART0_RTS_B", "mapped", "n/a", "n/a", + "vISH_UART0_TXD", "mapped", "n/a", "n/a", + "vISH_UART0_RXD", "mapped", "n/a", "n/a", + "vISH_UART0_CTS_B", "mapped", "n/a", "n/a", + "vISH_UART0_RTS_B", "mapped", "n/a", "n/a", + "vISH_UART1_TXD", "mapped", "n/a", "n/a", + "vISH_UART1_RXD", "mapped", "n/a", "n/a", + "vISH_UART1_CTS_B", "mapped", "n/a", "n/a", + "vISH_UART1_RTS_B", "mapped", "n/a", "n/a", + "vCNV_BT_I2S_BCLK", "SSP0", "SSP1", "SSP2", + "vCNV_BT_I2S_WS_SYNC", "SSP0", "SSP1", "SSP2", + "vCNV_BT_I2S_SDO", "SSP0", "SSP1", "SSP2", + "vCNV_BT_I2S_SDI", "SSP0", "SSP1", "SSP2", + "vSSP2_SCLK", "mapped", "n/a", "n/a", + "vSSP2_SFRM", "mapped", "n/a", "n/a", + "vSSP2_TXD", "mapped", "n/a", "n/a", + "vSSP2_RXD", "n/a", "n/a", "n/a", + "vCNV_GNSS_HOST_WAKE_B", "n/a", "n/a", "n/a", + "vSD3_CD_B", "n/a", "n/a", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_vgpio = { + .display = "------- GPIO Group VGPIO -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_vgpio_names) / 4, + .func_count = 4, + .pad_names = cannonlake_pch_lp_group_vgpio_names, +}; + +const char *const cannonlake_pch_lp_group_spi_names[] = { + "SPI0_IO_2", "SPI0_IO_2", + "SPI0_IO_3", "SPI0_IO_3", + "SPI0_MISO", "SPI0_MISO", + "SPI0_MOSI", "SPI0_MOSI", + "SPI0_CS2_B", "SPI0_CS2#", + "SPI0_CS0_B", "SPI0_CS0#", + "SPI0_CS1_B", "SPI0_CS1#", + "SPI0_CLK", "SPI0_CLK", + "SPI0_CLK_LOOPBK", "SPI0_CLK_LOOPBK", +}; + +const struct gpio_group cannonlake_pch_lp_group_spi = { + .display = "------- GPIO Group SPI -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_spi_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_lp_group_spi_names, +}; + +const char *const cannonlake_pch_lp_group_aza_names[] = { + "HDA_BCLK", "HDA_BCLK", "I2S0_SCLK", "n/a", + "HDA_RST_B", "HDA_RST#", "I2S1_SCLK", "SNDW1_CLK", + "HDA_SYNC", "HDA_SYNC", "I2S0_SFRM", "n/a", + "HDA_SDO", "HDA_SDO", "I2S0_TXD", "n/a", + "HDA_SDI0", "HDA_SDI0", "I2S0_RXD", "n/a", + "HDA_SDI1", "HDA_SDI1", "I2S1_RXD", "SNDW1_DATA", + "I2S1_SFRM", "I2S1_SFRM", "SNDW2_CLK", "n/a", + "I2S1_TXD", "I2S1_TXD", "SNDW2_DATA", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_aza = { + .display = "------- GPIO Group AZA -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_aza_names) / 4, + .func_count = 4, + .pad_names = cannonlake_pch_lp_group_aza_names, +}; + +const char *const cannonlake_pch_lp_group_cpu_names[] = { + "HDACPU_SDI", "HDACPU_SDI", + "HDACPU_SDO", "HDACPU_SDO", + "HDACPU_SCLK", "HDACPU_SCLK", + "PM_SYNC", "PM_SYNC", + "PECI", "PECI", + "CPUPWRGD", "CPUPWRGD", + "THRMTRIP_B", "THRMTRIP#", + "PLTRST_CPU_B", "PLTRST_CPU#", + "PM_DOWN", "PM_DOWN", + "TRIGGER_IN", "TRIGGER_IN", + "TRIGGER_OUT", "TRIGGER_OUT", +}; + +const struct gpio_group cannonlake_pch_lp_group_cpu = { + .display = "------- GPIO Group CPU -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_cpu_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_lp_group_cpu_names, +}; + +const char *const cannonlake_pch_lp_group_jtag_names[] = { + "PCH_TDO", "PCH_TDO", + "PCH_JTAGX", "PCH_JTAGX", + "PROC_PRDY_B", "PROC_PRDY#", + "PROC_PREQ_B", "PROC_PREQ#", + "CPU_TRST_B", "CPU_TRST#", + "PCH_TDI", "PCH_TDI", + "PCH_TMS", "PCH_TMS", + "PCH_TCK", "PCH_TCK", + "ITP_PMODE", "ITP_PMODE", +}; + +const struct gpio_group cannonlake_pch_lp_group_jtag = { + .display = "------- GPIO Group JTAG -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_jtag_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_lp_group_jtag_names, +}; + +const char *const cannonlake_pch_lp_group_hvmos_names[] = { + "EDP_VDDEN", "EDP_VDDEN", + "EDP_BKLTEN", "EDP_BKLTEN", + "EDP_BKLTCTL", "EDP_BKLTCTL", + "SYS_PWROK", "SYS_PWROK", + "SYS_RESET_B", "SYS_RESET#", + "CL_RST_B", "CL_RST#", +}; + +const struct gpio_group cannonlake_pch_lp_group_hvmos = { + .display = "------- GPIO Group HVMOS -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_hvmos_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_lp_group_hvmos_names, +}; + const struct gpio_group *const cannonlake_pch_lp_community_0_groups[] = { &cannonlake_pch_lp_group_a, &cannonlake_pch_lp_group_b, &cannonlake_pch_lp_group_g, + &cannonlake_pch_lp_group_spi, }; + const struct gpio_community cannonlake_pch_lp_community_0 = { .name = "------- GPIO Community 0 -------", .pcr_port_id = 0x6e, @@ -300,6 +450,7 @@ &cannonlake_pch_lp_group_d, &cannonlake_pch_lp_group_f, &cannonlake_pch_lp_group_h, + &cannonlake_pch_lp_group_vgpio, }; const struct gpio_community cannonlake_pch_lp_community_1 = { .name = "------- GPIO Community 1 -------", @@ -319,9 +470,23 @@ .groups = cannonlake_pch_lp_community_2_groups, }; +const struct gpio_group *const cannonlake_pch_lp_community_3_groups[] = { + &cannonlake_pch_lp_group_aza, + &cannonlake_pch_lp_group_cpu, +}; + +const struct gpio_community cannonlake_pch_lp_community_3 = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0x6b, + .group_count = ARRAY_SIZE(cannonlake_pch_lp_community_3_groups), + .groups = cannonlake_pch_lp_community_3_groups, +}; + const struct gpio_group *const cannonlake_pch_lp_community_4_groups[] = { &cannonlake_pch_lp_group_c, &cannonlake_pch_lp_group_e, + &cannonlake_pch_lp_group_jtag, + &cannonlake_pch_lp_group_hvmos, }; const struct gpio_community cannonlake_pch_lp_community_4 = { @@ -335,6 +500,7 @@ &cannonlake_pch_lp_community_0, &cannonlake_pch_lp_community_1, &cannonlake_pch_lp_community_2, + &cannonlake_pch_lp_community_3, &cannonlake_pch_lp_community_4, }; -- To view, visit
https://review.coreboot.org/c/coreboot/+/45201
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0509552da6ffad395c2b89df1676e1903c783695 Gerrit-Change-Number: 45201 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged
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Change in coreboot[master]: util/inteltool: add missing special function pads for CNL-LP
by Michael Niewöhner (Code Review)
11 Nov '20
11 Nov '20
Michael Niewöhner has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/45201
) Change subject: util/inteltool: add missing special function pads for CNL-LP ...................................................................... Patch Set 8: (1 comment)
https://review.coreboot.org/c/coreboot/+/45201/2/util/inteltool/gpio_names/…
File util/inteltool/gpio_names/cannonlake_lp.h:
https://review.coreboot.org/c/coreboot/+/45201/2/util/inteltool/gpio_names/…
PS2, Line 311: "vUART0_TXD", "mapped", "n/a", "n/a", : "vUART0_RXD", "mapped", "n/a", "n/a", : "vUART0_CTS_B", "mapped", "n/a", "n/a", : "vUART0_RTS_B", "mapped", "n/a", "n/a", : "vISH_UART0_TXD", "mapped", "n/a", "n/a", : "vISH_UART0_RXD", "mapped", "n/a", "n/a", : "vISH_UART0_CTS_B", "mapped", "n/a", "n/a", : "vISH_UART0_RTS_B", "mapped", "n/a", "n/a", : "vISH_UART1_TXD", "mapped", "n/a", "n/a", : "vISH_UART1_RXD", "mapped", "n/a", "n/a", : "vISH_UART1_CTS_B", "mapped", "n/a", "n/a", : "vISH_UART1_RTS_B", "mapped", "n/a", "n/a", : "vCNV_BT_I2S_BCLK", "SSP0", "SSP1", "SSP2", : "vCNV_BT_I2S_WS_SYNC", "SSP0", "SSP1", "SSP2", : "vCNV_BT_I2S_SDO", "SSP0", "SSP1", "SSP2", : "vCNV_BT_I2S_SDI", "SSP0", "SSP1", "SSP2", : "vSSP2_SCLK", "mapped", "n/a", "n/a", : "vSSP2_SFRM", "mapped", "n/a", "n/a", : "vSSP2_TXD", "mapped", "n/a", "n/a", : "vSSP2_RXD", "n/a", "n/a", "n/a", : "vCNV_GNSS_HOST_WAKEB", "n/a", "n/a", "n/a", : "vSD3_CD_B", "n/a", "n/a", "n/a", > this needs further investigation; it seems, they use vGPIOs as mux switches o. […] will be done in a follow-up later. for dumping the register values it's not that important for now -- To view, visit
https://review.coreboot.org/c/coreboot/+/45201
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0509552da6ffad395c2b89df1676e1903c783695 Gerrit-Change-Number: 45201 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 11 Nov 2020 12:32:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment
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Change in coreboot[master]: util/inteltool: add missing special function pads for CNL-H
by Michael Niewöhner (Code Review)
11 Nov '20
11 Nov '20
Michael Niewöhner has submitted this change. (
https://review.coreboot.org/c/coreboot/+/45204
) Change subject: util/inteltool: add missing special function pads for CNL-H ...................................................................... util/inteltool: add missing special function pads for CNL-H Add the missing special function gpio pad groups for CNL-H. The groups and names are documented in the PCH EDS, in Linux (linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places. Also, see soc/intel/tigerlake for reference. Change-Id: Ib83aeef9f4b6aa174e61ccbd87fb7b6450ed773b Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on:
https://review.coreboot.org/c/coreboot/+/45204
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M util/inteltool/gpio_names/cannonlake.h 1 file changed, 46 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved diff --git a/util/inteltool/gpio_names/cannonlake.h b/util/inteltool/gpio_names/cannonlake.h index 47672d5..694b158 100644 --- a/util/inteltool/gpio_names/cannonlake.h +++ b/util/inteltool/gpio_names/cannonlake.h @@ -264,6 +264,32 @@ "GPP_H23", "TIME_SYNC0", }; +const char *const cannonlake_pch_h_group_cpu_names[] = { + "HDACPU_SDI", "HDACPU_SDI", + "HDACPU_SDO", "HDACPU_SDO", + "HDACPU_SCLK", "HDACPU_SCLK", + "PM_SYNC", "PM_SYNC", + "PECI", "PECI", + "CPUPWRGD", "CPUPWRG#", + "THRMTRIP_B", "THRMTRIP#", + "PLTRST_CPU_B", "PLTRST_CPU#", + "PM_DOWN", "PM_DOWN", + "TRIGGER_IN", "TRIGGER_IN", + "TRIGGER_OUT", "TRIGGER_OUT", +}; + +const char *const cannonlake_pch_h_group_jtag_names[] = { + "PCH_TDO", "PCH_TDO", + "PCH_JTAGX", "PCH_JTAGX", + "PROC_PRDY_B", "PROC_RDY#", + "PROC_PREQ_B", "PROC_REQ#", + "CPU_TRST_B", "CPU_TRST#", + "PCH_TDI", "PCH_TDI", + "PCH_TMS", "PCH_TMS", + "PCH_TCK", "PCH_TCK", + "ITP_PMODE", "ITP_PMODE", +}; + static const char *const cannonlake_pch_h_group_i_names[] = { "GPP_I0", "DDPB_HPD0", "DISP_MISC0", "GPP_I1", "DDPB_HPD1", "DISP_MISC1", @@ -340,6 +366,10 @@ "GPD9", "SLP_WLAN#", "GPD10", "SLP_S5#", "GPD11", "LANPHYPC", + "SLP_LAN_B", "SLP_LAN#", + "SLP_SUS_B", "SLP_SUS#", + "WAKE_B", "WAKE#", + "DRAM_RESET_B", "DRAM_RESET#", }; static const struct gpio_group cannonlake_pch_h_group_a = { @@ -426,6 +456,20 @@ .pad_names = cannonlake_pch_h_group_h_names, }; +static const struct gpio_group cannonlake_pch_h_group_cpu = { + .display = "------- GPIO Group CPU -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_cpu_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_h_group_cpu_names, +}; + +static const struct gpio_group cannonlake_pch_h_group_jtag = { + .display = "------- GPIO Group JTAG -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_jtag_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_h_group_jtag_names, +}; + static const struct gpio_group cannonlake_pch_h_group_i = { .display = "------- GPIO Group GPP_I -------", .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_i_names) / 3, @@ -505,6 +549,8 @@ }; static const struct gpio_group *const cannonlake_pch_h_community_4_groups[] = { + &cannonlake_pch_h_group_cpu, + &cannonlake_pch_h_group_jtag, &cannonlake_pch_h_group_i, &cannonlake_pch_h_group_j, }; -- To view, visit
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib83aeef9f4b6aa174e61ccbd87fb7b6450ed773b Gerrit-Change-Number: 45204 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged
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Change in coreboot[master]: util/inteltool: add missing native functions of special pads for CNL-H
by Michael Niewöhner (Code Review)
11 Nov '20
11 Nov '20
Michael Niewöhner has submitted this change. (
https://review.coreboot.org/c/coreboot/+/45203
) Change subject: util/inteltool: add missing native functions of special pads for CNL-H ...................................................................... util/inteltool: add missing native functions of special pads for CNL-H Add the missing native functions for special gpio pads for CNL-H, which are documented in the PCH EDS and other places. Also, see soc/intel/tigerlake for reference. Change-Id: I71339d66362d29806c91375c214e9fb84c989201 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on:
https://review.coreboot.org/c/coreboot/+/45203
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M util/inteltool/gpio_names/cannonlake.h 1 file changed, 68 insertions(+), 68 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved diff --git a/util/inteltool/gpio_names/cannonlake.h b/util/inteltool/gpio_names/cannonlake.h index 0743936..47672d5 100644 --- a/util/inteltool/gpio_names/cannonlake.h +++ b/util/inteltool/gpio_names/cannonlake.h @@ -158,15 +158,15 @@ }; static const char *const cannonlake_pch_h_group_spi_names[] = { - "SPI0_IO_2", - "SPI0_IO_3", - "SPI0_MISO", - "SPI0_MOSI", - "SPI0_CS2_B", - "SPI0_CS0_B", - "SPI0_CS1_B", - "SPI0_CLK", - "SPI0_CLK_LOOPBK", + "SPI0_IO_2", "SPI0_IO_2", + "SPI0_IO_3", "SPI0_IO_3", + "SPI0_MISO", "SPI0_MISO", + "SPI0_MOSI", "SPI0_MOSI", + "SPI0_CS2_B", "SPI0_CS2#", + "SPI0_CS0_B", "SPI0_CS0#", + "SPI0_CS1_B", "SPI0_CS1#", + "SPI0_CLK", "SPI0_CLK", + "SPI0_CLK_LOOPBK", "SPI0_CLK_LOOPBK", }; static const char *const cannonlake_pch_h_group_g_names[] = { @@ -181,60 +181,60 @@ }; static const char *const cannonlake_pch_h_group_aza_names[] = { - "HDA_BCLK", - "HDA_RST_B", - "HDA_SYNC", - "HDA_SDO", - "HDA_SDI_0", - "HDA_SDI_1", - "I2S1_SFRM", - "I2S1_TXD", + "HDA_BCLK", "HDA_BCLK", "I2S0_SCLK", "n/a", + "HDA_RST_B", "HDA_RST#", "I2S1_SCLK", "SNDW1_CLK", + "HDA_SYNC", "HDA_SYNC", "I2S0_SFRM", "n/a", + "HDA_SDO", "HDA_SDO", "I2S0_TXD", "n/a", + "HDA_SDI0", "HDA_SDI0", "I2S0_RXD", "n/a", + "HDA_SDI1", "HDA_SDI1", "I2S1_RXD", "SNDW1_DATA", + "I2S1_SFRM", "I2S1_SFRM", "SNDW2_CLK", "n/a", + "I2S1_TXD", "I2S1_TXD", "SNDW2_DATA", "n/a", }; static const char *const cannonlake_pch_h_group_vgpio_0_names[] = { - "CNV_BTEN", - "CNV_GNEN", - "CNV_WFEN", - "CNV_WCEN", - "CNV_BT_HOST_WAKE_B", - "vCNV_GNSS_HOST_WAKE_B", - "vSD3_CD_B", - "CNV_BT_IF_SELECT", - "vCNV_BT_UART_TXD", - "vCNV_BT_UART_RXD", - "vCNV_BT_UART_CTS_B", - "vCNV_BT_UART_RTS_B", - "vCNV_MFUART1_TXD", - "vCNV_MFUART1_RXD", - "vCNV_MFUART1_CTS_B", - "vCNV_MFUART1_RTS_B", - "vCNV_GNSS_UART_TXD", - "vCNV_GNSS_UART_RXD", - "vCNV_GNSS_UART_CTS_B", - "vCNV_GNSS_UART_RTS_B", - "vUART0_TXD", - "vUART0_RXD", - "vUART0_CTS_B", - "vUART0_RTS_B", - "vISH_UART0_TXD", - "vISH_UART0_RXD", - "vISH_UART0_CTS_B", - "vISH_UART0_RTS_B", - "vISH_UART1_TXD", - "vISH_UART1_RXD", - "vISH_UART1_CTS_B", - "vISH_UART1_RTS_B", + "CNV_BTEN", "n/a", "n/a", "n/a", + "CNV_GNEN", "n/a", "n/a", "n/a", + "CNV_WFEN", "n/a", "n/a", "n/a", + "CNV_WCEN", "n/a", "n/a", "n/a", + "vCNV_GNSS_HOST_WAKE_B", "n/a", "n/a", "n/a", + "vSD3_CD_B", "n/a", "n/a", "n/a", + "CNV_BT_HOST_WAKE_B", "n/a", "n/a", "n/a", + "CNV_BT_IF_SELECT", "n/a", "n/a", "n/a", + "vCNV_BT_UART_TXD", "ISH UART0", "SIo UART2", "n/a", + "vCNV_BT_UART_RXD", "ISH UART0", "SIo UART2", "n/a", + "vCNV_BT_UART_CTS_B", "ISH UART0", "SIo UART2", "n/a", + "vCNV_BT_UART_RTS_B", "ISH UART0", "SIo UART2", "n/a", + "vCNV_MFUART1_TXD", "ISH UART0", "SIo UART2", "n/a", + "vCNV_MFUART1_RXD", "ISH UART0", "SIo UART2", "n/a", + "vCNV_MFUART1_CTS_B", "ISH UART0", "SIo UART2", "n/a", + "vCNV_MFUART1_RTS_B", "ISH UART0", "SIo UART2", "n/a", + "vCNV_GNSS_UART_TXD", "n/a", "n/a", "n/a", + "vCNV_GNSS_UART_RXD", "n/a", "n/a", "n/a", + "vCNV_GNSS_UART_CTS_B", "n/a", "n/a", "n/a", + "vCNV_GNSS_UART_RTS_B", "n/a", "n/a", "n/a", + "vUART0_TXD", "mapped", "n/a", "n/a", + "vUART0_RXD", "mapped", "n/a", "n/a", + "vUART0_CTS_B", "mapped", "n/a", "n/a", + "vUART0_RTS_B", "mapped", "n/a", "n/a", + "vISH_UART0_TXD", "mapped", "n/a", "n/a", + "vISH_UART0_RXD", "mapped", "n/a", "n/a", + "vISH_UART0_CTS_B", "mapped", "n/a", "n/a", + "vISH_UART0_RTS_B", "mapped", "n/a", "n/a", + "vISH_UART1_TXD", "mapped", "n/a", "n/a", + "vISH_UART1_RXD", "mapped", "n/a", "n/a", + "vISH_UART1_CTS_B", "mapped", "n/a", "n/a", + "vISH_UART1_RTS_B", "mapped", "n/a", "n/a", }; static const char *const cannonlake_pch_h_group_vgpio_1_names[] = { - "vCNV_BT_I2S_BCLK", - "vCNV_BT_I2S_WS_SYNC", - "vCNV_BT_I2S_SDO", - "vCNV_BT_I2S_SDI", - "vSSP2_SCLK", - "vSSP2_SFRM", - "vSSP2_TXD", - "vSSP2_RXD", + "vCNV_BT_I2S_BCLK", "SSP0", "SSP1", "SSP2", + "vCNV_BT_I2S_WS_SYNC", "SSP0", "SSP1", "SSP2", + "vCNV_BT_I2S_SDO", "SSP0", "SSP1", "SSP2", + "vCNV_BT_I2S_SDI", "SSP0", "SSP1", "SSP2", + "vSSP2_SCLK", "mapped", "n/a", "n/a", + "vSSP2_SFRM", "mapped", "n/a", "n/a", + "vSSP2_TXD", "mapped", "n/a", "n/a", + "vSSP2_RXD", "n/a", "n/a", "n/a", }; static const char *const cannonlake_pch_h_group_h_names[] = { @@ -280,9 +280,9 @@ "GPP_I12", "M2_SKT2_CFG1", "n/a", "GPP_I13", "M2_SKT2_CFG2", "n/a", "GPP_I14", "M2_SKT2_CFG3", "n/a", - "SYS_PWROK", "n/a", "n/a", - "SYS_RESET_B", "n/a", "n/a", - "CL_RST_B", "n/a", "n/a", + "SYS_PWROK", "SYS_PWROK", "n/a", + "SYS_RESET_B", "SYS_RESET#", "n/a", + "CL_RST_B", "CL_RST#", "n/a", }; static const char *const cannonlake_pch_h_group_j_names[] = { @@ -386,8 +386,8 @@ static const struct gpio_group cannonlake_pch_h_group_spi = { .display = "------- GPIO Group SPI -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_spi_names) / 1, - .func_count = 1, + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_spi_names) / 2, + .func_count = 2, .pad_names = cannonlake_pch_h_group_spi_names, }; @@ -400,22 +400,22 @@ static const struct gpio_group cannonlake_pch_h_group_aza = { .display = "------- GPIO Group AZA -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_aza_names) / 1, - .func_count = 1, + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_aza_names) / 4, + .func_count = 4, .pad_names = cannonlake_pch_h_group_aza_names, }; static const struct gpio_group cannonlake_pch_h_group_vgpio_0 = { .display = "------- GPIO Group VGPIO_0 -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_vgpio_0_names) / 1, - .func_count = 1, + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_vgpio_0_names) / 4, + .func_count = 4, .pad_names = cannonlake_pch_h_group_vgpio_0_names, }; static const struct gpio_group cannonlake_pch_h_group_vgpio_1 = { .display = "------- GPIO Group VGPIO_1 -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_vgpio_1_names) / 1, - .func_count = 1, + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_vgpio_1_names) / 4, + .func_count = 4, .pad_names = cannonlake_pch_h_group_vgpio_1_names, }; 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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71339d66362d29806c91375c214e9fb84c989201 Gerrit-Change-Number: 45203 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged
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Change in coreboot[master]: util/inteltool: rename GPIO_RSVD_* to their correct names for CNL-H
by Michael Niewöhner (Code Review)
11 Nov '20
11 Nov '20
Michael Niewöhner has submitted this change. (
https://review.coreboot.org/c/coreboot/+/45202
) Change subject: util/inteltool: rename GPIO_RSVD_* to their correct names for CNL-H ...................................................................... util/inteltool: rename GPIO_RSVD_* to their correct names for CNL-H The names of the GPIO_RSVD_* are documented in the PCH EDS, in Linux (linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places. Also, see soc/intel/tigerlake for reference. Change-Id: Ifd6cabb646000c8dff695c5c4f7196b2779f1430 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on:
https://review.coreboot.org/c/coreboot/+/45202
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M util/inteltool/gpio_names/cannonlake.h 1 file changed, 75 insertions(+), 75 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved diff --git a/util/inteltool/gpio_names/cannonlake.h b/util/inteltool/gpio_names/cannonlake.h index 305a1c3..0743936 100644 --- a/util/inteltool/gpio_names/cannonlake.h +++ b/util/inteltool/gpio_names/cannonlake.h @@ -4,60 +4,60 @@ #include "gpio_groups.h" static const char *const cannonlake_pch_h_group_a_names[] = { - "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", - "GPP_A1", "LAD0", "n/a", "ESPI_IO0", - "GPP_A2", "LAD1", "n/a", "ESPI_IO1", - "GPP_A3", "LAD2", "n/a", "ESPI_IO2", - "GPP_A4", "LAD3", "n/a", "ESPI_IO3", - "GPP_A5", "LFRAME#", "n/a", "ESPI_CS0#", - "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", - "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", - "GPP_A8", "CLKRUN#", "n/a", "n/a", - "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", - "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", - "GPP_A11", "PME#", "SD_VDD2_PWR_EN#", "n/a", - "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", - "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", - "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", - "GPP_A15", "SUSACK#", "n/a", "n/a", - "GPP_A16", "CLKOUT_48", "n/a", "n/a", - "GPP_A17", "SD_VDD1_PWR_EN#", "ISH_GP7", "n/a", - "GPP_A18", "ISH_GP0", "n/a", "n/a", - "GPP_A19", "ISH_GP1", "n/a", "n/a", - "GPP_A20", "ISH_GP2", "n/a", "n/a", - "GPP_A21", "ISH_GP3", "n/a", "n/a", - "GPP_A22", "ISH_GP4", "n/a", "n/a", - "GPP_A23", "ISH_GP5", "n/a", "n/a", - "GPIO_RSVD_0", "n/a", "n/a", "n/a", + "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", + "GPP_A1", "LAD0", "n/a", "ESPI_IO0", + "GPP_A2", "LAD1", "n/a", "ESPI_IO1", + "GPP_A3", "LAD2", "n/a", "ESPI_IO2", + "GPP_A4", "LAD3", "n/a", "ESPI_IO3", + "GPP_A5", "LFRAME#", "n/a", "ESPI_CS0#", + "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", + "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "SD_VDD2_PWR_EN#", "n/a", + "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", + "GPP_A15", "SUSACK#", "n/a", "n/a", + "GPP_A16", "CLKOUT_48", "n/a", "n/a", + "GPP_A17", "SD_VDD1_PWR_EN#", "ISH_GP7", "n/a", + "GPP_A18", "ISH_GP0", "n/a", "n/a", + "GPP_A19", "ISH_GP1", "n/a", "n/a", + "GPP_A20", "ISH_GP2", "n/a", "n/a", + "GPP_A21", "ISH_GP3", "n/a", "n/a", + "GPP_A22", "ISH_GP4", "n/a", "n/a", + "GPP_A23", "ISH_GP5", "n/a", "n/a", + "ESPI_CLK_LOOPBK", "ESPI_CLK_LOOPBK", "n/a", "n/a", }; static const char *const cannonlake_pch_h_group_b_names[] = { - "GPP_B0", "GSPI0_CS1#", "n/a", - "GPP_B1", "GSPI1_CS1#", "TIME_SYNC1", - "GPP_B2", "VRALERT#", "n/a", - "GPP_B3", "CPU_GP2", "n/a", - "GPP_B4", "CPU_GP3", "n/a", - "GPP_B5", "SRCCLKREQ0#", "n/a", - "GPP_B6", "SRCCLKREQ1#", "n/a", - "GPP_B7", "SRCCLKREQ2#", "n/a", - "GPP_B8", "SRCCLKREQ3#", "n/a", - "GPP_B9", "SRCCLKREQ4#", "n/a", - "GPP_B10", "SRCCLKREQ5#", "n/a", - "GPP_B11", "I2S_MCLK", "n/a", - "GPP_B12", "SLP_S0#", "n/a", - "GPP_B13", "PLTRST#", "n/a", - "GPP_B14", "SPKR", "n/a", - "GPP_B15", "GSPI0_CS0#", "n/a", - "GPP_B16", "GSPI0_CLK", "n/a", - "GPP_B17", "GSPI0_MISO", "n/a", - "GPP_B18", "GSPI0_MOSI", "n/a", - "GPP_B19", "GSPI1_CS0#", "n/a", - "GPP_B20", "GSPI1_CLK", "n/a", - "GPP_B21", "GSPI1_MISO", "n/a", - "GPP_B22", "GSPI1_MOSI", "n/a", - "GPP_B23", "SML1ALERT#", "PCHHOT#", - "GPIO_RSVD_1", "n/a", "n/a", - "GPIO_RSVD_2", "n/a", "n/a", + "GPP_B0", "GSPI0_CS1#", "n/a", + "GPP_B1", "GSPI1_CS1#", "TIME_SYNC1", + "GPP_B2", "VRALERT#", "n/a", + "GPP_B3", "CPU_GP2", "n/a", + "GPP_B4", "CPU_GP3", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", + "GPP_B11", "I2S_MCLK", "n/a", + "GPP_B12", "SLP_S0#", "n/a", + "GPP_B13", "PLTRST#", "n/a", + "GPP_B14", "SPKR", "n/a", + "GPP_B15", "GSPI0_CS0#", "n/a", + "GPP_B16", "GSPI0_CLK", "n/a", + "GPP_B17", "GSPI0_MISO", "n/a", + "GPP_B18", "GSPI0_MOSI", "n/a", + "GPP_B19", "GSPI1_CS0#", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", + "GSPI0_CLK_LOOPBK", "GSPI0_CLK_LOOPBK", "n/a", + "GSPI1_CLK_LOOPBK", "GSPI1_CLK_LOOPBK", "n/a", }; static const char *const cannonlake_pch_h_group_c_names[] = { @@ -158,15 +158,15 @@ }; static const char *const cannonlake_pch_h_group_spi_names[] = { - "GPIO_RSVD_11", - "GPIO_RSVD_12", - "GPIO_RSVD_13", - "GPIO_RSVD_14", - "GPIO_RSVD_15", - "GPIO_RSVD_16", - "GPIO_RSVD_17", - "GPIO_RSVD_18", - "GPIO_RSVD_19", + "SPI0_IO_2", + "SPI0_IO_3", + "SPI0_MISO", + "SPI0_MOSI", + "SPI0_CS2_B", + "SPI0_CS0_B", + "SPI0_CS1_B", + "SPI0_CLK", + "SPI0_CLK_LOOPBK", }; static const char *const cannonlake_pch_h_group_g_names[] = { @@ -181,14 +181,14 @@ }; static const char *const cannonlake_pch_h_group_aza_names[] = { - "GPIO_RSVD_3", - "GPIO_RSVD_4", - "GPIO_RSVD_5", - "GPIO_RSVD_6", - "GPIO_RSVD_7", - "GPIO_RSVD_8", - "GPIO_RSVD_9", - "GPIO_RSVD_10", + "HDA_BCLK", + "HDA_RST_B", + "HDA_SYNC", + "HDA_SDO", + "HDA_SDI_0", + "HDA_SDI_1", + "I2S1_SFRM", + "I2S1_TXD", }; static const char *const cannonlake_pch_h_group_vgpio_0_names[] = { @@ -196,8 +196,8 @@ "CNV_GNEN", "CNV_WFEN", "CNV_WCEN", - "CNV_BT_HOST_WAKEB", - "vCNV_GNSS_HOST_WAKEB", + "CNV_BT_HOST_WAKE_B", + "vCNV_GNSS_HOST_WAKE_B", "vSD3_CD_B", "CNV_BT_IF_SELECT", "vCNV_BT_UART_TXD", @@ -215,11 +215,11 @@ "vUART0_TXD", "vUART0_RXD", "vUART0_CTS_B", - "vUART0_RTSB", + "vUART0_RTS_B", "vISH_UART0_TXD", "vISH_UART0_RXD", "vISH_UART0_CTS_B", - "vISH_UART0_RTSB", + "vISH_UART0_RTS_B", "vISH_UART1_TXD", "vISH_UART1_RXD", "vISH_UART1_CTS_B", @@ -280,9 +280,9 @@ "GPP_I12", "M2_SKT2_CFG1", "n/a", "GPP_I13", "M2_SKT2_CFG2", "n/a", "GPP_I14", "M2_SKT2_CFG3", "n/a", - "GPIO_RSVD_40", "n/a", "n/a", - "GPIO_RSVD_41", "n/a", "n/a", - "GPIO_RSVD_42", "n/a", "n/a", + "SYS_PWROK", "n/a", "n/a", + "SYS_RESET_B", "n/a", "n/a", + "CL_RST_B", "n/a", "n/a", }; static const char *const cannonlake_pch_h_group_j_names[] = { -- To view, visit
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd6cabb646000c8dff695c5c4f7196b2779f1430 Gerrit-Change-Number: 45202 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged
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Change in coreboot[master]: util/inteltool: add missing native functions of special pads for CNL-LP
by Michael Niewöhner (Code Review)
11 Nov '20
11 Nov '20
Michael Niewöhner has submitted this change. (
https://review.coreboot.org/c/coreboot/+/45305
) Change subject: util/inteltool: add missing native functions of special pads for CNL-LP ...................................................................... util/inteltool: add missing native functions of special pads for CNL-LP Add the missing native functions for special gpio pads for CNL-LP, which are documented in the PCH EDS and other places. Also, see soc/intel/tigerlake for reference. Change-Id: Iedb726aa3afdbbbedafb67f6b7668bf591c2b9b4 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on:
https://review.coreboot.org/c/coreboot/+/45305
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M util/inteltool/gpio_names/cannonlake_lp.h 1 file changed, 26 insertions(+), 26 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved diff --git a/util/inteltool/gpio_names/cannonlake_lp.h b/util/inteltool/gpio_names/cannonlake_lp.h index 9d9c66b..27d820c 100644 --- a/util/inteltool/gpio_names/cannonlake_lp.h +++ b/util/inteltool/gpio_names/cannonlake_lp.h @@ -75,36 +75,36 @@ }; const char *const cannonlake_pch_lp_group_c_names[] = { - "GPP_C0", "SMBCLK", "n/a", - "GPP_C1", "SMBDATA", "n/a", - "GPP_C2", "SMBALERT#", "n/a", - "GPP_C3", "SML0CLK", "n/a", - "GPP_C4", "SML0DATA", "n/a", - "GPP_C5", "SML0ALERT#", "n/a", - "GPP_C6", "SML1CLK", "n/a", - "GPP_C7", "SML1DATA", "n/a", - "GPP_C8", "UART0_RXD", "n/a", - "GPP_C9", "UART0_TXD", "n/a", - "GPP_C10", "UART0_RTS#", "n/a", - "GPP_C11", "UART0_CTS#", "n/a", - "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", - "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", - "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", - "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", - "GPP_C16", "I2C0_SDA", "n/a", - "GPP_C17", "I2C0_SCL", "n/a", - "GPP_C18", "I2C1_SDA", "n/a", - "GPP_C19", "I2C1_SCL", "n/a", - "GPP_C20", "UART2_RXD", "n/a", - "GPP_C21", "UART2_TXD", "n/a", - "GPP_C22", "UART2_RTS#", "n/a", - "GPP_C23", "UART2_CTS#", "n/a", + "GPP_C0", "SMBCLK", "n/a", "n/a", + "GPP_C1", "SMBDATA", "n/a", "n/a", + "GPP_C2", "SMBALERT#", "n/a", "n/a", + "GPP_C3", "SML0CLK", "n/a", "n/a", + "GPP_C4", "SML0DATA", "n/a", "n/a", + "GPP_C5", "SML0ALERT#", "n/a", "n/a", + "GPP_C6", "SML1CLK", "n/a", "n/a", + "GPP_C7", "SML1DATA", "n/a", "n/a", + "GPP_C8", "UART0_RXD", "n/a", "n/a", + "GPP_C9", "UART0_TXD", "n/a", "n/a", + "GPP_C10", "UART0_RTS#", "n/a", "n/a", + "GPP_C11", "UART0_CTS#", "n/a", "n/a", + "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "CNV_MFUART1_RXD", + "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "CNV_MFUART1_TXD", + "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "CNV_MFUART1_RTS", + "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "CNV_MFUART1_CTS", + "GPP_C16", "I2C0_SDA", "n/a", "n/a", + "GPP_C17", "I2C0_SCL", "n/a", "n/a", + "GPP_C18", "I2C1_SDA", "n/a", "n/a", + "GPP_C19", "I2C1_SCL", "n/a", "n/a", + "GPP_C20", "UART2_RXD", "n/a", "n/a", + "GPP_C21", "UART2_TXD", "n/a", "n/a", + "GPP_C22", "UART2_RTS#", "n/a", "n/a", + "GPP_C23", "UART2_CTS#", "n/a", "n/a", }; const struct gpio_group cannonlake_pch_lp_group_c = { .display = "------- GPIO Group GPP_C -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_c_names) / 3, - .func_count = 3, + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_c_names) / 4, + .func_count = 4, .pad_names = cannonlake_pch_lp_group_c_names, }; -- To view, visit
https://review.coreboot.org/c/coreboot/+/45305
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedb726aa3afdbbbedafb67f6b7668bf591c2b9b4 Gerrit-Change-Number: 45305 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged
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Change in coreboot[master]: util/inteltool: rename GPIO_RSVD_* to their correct names for CNL-LP
by Michael Niewöhner (Code Review)
11 Nov '20
11 Nov '20
Michael Niewöhner has submitted this change. (
https://review.coreboot.org/c/coreboot/+/45200
) Change subject: util/inteltool: rename GPIO_RSVD_* to their correct names for CNL-LP ...................................................................... util/inteltool: rename GPIO_RSVD_* to their correct names for CNL-LP The names of the GPIO_RSVD_* are documented in the PCH EDS, in Linux (linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places. Also, see soc/intel/tigerlake for reference. Change-Id: I86c7159d9f48560c41efdfe49f162aef00499d13 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on:
https://review.coreboot.org/c/coreboot/+/45200
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M util/inteltool/gpio_names/cannonlake_lp.h 1 file changed, 76 insertions(+), 76 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved diff --git a/util/inteltool/gpio_names/cannonlake_lp.h b/util/inteltool/gpio_names/cannonlake_lp.h index 0aa69b0..9d9c66b 100644 --- a/util/inteltool/gpio_names/cannonlake_lp.h +++ b/util/inteltool/gpio_names/cannonlake_lp.h @@ -4,31 +4,31 @@ #include "gpio_groups.h" const char *const cannonlake_pch_lp_group_a_names[] = { - "GPP_A0", "RCIN#", "TIME_SYNC1", "n/a", - "GPP_A1", "LAD0", "ESPI_IO0", "n/a", - "GPP_A2", "LAD1", "ESPI_IO1", "n/a", - "GPP_A3", "LAD2", "ESPI_IO2", "n/a", - "GPP_A4", "LAD3", "ESPI_IO3", "n/a", - "GPP_A5", "LFRAME#", "ESPI_CS0#", "n/a", - "GPP_A6", "SERIRQ", "n/a", "n/a", - "GPP_A7", "PIRQA#", "GSPI0_CS1#", "n/a", - "GPP_A8", "CLKRUN#", "n/a", "n/a", - "GPP_A9", "CLKOUT_LPC0", "ESPI_CLK", "n/a", - "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", - "GPP_A11", "PME#", "GSPI1_CS1#", "SD_VDD2_PWR_EN#", - "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", - "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", - "GPP_A14", "SUS_STAT#", "ESPI_RESET#", "n/a", - "GPP_A15", "SUSACK#", "n/a", "n/a", - "GPP_A16", "SD_1P8_SEL", "n/a", "n/a", - "GPP_A17", "SD_VDD1_PWR_EN#", "ISH_GP7", "n/a", - "GPP_A18", "ISH_GP0", "n/a", "n/a", - "GPP_A19", "ISH_GP1", "n/a", "n/a", - "GPP_A20", "ISH_GP2", "n/a", "n/a", - "GPP_A21", "ISH_GP3", "n/a", "n/a", - "GPP_A22", "ISH_GP4", "n/a", "n/a", - "GPP_A23", "ISH_GP5", "n/a", "n/a", - "GPIO_RSVD_0", "n/a", "n/a", "n/a", + "GPP_A0", "RCIN#", "TIME_SYNC1", "n/a", + "GPP_A1", "LAD0", "ESPI_IO0", "n/a", + "GPP_A2", "LAD1", "ESPI_IO1", "n/a", + "GPP_A3", "LAD2", "ESPI_IO2", "n/a", + "GPP_A4", "LAD3", "ESPI_IO3", "n/a", + "GPP_A5", "LFRAME#", "ESPI_CS0#", "n/a", + "GPP_A6", "SERIRQ", "n/a", "n/a", + "GPP_A7", "PIRQA#", "GSPI0_CS1#", "n/a", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "ESPI_CLK", "n/a", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "GSPI1_CS1#", "SD_VDD2_PWR_EN#", + "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "SUS_STAT#", "ESPI_RESET#", "n/a", + "GPP_A15", "SUSACK#", "n/a", "n/a", + "GPP_A16", "SD_1P8_SEL", "n/a", "n/a", + "GPP_A17", "SD_VDD1_PWR_EN#", "ISH_GP7", "n/a", + "GPP_A18", "ISH_GP0", "n/a", "n/a", + "GPP_A19", "ISH_GP1", "n/a", "n/a", + "GPP_A20", "ISH_GP2", "n/a", "n/a", + "GPP_A21", "ISH_GP3", "n/a", "n/a", + "GPP_A22", "ISH_GP4", "n/a", "n/a", + "GPP_A23", "ISH_GP5", "n/a", "n/a", + "ESPI_CLK_LOOPBK", "ESPI_CLK_LOOPBK", "n/a", "n/a", }; const struct gpio_group cannonlake_pch_lp_group_a = { @@ -39,32 +39,32 @@ }; const char *const cannonlake_pch_lp_group_b_names[] = { - "GPP_B0", "Reserved", "n/a", - "GPP_B1", "Reserved", "n/a", - "GPP_B2", "VRALERT#", "n/a", - "GPP_B3", "CPU_GP2", "n/a", - "GPP_B4", "CPU_GP3", "n/a", - "GPP_B5", "SRCCLKREQ0#", "n/a", - "GPP_B6", "SRCCLKREQ1#", "n/a", - "GPP_B7", "SRCCLKREQ2#", "n/a", - "GPP_B8", "SRCCLKREQ3#", "n/a", - "GPP_B9", "SRCCLKREQ4#", "n/a", - "GPP_B10", "SRCCLKREQ5#", "n/a", - "GPP_B11", "EXT_PWR_GATE#", "n/a", - "GPP_B12", "SLP_S0#", "n/a", - "GPP_B13", "PLTRST#", "n/a", - "GPP_B14", "SPKR", "n/a", - "GPP_B15", "GSPI0_CS0#", "n/a", - "GPP_B16", "GSPI0_CLK", "n/a", - "GPP_B17", "GSPI0_MISO", "n/a", - "GPP_B18", "GSPI0_MOSI", "n/a", - "GPP_B19", "GSPI1_CS0#", "n/a", - "GPP_B20", "GSPI1_CLK", "n/a", - "GPP_B21", "GSPI1_MISO", "n/a", - "GPP_B22", "GSPI1_MOSI", "n/a", - "GPP_B23", "SML1ALERT#", "PCHHOT#", - "GPIO_RSVD_1", "n/a", "n/a", - "GPIO_RSVD_2", "n/a", "n/a", + "GPP_B0", "CORE_VID0", "n/a", + "GPP_B1", "CORE_VID1", "n/a", + "GPP_B2", "VRALERT#", "n/a", + "GPP_B3", "CPU_GP2", "n/a", + "GPP_B4", "CPU_GP3", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", + "GPP_B11", "EXT_PWR_GATE#", "n/a", + "GPP_B12", "SLP_S0#", "n/a", + "GPP_B13", "PLTRST#", "n/a", + "GPP_B14", "SPKR", "n/a", + "GPP_B15", "GSPI0_CS0#", "n/a", + "GPP_B16", "GSPI0_CLK", "n/a", + "GPP_B17", "GSPI0_MISO", "n/a", + "GPP_B18", "GSPI0_MOSI", "n/a", + "GPP_B19", "GSPI1_CS0#", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", + "GSPI0_CLK_LOOPBK", "GSPI0_CLK_LOOPBK", "n/a", + "GSPI1_CLK_LOOPBK", "GSPI1_CLK_LOOPBK", "n/a", }; const struct gpio_group cannonlake_pch_lp_group_b = { @@ -109,31 +109,31 @@ }; const char *const cannonlake_pch_lp_group_d_names[] = { - "GPP_D0", "SPI1_CS#", "BK0", "SBK0", - "GPP_D1", "SPI1_CLK", "BK1", "SBK1", - "GPP_D2", "SPI1_MISO", "BK2", "SBK2", - "GPP_D3", "SPI1_MOSI", "BK3", "SBK3", - "GPP_D4", "IMGCLKOUT0", "BK4", "SBK4", - "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a", - "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a", - "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a", - "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a", - "GPP_D9", "ISH_SPI_CS#", "n/a", "GSPI2_CS0#", - "GPP_D10", "ISH_SPI_CLK", "n/a", "GSPI2_CLK", - "GPP_D11", "ISH_SPI_MISO", "n/a", "GSPI2_MISO", - "GPP_D12", "ISH_SPI_MOSI", "n/a", "GSPI2_MOSI", - "GPP_D13", "ISH_UART0_RXD", "SML0BDATA", "I2C4B_SDA", - "GPP_D14", "ISH_UART0_TXD", "SML0BCLK", "I2C4B_SCL", - "GPP_D15", "ISH_UART0_RTS#", "GSPI2_CS1#", "n/a", - "GPP_D16", "ISH_UART0_CTS#", "SML0BALERT", "n/a", - "GPP_D17", "DMIC_CLK1", "SNDW3_CLK", "n/a", - "GPP_D18", "DMIC_DATA1", "SNDW3_DATA", "n/a", - "GPP_D19", "DMIC_CLK0", "SNDW4_CLK", "n/a", - "GPP_D20", "DMIC_DATA0", "SNDW4_DATA", "n/a", - "GPP_D21", "SPI1_IO2", "n/a", "n/a", - "GPP_D22", "SPI1_IO3", "n/a", "n/a", - "GPP_D23", "I2S_MCLK", "n/a", "n/a", - "GPIO_RSVD_12", "n/a", "n/a", "n/a", + "GPP_D0", "SPI1_CS#", "BK0", "SBK0", + "GPP_D1", "SPI1_CLK", "BK1", "SBK1", + "GPP_D2", "SPI1_MISO", "BK2", "SBK2", + "GPP_D3", "SPI1_MOSI", "BK3", "SBK3", + "GPP_D4", "IMGCLKOUT0", "BK4", "SBK4", + "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a", + "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a", + "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a", + "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a", + "GPP_D9", "ISH_SPI_CS#", "n/a", "GSPI2_CS0#", + "GPP_D10", "ISH_SPI_CLK", "n/a", "GSPI2_CLK", + "GPP_D11", "ISH_SPI_MISO", "n/a", "GSPI2_MISO", + "GPP_D12", "ISH_SPI_MOSI", "n/a", "GSPI2_MOSI", + "GPP_D13", "ISH_UART0_RXD", "SML0BDATA", "I2C4B_SDA", + "GPP_D14", "ISH_UART0_TXD", "SML0BCLK", "I2C4B_SCL", + "GPP_D15", "ISH_UART0_RTS#", "GSPI2_CS1#", "n/a", + "GPP_D16", "ISH_UART0_CTS#", "SML0BALERT", "n/a", + "GPP_D17", "DMIC_CLK1", "SNDW3_CLK", "n/a", + "GPP_D18", "DMIC_DATA1", "SNDW3_DATA", "n/a", + "GPP_D19", "DMIC_CLK0", "SNDW4_CLK", "n/a", + "GPP_D20", "DMIC_DATA0", "SNDW4_DATA", "n/a", + "GPP_D21", "SPI1_IO2", "n/a", "n/a", + "GPP_D22", "SPI1_IO3", "n/a", "n/a", + "GPP_D23", "I2S_MCLK", "n/a", "n/a", + "GSPI2_CLK_LOOPBK", "GSPI2_CLK_LOOPBK", "n/a", "n/a", }; const struct gpio_group cannonlake_pch_lp_group_d = { -- To view, visit
https://review.coreboot.org/c/coreboot/+/45200
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86c7159d9f48560c41efdfe49f162aef00499d13 Gerrit-Change-Number: 45200 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged
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Change in coreboot[master]: soc/amd/picasso: Use common SMM save state ops
by Arthur Heymans (Code Review)
11 Nov '20
11 Nov '20
Arthur Heymans has uploaded this change for review. (
https://review.coreboot.org/c/coreboot/+/37019
) Change subject: soc/amd/picasso: Use common SMM save state ops ...................................................................... soc/amd/picasso: Use common SMM save state ops Change-Id: I9eb42b9f9b14925a682356e21bbb0d2ccaeaafec Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/picasso/smihandler.c 1 file changed, 24 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37019/1 diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 39c2dfd..b04eddb 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <cpu/x86/cache.h> -#include <cpu/amd/amd64_save_state.h> #include <arch/acpi.h> #include <arch/hlt.h> #include <device/pci_def.h> @@ -41,17 +40,18 @@ SMM_IO_TRAP_PORT_ADDRESS_MASK); } -static void *find_save_state(int cmd) +static int find_save_state_node(int cmd) { int core; - amd64_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); u32 smm_io_trap; u8 reg_al; + u64 rax; /* Check all nodes looking for the one that issued the IO */ for (core = 0; core < CONFIG_MAX_CPUS; core++) { - state = smm_get_save_state(core); - smm_io_trap = state->smm_io_trap_offset; + if (ops->get_io_trap(core, &smm_io_trap)) + continue; /* Check for Valid IO Trap Word (bit1==1) */ if (!(smm_io_trap & SMM_IO_TRAP_VALID)) continue; @@ -62,30 +62,39 @@ if (pm_acpi_smi_cmd_port() != get_io_address(smm_io_trap)) continue; /* Check AL against the requested command */ - reg_al = state->rax; + if (ops->get_reg(core, RAX, &rax)) + continue; + reg_al = rax; if (reg_al == cmd) - return state; + return core; } - return NULL; + return -1; } static void southbridge_smi_gsmi(void) { + u32 ret, param; u8 sub_command; - amd64_smm_state_save_area_t *io_smi; - u32 reg_ebx; + int node = find_save_state_node(APM_CNT_ELOG_GSMI); + const struct smm_save_state_ops *ops = get_save_state_ops(); - io_smi = find_save_state(APM_CNT_ELOG_GSMI); - if (!io_smi) + if (node < -1) return; + /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; + uint64_t reg; + if (ops->get_reg(node, RAX, ®)) + return; + sub_command = (u8)(reg >> 8); /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; + if (ops->get_reg(node, RBX, ®)) + return; + param = reg & UINT32_MAX; /* drivers/elog/gsmi.c */ - io_smi->rax = gsmi_exec(sub_command, ®_ebx); + ret = gsmi_exec(sub_command, (u32 *)param); + ops->set_reg(node, RAX, reg); } static void sb_apmc_smi_handler(void) -- To view, visit
https://review.coreboot.org/c/coreboot/+/37019
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9eb42b9f9b14925a682356e21bbb0d2ccaeaafec Gerrit-Change-Number: 37019 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange
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Change in coreboot[master]: soc/amd/stoneyridge: Use common SMM save state ops
by Arthur Heymans (Code Review)
11 Nov '20
11 Nov '20
Arthur Heymans has uploaded this change for review. (
https://review.coreboot.org/c/coreboot/+/37018
) Change subject: soc/amd/stoneyridge: Use common SMM save state ops ...................................................................... soc/amd/stoneyridge: Use common SMM save state ops Change-Id: I2f98062dd254528c0c72e8739035c9e620a8497f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/stoneyridge/smihandler.c 1 file changed, 24 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/37018/1 diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index 2b88397..d2945c8 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <cpu/x86/cache.h> -#include <cpu/amd/amd64_save_state.h> #include <arch/acpi.h> #include <arch/hlt.h> #include <device/pci_def.h> @@ -41,17 +40,18 @@ SMM_IO_TRAP_PORT_ADDRESS_MASK); } -static void *find_save_state(int cmd) +static int find_save_state_node(int cmd) { int core; - amd64_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); u32 smm_io_trap; u8 reg_al; + u64 rax; /* Check all nodes looking for the one that issued the IO */ for (core = 0; core < CONFIG_MAX_CPUS; core++) { - state = smm_get_save_state(core); - smm_io_trap = state->smm_io_trap_offset; + if (ops->get_io_trap(core, &smm_io_trap)) + continue; /* Check for Valid IO Trap Word (bit1==1) */ if (!(smm_io_trap & SMM_IO_TRAP_VALID)) continue; @@ -62,30 +62,39 @@ if (pm_acpi_smi_cmd_port() != get_io_address(smm_io_trap)) continue; /* Check AL against the requested command */ - reg_al = state->rax; + if (ops->get_reg(core, RAX, &rax)) + continue; + reg_al = rax; if (reg_al == cmd) - return state; + return core; } - return NULL; + return -1; } static void southbridge_smi_gsmi(void) { + u32 ret, param; u8 sub_command; - amd64_smm_state_save_area_t *io_smi; - u32 reg_ebx; + int node = find_save_state_node(APM_CNT_ELOG_GSMI); + const struct smm_save_state_ops *ops = get_save_state_ops(); - io_smi = find_save_state(APM_CNT_ELOG_GSMI); - if (!io_smi) + if (node < -1) return; + /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; + uint64_t reg; + if (ops->get_reg(node, RAX, ®)) + return; + sub_command = (u8)(reg >> 8); /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; + if (ops->get_reg(node, RBX, ®)) + return; + param = reg & UINT32_MAX; /* drivers/elog/gsmi.c */ - io_smi->rax = gsmi_exec(sub_command, ®_ebx); + ret = gsmi_exec(sub_command, (u32 *)param); + ops->set_reg(node, RAX, reg); } static void sb_apmc_smi_handler(void) -- To view, visit
https://review.coreboot.org/c/coreboot/+/37018
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f98062dd254528c0c72e8739035c9e620a8497f Gerrit-Change-Number: 37018 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange
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Change in coreboot[master]: soc/intel/denverton_ns: Use common SMM save state ops
by Arthur Heymans (Code Review)
11 Nov '20
11 Nov '20
Arthur Heymans has uploaded this change for review. (
https://review.coreboot.org/c/coreboot/+/37017
) Change subject: soc/intel/denverton_ns: Use common SMM save state ops ...................................................................... soc/intel/denverton_ns: Use common SMM save state ops Change-Id: Ieb5baaa4e36d97414d87addf5c8e318b881e8996 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/denverton_ns/smihandler.c 1 file changed, 36 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/37017/1 diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index c292e4d..ce0022f 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -23,7 +23,6 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t100_save_state.h> #include <device/pci_def.h> #include <intelblocks/fast_spi.h> #include <spi-generic.h> @@ -168,35 +167,39 @@ * core in case we are not running on the same core that * initiated the IO transaction. */ -static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) +static int smi_apmc_find_state_save_node(u8 cmd) { - em64t100_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); int node; /* Check all nodes looking for the one that issued the IO */ for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0==1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4==0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - + uint32_t io_misc_info; + uint64_t rax; + if (ops->get_reg(node, RAX, &rax)) + continue; /* ??? */ /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) + if ((rax & 0xff) != cmd) continue; + if (ops->get_io_misc_info(node, &io_misc_info)) { - return state; + /* Check for Synchronous IO (bit0 == 1) */ + if (!(io_misc_info & (1 << 0))) + continue; + + /* Make sure it was a write (bit4 == 0) */ + if (io_misc_info & (1 << 4)) + continue; + + /* Check for APMC IO port */ + if (((io_misc_info >> 16) & 0xff) != APM_CNT) + continue; + } + + return node; } - return NULL; + return -1; } static void finalize(void) @@ -217,7 +220,7 @@ static void southbridge_smi_apmc(void) { uint8_t reg8; - em64t100_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); /* Emulate B2 register as the FADT / Linux expects it */ @@ -254,13 +257,18 @@ "SMI#: SMM structures already initialized!\n"); return; } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((uint32_t)state->rbx); - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } + int node = smi_apmc_find_state_save_node(APM_CNT_GNVS_UPDATE); + if (node < -1) + return; + + uint64_t rbx; + if (ops->get_reg(node, RBX, &rbx)) + return; + + /* EBX in the state save contains the GNVS pointer */ + gnvs = (global_nvs_t *)(u32)rbx; + smm_initialized = 1; + printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); break; } -- To view, visit
https://review.coreboot.org/c/coreboot/+/37017
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb5baaa4e36d97414d87addf5c8e318b881e8996 Gerrit-Change-Number: 37017 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange
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