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Change in coreboot[master]: soc/intel/common: Add support for CSE Lite driver to handle CSE RW an...
by Sridhar Siricilla (Code Review) 11 Nov '20

11 Nov '20

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46552 ) Change subject: soc/intel/common: Add support for CSE Lite driver to handle CSE RW and metadata ...................................................................... soc/intel/common: Add support for CSE Lite driver to handle CSE RW and metadata The patch modifies CSE Lite driver to support to have separate CBFS file for metadata of RW blobs. So, the driver expects separate CBFS files for CSE RW and it's metadata. Also, the driver initiates CSE Firmware update path if it finds the metadata's CBFS file. The change gives flexibility to modify RW blob's FMAP locations while maintaining uniform or little modified CSE Lite driver. Currently, CSE RW blob and it's metadata were unified into one RW blob. TEST=Verified on hatch. BRANCH=Puff Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I316344d23987d9907b64efafbe61f36ae7ade337 --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/cse_lite.c 3 files changed, 128 insertions(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/46552/1 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 1cb7d35..6512e3d 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -37,3 +37,15 @@ default "" help Intel CSE CBFS RW blob path and file name + +config SOC_INTEL_CSE_RW_METADATA_CBFS_NAME + string "CBFS entry name for CSE RW blob" + default "me_rw.metadata" + help + CBFS entry name for Intel CSE CBFS RW blob + +config SOC_INTEL_CSE_RW_METADATA_FILE + string "Intel CSE CBFS RW path and filename" + default "" + help + Intel CSE CBFS RW blob path and file name diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 11cc3c2..59ba0cb 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -4,11 +4,20 @@ ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c +ifneq ($(CONFIG_SOC_INTEL_CSE_RW_METADATA_FILE),"") +CSE_LITE_RW_METADATA = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_METADATA_CBFS_NAME)) +regions-for-file-$(CSE_LITE_RW_METADATA) = FW_MAIN_A,FW_MAIN_B +cbfs-files-y += $(CSE_LITE_RW_METADATA) +$(CSE_LITE_RW_METADATA)-file := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_METADATA_FILE)) +$(CSE_LITE_RW_METADATA)-name := $(CSE_LITE_RW_METADATA) +$(CSE_LITE_RW_METADATA)-type := raw +endif + ifneq ($(CONFIG_SOC_INTEL_CSE_RW_FILE),"") -CSE_LITE_ME_RW = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME)) -regions-for-file-$(CSE_LITE_ME_RW) = FW_MAIN_A,FW_MAIN_B -cbfs-files-y += $(CSE_LITE_ME_RW) -$(CSE_LITE_ME_RW)-file := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) -$(CSE_LITE_ME_RW)-name := $(CSE_LITE_ME_RW) -$(CSE_LITE_ME_RW)-type := raw +CSE_LITE_RW = $(call strip_quotes, $(CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME)) +regions-for-file-$(CSE_LITE_RW) = FW_MAIN_A, FW_MAIN_B +cbfs-files-y += $(CSE_LITE_RW) +$(CSE_LITE_RW)-file := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) +$(CSE_LITE_RW)-name := $(CSE_LITE_RW) +$(CSE_LITE_RW)-type := raw endif diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index c9e4e1f..7218a92 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -12,9 +12,6 @@ #include <vb2_api.h> #include <soc/intel/common/reset.h> -/* CSE RW version size reserved in the CSE CBFS RW binary */ -#define CSE_RW_VERSION_SZ 16 - /* Converts bp index to boot partition string */ #define GET_BP_STR(bp_index) (bp_index ? "RW" : "RO") @@ -45,6 +42,9 @@ /* CSE recovery sub-error codes */ enum csme_failure_reason { + + /* No error */ + CSE_LITE_SKU_NO_ERROR = 0, /* Unspecified error */ CSE_LITE_SKU_UNSPECIFIED = 1, @@ -64,7 +64,10 @@ CSE_LITE_SKU_COMMUNICATION_ERROR = 6, /* Fails to wipe CSE runtime data */ - CSE_LITE_SKU_DATA_WIPE_ERROR = 7 + CSE_LITE_SKU_DATA_WIPE_ERROR = 7, + + /* CSE RW is not found */ + CSE_LITE_SKU_RW_BLOB_NOT_FOUND = 8, }; /* @@ -157,6 +160,13 @@ struct cse_bp_info bp_info; } __packed; +/* CSE CBFS RW metadata */ +struct cse_cbfs_rw_info { + /* CSE CBFS RW version */ + struct fw_version fw_ver; + uint8_t reserved[8]; +}; + static void cse_log_status_registers(void) { printk(BIOS_DEBUG, "cse_lite: CSE status registers: HFSTS1: 0x%x, HFSTS2: 0x%x " @@ -423,7 +433,7 @@ { struct cbfsf file_desc; - if (cbfs_boot_locate(&file_desc, CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME, NULL) < 0) + if (cbfs_boot_locate(&file_desc, CONFIG_SOC_INTEL_CSE_RW_METADATA_CBFS_NAME, NULL) < 0) return false; cbfs_file_data(source_rdev, &file_desc); @@ -503,15 +513,33 @@ return true; } -static bool cse_get_cbfs_rw_version(const struct region_device *source_rdev, - void *cse_cbfs_rw_ver) +static bool cse_get_cbfs_rw(struct region_device *rdev) +{ + struct cbfsf file_desc; + + if (cbfs_boot_locate(&file_desc, CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME, NULL) < 0) + return false; + + cbfs_file_data(rdev, &file_desc); + + return true; +} + +static bool cse_get_cbfs_rw_metadata(const struct region_device *source_info_rdev, + struct cse_cbfs_rw_info *source_info) { - if (rdev_readat(source_rdev, (void *) cse_cbfs_rw_ver, 0, sizeof(struct fw_version)) - != sizeof(struct fw_version)) { - printk(BIOS_ERR, "cse_lite: Failed to read CSE CBFW RW version\n"); + if (rdev_readat(source_info_rdev, (void *) source_info, 0, + sizeof(struct cse_cbfs_rw_info)) != sizeof(struct cse_cbfs_rw_info)) { + printk(BIOS_ERR, "cse_lite: Failed to read CSE CBFS RW metadata\n"); return false; } + + printk(BIOS_SPEW, "cse_lite: CSE CBFS RW version : %d.%d.%d.%d\n", + source_info->fw_ver.major, + source_info->fw_ver.minor, + source_info->fw_ver.hotfix, + source_info->fw_ver.build); return true; } @@ -522,30 +550,26 @@ * If ver_cmp_status > 0, coreboot upgrades CSE RW region */ static int cse_check_version_mismatch(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) + const struct cse_cbfs_rw_info *source_info) { - struct fw_version cse_cbfs_rw_ver; const struct fw_version *cse_rw_ver; - if (!cse_get_cbfs_rw_version(source_rdev, &cse_cbfs_rw_ver)) - return false; - printk(BIOS_DEBUG, "cse_lite: CSE CBFS RW version : %d.%d.%d.%d\n", - cse_cbfs_rw_ver.major, - cse_cbfs_rw_ver.minor, - cse_cbfs_rw_ver.hotfix, - cse_cbfs_rw_ver.build); + source_info->fw_ver.major, + source_info->fw_ver.minor, + source_info->fw_ver.hotfix, + source_info->fw_ver.build); cse_rw_ver = cse_get_rw_version(cse_bp_info); - if (cse_cbfs_rw_ver.major != cse_rw_ver->major) - return cse_cbfs_rw_ver.major - cse_rw_ver->major; - else if (cse_cbfs_rw_ver.minor != cse_rw_ver->minor) - return cse_cbfs_rw_ver.minor - cse_rw_ver->minor; - else if (cse_cbfs_rw_ver.hotfix != cse_rw_ver->hotfix) - return cse_cbfs_rw_ver.hotfix - cse_rw_ver->hotfix; + if (source_info->fw_ver.major != cse_rw_ver->major) + return source_info->fw_ver.major - cse_rw_ver->major; + else if (source_info->fw_ver.minor != cse_rw_ver->minor) + return source_info->fw_ver.minor - cse_rw_ver->minor; + else if (source_info->fw_ver.hotfix != cse_rw_ver->hotfix) + return source_info->fw_ver.hotfix - cse_rw_ver->hotfix; else - return cse_cbfs_rw_ver.build - cse_rw_ver->build; + return source_info->fw_ver.build - cse_rw_ver->build; } /* Check if CSE RW data partition is valid or not */ @@ -587,8 +611,8 @@ return true; } -static bool cse_copy_rw(const struct region_device *target_rdev, const void *buf, size_t offset, - size_t size) +static bool cse_copy_rw(const struct region_device *target_rdev, const void *buf, + size_t offset, size_t size) { if (rdev_writeat(target_rdev, buf, offset, size) < 0) { printk(BIOS_ERR, "cse_lite: Failed to update CSE firmware\n"); @@ -599,36 +623,35 @@ } static bool cse_is_rw_version_latest(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) + const struct cse_cbfs_rw_info *source_info) { - return !cse_check_version_mismatch(cse_bp_info, source_rdev); + return !cse_check_version_mismatch(cse_bp_info, source_info); } static bool cse_is_downgrade_instance(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) + const struct cse_cbfs_rw_info *source_info) { - return cse_check_version_mismatch(cse_bp_info, source_rdev) < 0; + return cse_check_version_mismatch(cse_bp_info, source_info) < 0; } static bool cse_is_update_required(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev, struct region_device *target_rdev) + const struct cse_cbfs_rw_info *source_info, struct region_device *target_rdev) { return (!cse_is_rw_bp_sign_valid(target_rdev) || - !cse_is_rw_version_latest(cse_bp_info, source_rdev)); + !cse_is_rw_version_latest(cse_bp_info, source_info)); } static bool cse_write_rw_region(const struct region_device *target_rdev, const struct region_device *source_rdev) { - void *cse_cbfs_rw = rdev_mmap(source_rdev, CSE_RW_VERSION_SZ, - region_device_sz(source_rdev) - CSE_RW_VERSION_SZ); + + void *cse_cbfs_rw = rdev_mmap(source_rdev, 0, region_device_sz(source_rdev)); /* Points to CSE CBFS RW image after boot partition signature */ uint8_t *cse_cbfs_rw_wo_sign = (uint8_t *)cse_cbfs_rw + CSE_RW_SIGN_SIZE; /* Size of CSE CBFS RW image without boot partition signature */ - uint32_t cse_cbfs_rw_wo_sign_sz = region_device_sz(source_rdev) - - (CSE_RW_VERSION_SZ + CSE_RW_SIGN_SIZE); + uint32_t cse_cbfs_rw_wo_sign_sz = region_device_sz(source_rdev) - CSE_RW_SIGN_SIZE; /* Update except CSE RW signature */ if (!cse_copy_rw(target_rdev, cse_cbfs_rw_wo_sign, CSE_RW_SIGN_SIZE, @@ -639,29 +662,32 @@ if (!cse_copy_rw(target_rdev, (void *)cse_cbfs_rw, 0, CSE_RW_SIGN_SIZE)) goto exit_rw_update; - rdev_munmap(source_rdev, cse_cbfs_rw_wo_sign); - return true; + printk(BIOS_INFO, "cse_lite: CSE RW Update Successful\n"); + rdev_munmap(source_rdev, cse_cbfs_rw); + return CSE_LITE_SKU_NO_ERROR; exit_rw_update: - rdev_munmap(source_rdev, cse_cbfs_rw_wo_sign); - return false; + rdev_munmap(source_rdev, cse_cbfs_rw); + return CSE_LITE_SKU_FW_UPDATE_ERROR; } static bool cse_update_rw(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev, struct region_device *target_rdev) + struct region_device *target_rdev) { + + struct region_device source_rdev; + + if (!cse_get_cbfs_rw(&source_rdev)) + return CSE_LITE_SKU_RW_BLOB_NOT_FOUND; + if (!cse_erase_rw_region(target_rdev)) - return false; + return CSE_LITE_SKU_FW_UPDATE_ERROR; - if (!cse_write_rw_region(target_rdev, source_rdev)) - return false; - - printk(BIOS_INFO, "cse_lite: CSE RW Update Successful\n"); - return true; + return cse_write_rw_region(target_rdev, &source_rdev); } static bool cse_prep_for_rw_update(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) + const struct cse_cbfs_rw_info *source_info) { /* * To set CSE's operation mode to HMRFPO mode: @@ -671,7 +697,7 @@ if (!cse_boot_to_ro(cse_bp_info)) return false; - if (cse_is_downgrade_instance(cse_bp_info, source_rdev) && + if (cse_is_downgrade_instance(cse_bp_info, source_info) && !cse_data_clear_request(cse_bp_info)) { printk(BIOS_ERR, "cse_lite: CSE FW downgrade is aborted\n"); return false; @@ -680,20 +706,18 @@ return cse_hmrfpo_enable(); } -static uint8_t cse_trigger_fw_update(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev, struct region_device *target_rdev) +static enum csme_failure_reason cse_trigger_fw_update(const struct cse_bp_info *cse_bp_info, + const struct cse_cbfs_rw_info *source_info, struct region_device *target_rdev) { - if (!cse_prep_for_rw_update(cse_bp_info, source_rdev)) + + if (!cse_prep_for_rw_update(cse_bp_info, source_info)) return CSE_LITE_SKU_COMMUNICATION_ERROR; - if (!cse_update_rw(cse_bp_info, source_rdev, target_rdev)) - return CSE_LITE_SKU_FW_UPDATE_ERROR; - - return 0; + return cse_update_rw(cse_bp_info, target_rdev); } static uint8_t cse_fw_update(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) + const struct region_device *source_info_rdev) { struct region_device target_rdev; @@ -702,9 +726,17 @@ return CSE_LITE_SKU_RW_ACCESS_ERROR; } - if (cse_is_update_required(cse_bp_info, source_rdev, &target_rdev)) { + struct cse_cbfs_rw_info source_info; + + /* Read CSE CBFS RW metadata */ + if (!cse_get_cbfs_rw_metadata(source_info_rdev, &source_info)) { + printk(BIOS_ERR, "cse_lite: Failed to get CSE RW blob metadata\n"); + return CSE_LITE_SKU_UNSPECIFIED; + } + + if (cse_is_update_required(cse_bp_info, &source_info, &target_rdev)) { printk(BIOS_DEBUG, "cse_lite: CSE RW update is initiated\n"); - return cse_trigger_fw_update(cse_bp_info, source_rdev, &target_rdev); + return cse_trigger_fw_update(cse_bp_info, &source_info, &target_rdev); } if (!cse_is_rw_bp_status_valid(cse_bp_info)) @@ -736,11 +768,15 @@ if (!cse_fix_data_failure_err(&cse_bp_info.bp_info)) cse_trigger_recovery(CSE_LITE_SKU_DATA_WIPE_ERROR); - /* If RW blob is present in CBFS, then trigger CSE firmware update */ + /* + * If CSE CBFS RW blob metadata is present in CBFS, then trigger CSE firmware update. + * The driver triggers recovery if CSE CBFS RW metadata is present in the CBFS and CSE + * CBFS RW blob is not available. + */ uint8_t rv; - struct region_device source_rdev; - if (cse_get_cbfs_rdev(&source_rdev)) { - rv = cse_fw_update(&cse_bp_info.bp_info, &source_rdev); + struct region_device source_info_rdev; + if (cse_get_cbfs_rdev(&source_info_rdev)) { + rv = cse_fw_update(&cse_bp_info.bp_info, &source_info_rdev); if (rv) cse_trigger_recovery(rv); } -- To view, visit https://review.coreboot.org/c/coreboot/+/46552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I316344d23987d9907b64efafbe61f36ae7ade337 Gerrit-Change-Number: 46552 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 11

Change in coreboot[master]: sc7180: add qclib_post_fixup to allow SoC specific code
by mturney mturney (Code Review) 11 Nov '20

11 Nov '20

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37795 ) Change subject: sc7180: add qclib_post_fixup to allow SoC specific code ...................................................................... sc7180: add qclib_post_fixup to allow SoC specific code * Provide hook for SoC specific code to run after QCLib Change-Id: I5507187fddfd7d0af0ee0983b06d67077de0dbc8 Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M src/soc/qualcomm/common/include/soc/qclib_common.h M src/soc/qualcomm/common/qclib.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/37795/1 diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h index 19ec083..5817c08 100644 --- a/src/soc/qualcomm/common/include/soc/qclib_common.h +++ b/src/soc/qualcomm/common/include/soc/qclib_common.h @@ -72,5 +72,6 @@ uint32_t size, uint32_t attrs); void qclib_load_and_run(void); int qclib_soc_blob_load(void); +int qclib_post_fixup(void); #endif // _SOC_QUALCOMM_QCLIB_COMMON_H_ diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index ac80a76..ce07078 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -119,6 +119,7 @@ } __weak int qclib_soc_blob_load(void) { return 0; } +__weak int qclib_post_fixup(void) { return 0; } void qclib_load_and_run(void) { @@ -209,6 +210,12 @@ mmu_restore_context(&pre_qclib_mmu_context); mmu_enable(); + /* hook for SoC specific fixup after QCLib runs */ + if (qclib_post_fixup()) { + printk(BIOS_ERR, "qclib_post_fixup failed\n"); + goto fail; + } + /* step through I/F table, handling return values */ for (i = 0; i < qclib_cb_if_table.num_entries; i++) if (qclib_cb_if_table.te[i].blob_attributes & -- To view, visit https://review.coreboot.org/c/coreboot/+/37795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5507187fddfd7d0af0ee0983b06d67077de0dbc8 Gerrit-Change-Number: 37795 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: util/inteltool: add missing special function pads for CNL-LP
by Michael Niewöhner (Code Review) 11 Nov '20

11 Nov '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45201 ) Change subject: util/inteltool: add missing special function pads for CNL-LP ...................................................................... util/inteltool: add missing special function pads for CNL-LP Add the missing special function gpio pad groups for CNL-LP. The groups and names are documented in the PCH EDS, in Linux (linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places. Also, see soc/intel/tigerlake for reference. Change-Id: I0509552da6ffad395c2b89df1676e1903c783695 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45201 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M util/inteltool/gpio_names/cannonlake_lp.h 1 file changed, 166 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved diff --git a/util/inteltool/gpio_names/cannonlake_lp.h b/util/inteltool/gpio_names/cannonlake_lp.h index 27d820c..af14c1f 100644 --- a/util/inteltool/gpio_names/cannonlake_lp.h +++ b/util/inteltool/gpio_names/cannonlake_lp.h @@ -276,7 +276,12 @@ "GPD9", "SLP_WLAN#", "GPD10", "SLP_S5#", "GPD11", "LANPHYPC", + "SLP_LAN_B", "SLP_LAN#", + "SLP_SUS_B", "SLP_SUS#", + "WAKE_B", "WAKE#", + "DRAM_RESET_B", "DRAM_RESET#", }; + const struct gpio_group cannonlake_pch_lp_group_gpd = { .display = "------- GPIO Group GPD -------", .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_gpd_names) / 2, @@ -284,11 +289,156 @@ .pad_names = cannonlake_pch_lp_group_gpd_names, }; +const char *const cannonlake_pch_lp_group_vgpio_names[] = { + "CNV_BTEN", "n/a", "n/a", "n/a", + "CNV_GNEN", "n/a", "n/a", "n/a", + "CNV_WFEN", "n/a", "n/a", "n/a", + "CNV_WCEN", "n/a", "n/a", "n/a", + "CNV_BT_HOST_WAKE_B", "n/a", "n/a", "n/a", + "CNV_BT_IF_SELECT", "n/a", "n/a", "n/a", + "vCNV_BT_UART_TXD", "ISH UART0", "SIo UART2", "n/a", + "vCNV_BT_UART_RXD", "ISH UART0", "SIo UART2", "n/a", + "vCNV_BT_UART_CTS_B", "ISH UART0", "SIo UART2", "n/a", + "vCNV_BT_UART_RTS_B", "ISH UART0", "SIo UART2", "n/a", + "vCNV_MFUART1_TXD", "ISH UART0", "SIo UART2", "n/a", + "vCNV_MFUART1_RXD", "ISH UART0", "SIo UART2", "n/a", + "vCNV_MFUART1_CTS_B", "ISH UART0", "SIo UART2", "n/a", + "vCNV_MFUART1_RTS_B", "ISH UART0", "SIo UART2", "n/a", + "vCNV_GNSS_UART_TXD", "n/a", "n/a", "n/a", + "vCNV_GNSS_UART_RXD", "n/a", "n/a", "n/a", + "vCNV_GNSS_UART_CTS_B", "n/a", "n/a", "n/a", + "vCNV_GNSS_UART_RTS_B", "n/a", "n/a", "n/a", + "vUART0_TXD", "mapped", "n/a", "n/a", + "vUART0_RXD", "mapped", "n/a", "n/a", + "vUART0_CTS_B", "mapped", "n/a", "n/a", + "vUART0_RTS_B", "mapped", "n/a", "n/a", + "vISH_UART0_TXD", "mapped", "n/a", "n/a", + "vISH_UART0_RXD", "mapped", "n/a", "n/a", + "vISH_UART0_CTS_B", "mapped", "n/a", "n/a", + "vISH_UART0_RTS_B", "mapped", "n/a", "n/a", + "vISH_UART1_TXD", "mapped", "n/a", "n/a", + "vISH_UART1_RXD", "mapped", "n/a", "n/a", + "vISH_UART1_CTS_B", "mapped", "n/a", "n/a", + "vISH_UART1_RTS_B", "mapped", "n/a", "n/a", + "vCNV_BT_I2S_BCLK", "SSP0", "SSP1", "SSP2", + "vCNV_BT_I2S_WS_SYNC", "SSP0", "SSP1", "SSP2", + "vCNV_BT_I2S_SDO", "SSP0", "SSP1", "SSP2", + "vCNV_BT_I2S_SDI", "SSP0", "SSP1", "SSP2", + "vSSP2_SCLK", "mapped", "n/a", "n/a", + "vSSP2_SFRM", "mapped", "n/a", "n/a", + "vSSP2_TXD", "mapped", "n/a", "n/a", + "vSSP2_RXD", "n/a", "n/a", "n/a", + "vCNV_GNSS_HOST_WAKE_B", "n/a", "n/a", "n/a", + "vSD3_CD_B", "n/a", "n/a", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_vgpio = { + .display = "------- GPIO Group VGPIO -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_vgpio_names) / 4, + .func_count = 4, + .pad_names = cannonlake_pch_lp_group_vgpio_names, +}; + +const char *const cannonlake_pch_lp_group_spi_names[] = { + "SPI0_IO_2", "SPI0_IO_2", + "SPI0_IO_3", "SPI0_IO_3", + "SPI0_MISO", "SPI0_MISO", + "SPI0_MOSI", "SPI0_MOSI", + "SPI0_CS2_B", "SPI0_CS2#", + "SPI0_CS0_B", "SPI0_CS0#", + "SPI0_CS1_B", "SPI0_CS1#", + "SPI0_CLK", "SPI0_CLK", + "SPI0_CLK_LOOPBK", "SPI0_CLK_LOOPBK", +}; + +const struct gpio_group cannonlake_pch_lp_group_spi = { + .display = "------- GPIO Group SPI -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_spi_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_lp_group_spi_names, +}; + +const char *const cannonlake_pch_lp_group_aza_names[] = { + "HDA_BCLK", "HDA_BCLK", "I2S0_SCLK", "n/a", + "HDA_RST_B", "HDA_RST#", "I2S1_SCLK", "SNDW1_CLK", + "HDA_SYNC", "HDA_SYNC", "I2S0_SFRM", "n/a", + "HDA_SDO", "HDA_SDO", "I2S0_TXD", "n/a", + "HDA_SDI0", "HDA_SDI0", "I2S0_RXD", "n/a", + "HDA_SDI1", "HDA_SDI1", "I2S1_RXD", "SNDW1_DATA", + "I2S1_SFRM", "I2S1_SFRM", "SNDW2_CLK", "n/a", + "I2S1_TXD", "I2S1_TXD", "SNDW2_DATA", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_aza = { + .display = "------- GPIO Group AZA -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_aza_names) / 4, + .func_count = 4, + .pad_names = cannonlake_pch_lp_group_aza_names, +}; + +const char *const cannonlake_pch_lp_group_cpu_names[] = { + "HDACPU_SDI", "HDACPU_SDI", + "HDACPU_SDO", "HDACPU_SDO", + "HDACPU_SCLK", "HDACPU_SCLK", + "PM_SYNC", "PM_SYNC", + "PECI", "PECI", + "CPUPWRGD", "CPUPWRGD", + "THRMTRIP_B", "THRMTRIP#", + "PLTRST_CPU_B", "PLTRST_CPU#", + "PM_DOWN", "PM_DOWN", + "TRIGGER_IN", "TRIGGER_IN", + "TRIGGER_OUT", "TRIGGER_OUT", +}; + +const struct gpio_group cannonlake_pch_lp_group_cpu = { + .display = "------- GPIO Group CPU -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_cpu_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_lp_group_cpu_names, +}; + +const char *const cannonlake_pch_lp_group_jtag_names[] = { + "PCH_TDO", "PCH_TDO", + "PCH_JTAGX", "PCH_JTAGX", + "PROC_PRDY_B", "PROC_PRDY#", + "PROC_PREQ_B", "PROC_PREQ#", + "CPU_TRST_B", "CPU_TRST#", + "PCH_TDI", "PCH_TDI", + "PCH_TMS", "PCH_TMS", + "PCH_TCK", "PCH_TCK", + "ITP_PMODE", "ITP_PMODE", +}; + +const struct gpio_group cannonlake_pch_lp_group_jtag = { + .display = "------- GPIO Group JTAG -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_jtag_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_lp_group_jtag_names, +}; + +const char *const cannonlake_pch_lp_group_hvmos_names[] = { + "EDP_VDDEN", "EDP_VDDEN", + "EDP_BKLTEN", "EDP_BKLTEN", + "EDP_BKLTCTL", "EDP_BKLTCTL", + "SYS_PWROK", "SYS_PWROK", + "SYS_RESET_B", "SYS_RESET#", + "CL_RST_B", "CL_RST#", +}; + +const struct gpio_group cannonlake_pch_lp_group_hvmos = { + .display = "------- GPIO Group HVMOS -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_hvmos_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_lp_group_hvmos_names, +}; + const struct gpio_group *const cannonlake_pch_lp_community_0_groups[] = { &cannonlake_pch_lp_group_a, &cannonlake_pch_lp_group_b, &cannonlake_pch_lp_group_g, + &cannonlake_pch_lp_group_spi, }; + const struct gpio_community cannonlake_pch_lp_community_0 = { .name = "------- GPIO Community 0 -------", .pcr_port_id = 0x6e, @@ -300,6 +450,7 @@ &cannonlake_pch_lp_group_d, &cannonlake_pch_lp_group_f, &cannonlake_pch_lp_group_h, + &cannonlake_pch_lp_group_vgpio, }; const struct gpio_community cannonlake_pch_lp_community_1 = { .name = "------- GPIO Community 1 -------", @@ -319,9 +470,23 @@ .groups = cannonlake_pch_lp_community_2_groups, }; +const struct gpio_group *const cannonlake_pch_lp_community_3_groups[] = { + &cannonlake_pch_lp_group_aza, + &cannonlake_pch_lp_group_cpu, +}; + +const struct gpio_community cannonlake_pch_lp_community_3 = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0x6b, + .group_count = ARRAY_SIZE(cannonlake_pch_lp_community_3_groups), + .groups = cannonlake_pch_lp_community_3_groups, +}; + const struct gpio_group *const cannonlake_pch_lp_community_4_groups[] = { &cannonlake_pch_lp_group_c, &cannonlake_pch_lp_group_e, + &cannonlake_pch_lp_group_jtag, + &cannonlake_pch_lp_group_hvmos, }; const struct gpio_community cannonlake_pch_lp_community_4 = { @@ -335,6 +500,7 @@ &cannonlake_pch_lp_community_0, &cannonlake_pch_lp_community_1, &cannonlake_pch_lp_community_2, + &cannonlake_pch_lp_community_3, &cannonlake_pch_lp_community_4, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/45201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0509552da6ffad395c2b89df1676e1903c783695 Gerrit-Change-Number: 45201 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/inteltool: add missing special function pads for CNL-LP
by Michael Niewöhner (Code Review) 11 Nov '20

11 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45201 ) Change subject: util/inteltool: add missing special function pads for CNL-LP ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/45201/2/util/inteltool/gpio_names/… File util/inteltool/gpio_names/cannonlake_lp.h: https://review.coreboot.org/c/coreboot/+/45201/2/util/inteltool/gpio_names/… PS2, Line 311: "vUART0_TXD", "mapped", "n/a", "n/a", : "vUART0_RXD", "mapped", "n/a", "n/a", : "vUART0_CTS_B", "mapped", "n/a", "n/a", : "vUART0_RTS_B", "mapped", "n/a", "n/a", : "vISH_UART0_TXD", "mapped", "n/a", "n/a", : "vISH_UART0_RXD", "mapped", "n/a", "n/a", : "vISH_UART0_CTS_B", "mapped", "n/a", "n/a", : "vISH_UART0_RTS_B", "mapped", "n/a", "n/a", : "vISH_UART1_TXD", "mapped", "n/a", "n/a", : "vISH_UART1_RXD", "mapped", "n/a", "n/a", : "vISH_UART1_CTS_B", "mapped", "n/a", "n/a", : "vISH_UART1_RTS_B", "mapped", "n/a", "n/a", : "vCNV_BT_I2S_BCLK", "SSP0", "SSP1", "SSP2", : "vCNV_BT_I2S_WS_SYNC", "SSP0", "SSP1", "SSP2", : "vCNV_BT_I2S_SDO", "SSP0", "SSP1", "SSP2", : "vCNV_BT_I2S_SDI", "SSP0", "SSP1", "SSP2", : "vSSP2_SCLK", "mapped", "n/a", "n/a", : "vSSP2_SFRM", "mapped", "n/a", "n/a", : "vSSP2_TXD", "mapped", "n/a", "n/a", : "vSSP2_RXD", "n/a", "n/a", "n/a", : "vCNV_GNSS_HOST_WAKEB", "n/a", "n/a", "n/a", : "vSD3_CD_B", "n/a", "n/a", "n/a", > this needs further investigation; it seems, they use vGPIOs as mux switches o. […] will be done in a follow-up later. for dumping the register values it's not that important for now -- To view, visit https://review.coreboot.org/c/coreboot/+/45201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0509552da6ffad395c2b89df1676e1903c783695 Gerrit-Change-Number: 45201 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 11 Nov 2020 12:32:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: util/inteltool: add missing special function pads for CNL-H
by Michael Niewöhner (Code Review) 11 Nov '20

11 Nov '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45204 ) Change subject: util/inteltool: add missing special function pads for CNL-H ...................................................................... util/inteltool: add missing special function pads for CNL-H Add the missing special function gpio pad groups for CNL-H. The groups and names are documented in the PCH EDS, in Linux (linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places. Also, see soc/intel/tigerlake for reference. Change-Id: Ib83aeef9f4b6aa174e61ccbd87fb7b6450ed773b Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45204 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M util/inteltool/gpio_names/cannonlake.h 1 file changed, 46 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved diff --git a/util/inteltool/gpio_names/cannonlake.h b/util/inteltool/gpio_names/cannonlake.h index 47672d5..694b158 100644 --- a/util/inteltool/gpio_names/cannonlake.h +++ b/util/inteltool/gpio_names/cannonlake.h @@ -264,6 +264,32 @@ "GPP_H23", "TIME_SYNC0", }; +const char *const cannonlake_pch_h_group_cpu_names[] = { + "HDACPU_SDI", "HDACPU_SDI", + "HDACPU_SDO", "HDACPU_SDO", + "HDACPU_SCLK", "HDACPU_SCLK", + "PM_SYNC", "PM_SYNC", + "PECI", "PECI", + "CPUPWRGD", "CPUPWRG#", + "THRMTRIP_B", "THRMTRIP#", + "PLTRST_CPU_B", "PLTRST_CPU#", + "PM_DOWN", "PM_DOWN", + "TRIGGER_IN", "TRIGGER_IN", + "TRIGGER_OUT", "TRIGGER_OUT", +}; + +const char *const cannonlake_pch_h_group_jtag_names[] = { + "PCH_TDO", "PCH_TDO", + "PCH_JTAGX", "PCH_JTAGX", + "PROC_PRDY_B", "PROC_RDY#", + "PROC_PREQ_B", "PROC_REQ#", + "CPU_TRST_B", "CPU_TRST#", + "PCH_TDI", "PCH_TDI", + "PCH_TMS", "PCH_TMS", + "PCH_TCK", "PCH_TCK", + "ITP_PMODE", "ITP_PMODE", +}; + static const char *const cannonlake_pch_h_group_i_names[] = { "GPP_I0", "DDPB_HPD0", "DISP_MISC0", "GPP_I1", "DDPB_HPD1", "DISP_MISC1", @@ -340,6 +366,10 @@ "GPD9", "SLP_WLAN#", "GPD10", "SLP_S5#", "GPD11", "LANPHYPC", + "SLP_LAN_B", "SLP_LAN#", + "SLP_SUS_B", "SLP_SUS#", + "WAKE_B", "WAKE#", + "DRAM_RESET_B", "DRAM_RESET#", }; static const struct gpio_group cannonlake_pch_h_group_a = { @@ -426,6 +456,20 @@ .pad_names = cannonlake_pch_h_group_h_names, }; +static const struct gpio_group cannonlake_pch_h_group_cpu = { + .display = "------- GPIO Group CPU -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_cpu_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_h_group_cpu_names, +}; + +static const struct gpio_group cannonlake_pch_h_group_jtag = { + .display = "------- GPIO Group JTAG -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_jtag_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_h_group_jtag_names, +}; + static const struct gpio_group cannonlake_pch_h_group_i = { .display = "------- GPIO Group GPP_I -------", .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_i_names) / 3, @@ -505,6 +549,8 @@ }; static const struct gpio_group *const cannonlake_pch_h_community_4_groups[] = { + &cannonlake_pch_h_group_cpu, + &cannonlake_pch_h_group_jtag, &cannonlake_pch_h_group_i, &cannonlake_pch_h_group_j, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/45204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib83aeef9f4b6aa174e61ccbd87fb7b6450ed773b Gerrit-Change-Number: 45204 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: util/inteltool: add missing native functions of special pads for CNL-H
by Michael Niewöhner (Code Review) 11 Nov '20

11 Nov '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45203 ) Change subject: util/inteltool: add missing native functions of special pads for CNL-H ...................................................................... util/inteltool: add missing native functions of special pads for CNL-H Add the missing native functions for special gpio pads for CNL-H, which are documented in the PCH EDS and other places. Also, see soc/intel/tigerlake for reference. Change-Id: I71339d66362d29806c91375c214e9fb84c989201 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45203 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M util/inteltool/gpio_names/cannonlake.h 1 file changed, 68 insertions(+), 68 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved diff --git a/util/inteltool/gpio_names/cannonlake.h b/util/inteltool/gpio_names/cannonlake.h index 0743936..47672d5 100644 --- a/util/inteltool/gpio_names/cannonlake.h +++ b/util/inteltool/gpio_names/cannonlake.h @@ -158,15 +158,15 @@ }; static const char *const cannonlake_pch_h_group_spi_names[] = { - "SPI0_IO_2", - "SPI0_IO_3", - "SPI0_MISO", - "SPI0_MOSI", - "SPI0_CS2_B", - "SPI0_CS0_B", - "SPI0_CS1_B", - "SPI0_CLK", - "SPI0_CLK_LOOPBK", + "SPI0_IO_2", "SPI0_IO_2", + "SPI0_IO_3", "SPI0_IO_3", + "SPI0_MISO", "SPI0_MISO", + "SPI0_MOSI", "SPI0_MOSI", + "SPI0_CS2_B", "SPI0_CS2#", + "SPI0_CS0_B", "SPI0_CS0#", + "SPI0_CS1_B", "SPI0_CS1#", + "SPI0_CLK", "SPI0_CLK", + "SPI0_CLK_LOOPBK", "SPI0_CLK_LOOPBK", }; static const char *const cannonlake_pch_h_group_g_names[] = { @@ -181,60 +181,60 @@ }; static const char *const cannonlake_pch_h_group_aza_names[] = { - "HDA_BCLK", - "HDA_RST_B", - "HDA_SYNC", - "HDA_SDO", - "HDA_SDI_0", - "HDA_SDI_1", - "I2S1_SFRM", - "I2S1_TXD", + "HDA_BCLK", "HDA_BCLK", "I2S0_SCLK", "n/a", + "HDA_RST_B", "HDA_RST#", "I2S1_SCLK", "SNDW1_CLK", + "HDA_SYNC", "HDA_SYNC", "I2S0_SFRM", "n/a", + "HDA_SDO", "HDA_SDO", "I2S0_TXD", "n/a", + "HDA_SDI0", "HDA_SDI0", "I2S0_RXD", "n/a", + "HDA_SDI1", "HDA_SDI1", "I2S1_RXD", "SNDW1_DATA", + "I2S1_SFRM", "I2S1_SFRM", "SNDW2_CLK", "n/a", + "I2S1_TXD", "I2S1_TXD", "SNDW2_DATA", "n/a", }; static const char *const cannonlake_pch_h_group_vgpio_0_names[] = { - "CNV_BTEN", - "CNV_GNEN", - "CNV_WFEN", - "CNV_WCEN", - "CNV_BT_HOST_WAKE_B", - "vCNV_GNSS_HOST_WAKE_B", - "vSD3_CD_B", - "CNV_BT_IF_SELECT", - "vCNV_BT_UART_TXD", - "vCNV_BT_UART_RXD", - "vCNV_BT_UART_CTS_B", - "vCNV_BT_UART_RTS_B", - "vCNV_MFUART1_TXD", - "vCNV_MFUART1_RXD", - "vCNV_MFUART1_CTS_B", - "vCNV_MFUART1_RTS_B", - "vCNV_GNSS_UART_TXD", - "vCNV_GNSS_UART_RXD", - "vCNV_GNSS_UART_CTS_B", - "vCNV_GNSS_UART_RTS_B", - "vUART0_TXD", - "vUART0_RXD", - "vUART0_CTS_B", - "vUART0_RTS_B", - "vISH_UART0_TXD", - "vISH_UART0_RXD", - "vISH_UART0_CTS_B", - "vISH_UART0_RTS_B", - "vISH_UART1_TXD", - "vISH_UART1_RXD", - "vISH_UART1_CTS_B", - "vISH_UART1_RTS_B", + "CNV_BTEN", "n/a", "n/a", "n/a", + "CNV_GNEN", "n/a", "n/a", "n/a", + "CNV_WFEN", "n/a", "n/a", "n/a", + "CNV_WCEN", "n/a", "n/a", "n/a", + "vCNV_GNSS_HOST_WAKE_B", "n/a", "n/a", "n/a", + "vSD3_CD_B", "n/a", "n/a", "n/a", + "CNV_BT_HOST_WAKE_B", "n/a", "n/a", "n/a", + "CNV_BT_IF_SELECT", "n/a", "n/a", "n/a", + "vCNV_BT_UART_TXD", "ISH UART0", "SIo UART2", "n/a", + "vCNV_BT_UART_RXD", "ISH UART0", "SIo UART2", "n/a", + "vCNV_BT_UART_CTS_B", "ISH UART0", "SIo UART2", "n/a", + "vCNV_BT_UART_RTS_B", "ISH UART0", "SIo UART2", "n/a", + "vCNV_MFUART1_TXD", "ISH UART0", "SIo UART2", "n/a", + "vCNV_MFUART1_RXD", "ISH UART0", "SIo UART2", "n/a", + "vCNV_MFUART1_CTS_B", "ISH UART0", "SIo UART2", "n/a", + "vCNV_MFUART1_RTS_B", "ISH UART0", "SIo UART2", "n/a", + "vCNV_GNSS_UART_TXD", "n/a", "n/a", "n/a", + "vCNV_GNSS_UART_RXD", "n/a", "n/a", "n/a", + "vCNV_GNSS_UART_CTS_B", "n/a", "n/a", "n/a", + "vCNV_GNSS_UART_RTS_B", "n/a", "n/a", "n/a", + "vUART0_TXD", "mapped", "n/a", "n/a", + "vUART0_RXD", "mapped", "n/a", "n/a", + "vUART0_CTS_B", "mapped", "n/a", "n/a", + "vUART0_RTS_B", "mapped", "n/a", "n/a", + "vISH_UART0_TXD", "mapped", "n/a", "n/a", + "vISH_UART0_RXD", "mapped", "n/a", "n/a", + "vISH_UART0_CTS_B", "mapped", "n/a", "n/a", + "vISH_UART0_RTS_B", "mapped", "n/a", "n/a", + "vISH_UART1_TXD", "mapped", "n/a", "n/a", + "vISH_UART1_RXD", "mapped", "n/a", "n/a", + "vISH_UART1_CTS_B", "mapped", "n/a", "n/a", + "vISH_UART1_RTS_B", "mapped", "n/a", "n/a", }; static const char *const cannonlake_pch_h_group_vgpio_1_names[] = { - "vCNV_BT_I2S_BCLK", - "vCNV_BT_I2S_WS_SYNC", - "vCNV_BT_I2S_SDO", - "vCNV_BT_I2S_SDI", - "vSSP2_SCLK", - "vSSP2_SFRM", - "vSSP2_TXD", - "vSSP2_RXD", + "vCNV_BT_I2S_BCLK", "SSP0", "SSP1", "SSP2", + "vCNV_BT_I2S_WS_SYNC", "SSP0", "SSP1", "SSP2", + "vCNV_BT_I2S_SDO", "SSP0", "SSP1", "SSP2", + "vCNV_BT_I2S_SDI", "SSP0", "SSP1", "SSP2", + "vSSP2_SCLK", "mapped", "n/a", "n/a", + "vSSP2_SFRM", "mapped", "n/a", "n/a", + "vSSP2_TXD", "mapped", "n/a", "n/a", + "vSSP2_RXD", "n/a", "n/a", "n/a", }; static const char *const cannonlake_pch_h_group_h_names[] = { @@ -280,9 +280,9 @@ "GPP_I12", "M2_SKT2_CFG1", "n/a", "GPP_I13", "M2_SKT2_CFG2", "n/a", "GPP_I14", "M2_SKT2_CFG3", "n/a", - "SYS_PWROK", "n/a", "n/a", - "SYS_RESET_B", "n/a", "n/a", - "CL_RST_B", "n/a", "n/a", + "SYS_PWROK", "SYS_PWROK", "n/a", + "SYS_RESET_B", "SYS_RESET#", "n/a", + "CL_RST_B", "CL_RST#", "n/a", }; static const char *const cannonlake_pch_h_group_j_names[] = { @@ -386,8 +386,8 @@ static const struct gpio_group cannonlake_pch_h_group_spi = { .display = "------- GPIO Group SPI -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_spi_names) / 1, - .func_count = 1, + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_spi_names) / 2, + .func_count = 2, .pad_names = cannonlake_pch_h_group_spi_names, }; @@ -400,22 +400,22 @@ static const struct gpio_group cannonlake_pch_h_group_aza = { .display = "------- GPIO Group AZA -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_aza_names) / 1, - .func_count = 1, + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_aza_names) / 4, + .func_count = 4, .pad_names = cannonlake_pch_h_group_aza_names, }; static const struct gpio_group cannonlake_pch_h_group_vgpio_0 = { .display = "------- GPIO Group VGPIO_0 -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_vgpio_0_names) / 1, - .func_count = 1, + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_vgpio_0_names) / 4, + .func_count = 4, .pad_names = cannonlake_pch_h_group_vgpio_0_names, }; static const struct gpio_group cannonlake_pch_h_group_vgpio_1 = { .display = "------- GPIO Group VGPIO_1 -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_vgpio_1_names) / 1, - .func_count = 1, + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_vgpio_1_names) / 4, + .func_count = 4, .pad_names = cannonlake_pch_h_group_vgpio_1_names, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/45203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71339d66362d29806c91375c214e9fb84c989201 Gerrit-Change-Number: 45203 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: util/inteltool: rename GPIO_RSVD_* to their correct names for CNL-H
by Michael Niewöhner (Code Review) 11 Nov '20

11 Nov '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45202 ) Change subject: util/inteltool: rename GPIO_RSVD_* to their correct names for CNL-H ...................................................................... util/inteltool: rename GPIO_RSVD_* to their correct names for CNL-H The names of the GPIO_RSVD_* are documented in the PCH EDS, in Linux (linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places. Also, see soc/intel/tigerlake for reference. Change-Id: Ifd6cabb646000c8dff695c5c4f7196b2779f1430 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45202 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M util/inteltool/gpio_names/cannonlake.h 1 file changed, 75 insertions(+), 75 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved diff --git a/util/inteltool/gpio_names/cannonlake.h b/util/inteltool/gpio_names/cannonlake.h index 305a1c3..0743936 100644 --- a/util/inteltool/gpio_names/cannonlake.h +++ b/util/inteltool/gpio_names/cannonlake.h @@ -4,60 +4,60 @@ #include "gpio_groups.h" static const char *const cannonlake_pch_h_group_a_names[] = { - "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", - "GPP_A1", "LAD0", "n/a", "ESPI_IO0", - "GPP_A2", "LAD1", "n/a", "ESPI_IO1", - "GPP_A3", "LAD2", "n/a", "ESPI_IO2", - "GPP_A4", "LAD3", "n/a", "ESPI_IO3", - "GPP_A5", "LFRAME#", "n/a", "ESPI_CS0#", - "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", - "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", - "GPP_A8", "CLKRUN#", "n/a", "n/a", - "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", - "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", - "GPP_A11", "PME#", "SD_VDD2_PWR_EN#", "n/a", - "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", - "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", - "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", - "GPP_A15", "SUSACK#", "n/a", "n/a", - "GPP_A16", "CLKOUT_48", "n/a", "n/a", - "GPP_A17", "SD_VDD1_PWR_EN#", "ISH_GP7", "n/a", - "GPP_A18", "ISH_GP0", "n/a", "n/a", - "GPP_A19", "ISH_GP1", "n/a", "n/a", - "GPP_A20", "ISH_GP2", "n/a", "n/a", - "GPP_A21", "ISH_GP3", "n/a", "n/a", - "GPP_A22", "ISH_GP4", "n/a", "n/a", - "GPP_A23", "ISH_GP5", "n/a", "n/a", - "GPIO_RSVD_0", "n/a", "n/a", "n/a", + "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", + "GPP_A1", "LAD0", "n/a", "ESPI_IO0", + "GPP_A2", "LAD1", "n/a", "ESPI_IO1", + "GPP_A3", "LAD2", "n/a", "ESPI_IO2", + "GPP_A4", "LAD3", "n/a", "ESPI_IO3", + "GPP_A5", "LFRAME#", "n/a", "ESPI_CS0#", + "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", + "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "SD_VDD2_PWR_EN#", "n/a", + "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", + "GPP_A15", "SUSACK#", "n/a", "n/a", + "GPP_A16", "CLKOUT_48", "n/a", "n/a", + "GPP_A17", "SD_VDD1_PWR_EN#", "ISH_GP7", "n/a", + "GPP_A18", "ISH_GP0", "n/a", "n/a", + "GPP_A19", "ISH_GP1", "n/a", "n/a", + "GPP_A20", "ISH_GP2", "n/a", "n/a", + "GPP_A21", "ISH_GP3", "n/a", "n/a", + "GPP_A22", "ISH_GP4", "n/a", "n/a", + "GPP_A23", "ISH_GP5", "n/a", "n/a", + "ESPI_CLK_LOOPBK", "ESPI_CLK_LOOPBK", "n/a", "n/a", }; static const char *const cannonlake_pch_h_group_b_names[] = { - "GPP_B0", "GSPI0_CS1#", "n/a", - "GPP_B1", "GSPI1_CS1#", "TIME_SYNC1", - "GPP_B2", "VRALERT#", "n/a", - "GPP_B3", "CPU_GP2", "n/a", - "GPP_B4", "CPU_GP3", "n/a", - "GPP_B5", "SRCCLKREQ0#", "n/a", - "GPP_B6", "SRCCLKREQ1#", "n/a", - "GPP_B7", "SRCCLKREQ2#", "n/a", - "GPP_B8", "SRCCLKREQ3#", "n/a", - "GPP_B9", "SRCCLKREQ4#", "n/a", - "GPP_B10", "SRCCLKREQ5#", "n/a", - "GPP_B11", "I2S_MCLK", "n/a", - "GPP_B12", "SLP_S0#", "n/a", - "GPP_B13", "PLTRST#", "n/a", - "GPP_B14", "SPKR", "n/a", - "GPP_B15", "GSPI0_CS0#", "n/a", - "GPP_B16", "GSPI0_CLK", "n/a", - "GPP_B17", "GSPI0_MISO", "n/a", - "GPP_B18", "GSPI0_MOSI", "n/a", - "GPP_B19", "GSPI1_CS0#", "n/a", - "GPP_B20", "GSPI1_CLK", "n/a", - "GPP_B21", "GSPI1_MISO", "n/a", - "GPP_B22", "GSPI1_MOSI", "n/a", - "GPP_B23", "SML1ALERT#", "PCHHOT#", - "GPIO_RSVD_1", "n/a", "n/a", - "GPIO_RSVD_2", "n/a", "n/a", + "GPP_B0", "GSPI0_CS1#", "n/a", + "GPP_B1", "GSPI1_CS1#", "TIME_SYNC1", + "GPP_B2", "VRALERT#", "n/a", + "GPP_B3", "CPU_GP2", "n/a", + "GPP_B4", "CPU_GP3", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", + "GPP_B11", "I2S_MCLK", "n/a", + "GPP_B12", "SLP_S0#", "n/a", + "GPP_B13", "PLTRST#", "n/a", + "GPP_B14", "SPKR", "n/a", + "GPP_B15", "GSPI0_CS0#", "n/a", + "GPP_B16", "GSPI0_CLK", "n/a", + "GPP_B17", "GSPI0_MISO", "n/a", + "GPP_B18", "GSPI0_MOSI", "n/a", + "GPP_B19", "GSPI1_CS0#", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", + "GSPI0_CLK_LOOPBK", "GSPI0_CLK_LOOPBK", "n/a", + "GSPI1_CLK_LOOPBK", "GSPI1_CLK_LOOPBK", "n/a", }; static const char *const cannonlake_pch_h_group_c_names[] = { @@ -158,15 +158,15 @@ }; static const char *const cannonlake_pch_h_group_spi_names[] = { - "GPIO_RSVD_11", - "GPIO_RSVD_12", - "GPIO_RSVD_13", - "GPIO_RSVD_14", - "GPIO_RSVD_15", - "GPIO_RSVD_16", - "GPIO_RSVD_17", - "GPIO_RSVD_18", - "GPIO_RSVD_19", + "SPI0_IO_2", + "SPI0_IO_3", + "SPI0_MISO", + "SPI0_MOSI", + "SPI0_CS2_B", + "SPI0_CS0_B", + "SPI0_CS1_B", + "SPI0_CLK", + "SPI0_CLK_LOOPBK", }; static const char *const cannonlake_pch_h_group_g_names[] = { @@ -181,14 +181,14 @@ }; static const char *const cannonlake_pch_h_group_aza_names[] = { - "GPIO_RSVD_3", - "GPIO_RSVD_4", - "GPIO_RSVD_5", - "GPIO_RSVD_6", - "GPIO_RSVD_7", - "GPIO_RSVD_8", - "GPIO_RSVD_9", - "GPIO_RSVD_10", + "HDA_BCLK", + "HDA_RST_B", + "HDA_SYNC", + "HDA_SDO", + "HDA_SDI_0", + "HDA_SDI_1", + "I2S1_SFRM", + "I2S1_TXD", }; static const char *const cannonlake_pch_h_group_vgpio_0_names[] = { @@ -196,8 +196,8 @@ "CNV_GNEN", "CNV_WFEN", "CNV_WCEN", - "CNV_BT_HOST_WAKEB", - "vCNV_GNSS_HOST_WAKEB", + "CNV_BT_HOST_WAKE_B", + "vCNV_GNSS_HOST_WAKE_B", "vSD3_CD_B", "CNV_BT_IF_SELECT", "vCNV_BT_UART_TXD", @@ -215,11 +215,11 @@ "vUART0_TXD", "vUART0_RXD", "vUART0_CTS_B", - "vUART0_RTSB", + "vUART0_RTS_B", "vISH_UART0_TXD", "vISH_UART0_RXD", "vISH_UART0_CTS_B", - "vISH_UART0_RTSB", + "vISH_UART0_RTS_B", "vISH_UART1_TXD", "vISH_UART1_RXD", "vISH_UART1_CTS_B", @@ -280,9 +280,9 @@ "GPP_I12", "M2_SKT2_CFG1", "n/a", "GPP_I13", "M2_SKT2_CFG2", "n/a", "GPP_I14", "M2_SKT2_CFG3", "n/a", - "GPIO_RSVD_40", "n/a", "n/a", - "GPIO_RSVD_41", "n/a", "n/a", - "GPIO_RSVD_42", "n/a", "n/a", + "SYS_PWROK", "n/a", "n/a", + "SYS_RESET_B", "n/a", "n/a", + "CL_RST_B", "n/a", "n/a", }; static const char *const cannonlake_pch_h_group_j_names[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/45202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd6cabb646000c8dff695c5c4f7196b2779f1430 Gerrit-Change-Number: 45202 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/inteltool: add missing native functions of special pads for CNL-LP
by Michael Niewöhner (Code Review) 11 Nov '20

11 Nov '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45305 ) Change subject: util/inteltool: add missing native functions of special pads for CNL-LP ...................................................................... util/inteltool: add missing native functions of special pads for CNL-LP Add the missing native functions for special gpio pads for CNL-LP, which are documented in the PCH EDS and other places. Also, see soc/intel/tigerlake for reference. Change-Id: Iedb726aa3afdbbbedafb67f6b7668bf591c2b9b4 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45305 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M util/inteltool/gpio_names/cannonlake_lp.h 1 file changed, 26 insertions(+), 26 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved diff --git a/util/inteltool/gpio_names/cannonlake_lp.h b/util/inteltool/gpio_names/cannonlake_lp.h index 9d9c66b..27d820c 100644 --- a/util/inteltool/gpio_names/cannonlake_lp.h +++ b/util/inteltool/gpio_names/cannonlake_lp.h @@ -75,36 +75,36 @@ }; const char *const cannonlake_pch_lp_group_c_names[] = { - "GPP_C0", "SMBCLK", "n/a", - "GPP_C1", "SMBDATA", "n/a", - "GPP_C2", "SMBALERT#", "n/a", - "GPP_C3", "SML0CLK", "n/a", - "GPP_C4", "SML0DATA", "n/a", - "GPP_C5", "SML0ALERT#", "n/a", - "GPP_C6", "SML1CLK", "n/a", - "GPP_C7", "SML1DATA", "n/a", - "GPP_C8", "UART0_RXD", "n/a", - "GPP_C9", "UART0_TXD", "n/a", - "GPP_C10", "UART0_RTS#", "n/a", - "GPP_C11", "UART0_CTS#", "n/a", - "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", - "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", - "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", - "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", - "GPP_C16", "I2C0_SDA", "n/a", - "GPP_C17", "I2C0_SCL", "n/a", - "GPP_C18", "I2C1_SDA", "n/a", - "GPP_C19", "I2C1_SCL", "n/a", - "GPP_C20", "UART2_RXD", "n/a", - "GPP_C21", "UART2_TXD", "n/a", - "GPP_C22", "UART2_RTS#", "n/a", - "GPP_C23", "UART2_CTS#", "n/a", + "GPP_C0", "SMBCLK", "n/a", "n/a", + "GPP_C1", "SMBDATA", "n/a", "n/a", + "GPP_C2", "SMBALERT#", "n/a", "n/a", + "GPP_C3", "SML0CLK", "n/a", "n/a", + "GPP_C4", "SML0DATA", "n/a", "n/a", + "GPP_C5", "SML0ALERT#", "n/a", "n/a", + "GPP_C6", "SML1CLK", "n/a", "n/a", + "GPP_C7", "SML1DATA", "n/a", "n/a", + "GPP_C8", "UART0_RXD", "n/a", "n/a", + "GPP_C9", "UART0_TXD", "n/a", "n/a", + "GPP_C10", "UART0_RTS#", "n/a", "n/a", + "GPP_C11", "UART0_CTS#", "n/a", "n/a", + "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "CNV_MFUART1_RXD", + "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "CNV_MFUART1_TXD", + "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "CNV_MFUART1_RTS", + "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "CNV_MFUART1_CTS", + "GPP_C16", "I2C0_SDA", "n/a", "n/a", + "GPP_C17", "I2C0_SCL", "n/a", "n/a", + "GPP_C18", "I2C1_SDA", "n/a", "n/a", + "GPP_C19", "I2C1_SCL", "n/a", "n/a", + "GPP_C20", "UART2_RXD", "n/a", "n/a", + "GPP_C21", "UART2_TXD", "n/a", "n/a", + "GPP_C22", "UART2_RTS#", "n/a", "n/a", + "GPP_C23", "UART2_CTS#", "n/a", "n/a", }; const struct gpio_group cannonlake_pch_lp_group_c = { .display = "------- GPIO Group GPP_C -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_c_names) / 3, - .func_count = 3, + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_c_names) / 4, + .func_count = 4, .pad_names = cannonlake_pch_lp_group_c_names, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/45305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedb726aa3afdbbbedafb67f6b7668bf591c2b9b4 Gerrit-Change-Number: 45305 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/inteltool: rename GPIO_RSVD_* to their correct names for CNL-LP
by Michael Niewöhner (Code Review) 11 Nov '20

11 Nov '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45200 ) Change subject: util/inteltool: rename GPIO_RSVD_* to their correct names for CNL-LP ...................................................................... util/inteltool: rename GPIO_RSVD_* to their correct names for CNL-LP The names of the GPIO_RSVD_* are documented in the PCH EDS, in Linux (linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places. Also, see soc/intel/tigerlake for reference. Change-Id: I86c7159d9f48560c41efdfe49f162aef00499d13 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45200 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M util/inteltool/gpio_names/cannonlake_lp.h 1 file changed, 76 insertions(+), 76 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved diff --git a/util/inteltool/gpio_names/cannonlake_lp.h b/util/inteltool/gpio_names/cannonlake_lp.h index 0aa69b0..9d9c66b 100644 --- a/util/inteltool/gpio_names/cannonlake_lp.h +++ b/util/inteltool/gpio_names/cannonlake_lp.h @@ -4,31 +4,31 @@ #include "gpio_groups.h" const char *const cannonlake_pch_lp_group_a_names[] = { - "GPP_A0", "RCIN#", "TIME_SYNC1", "n/a", - "GPP_A1", "LAD0", "ESPI_IO0", "n/a", - "GPP_A2", "LAD1", "ESPI_IO1", "n/a", - "GPP_A3", "LAD2", "ESPI_IO2", "n/a", - "GPP_A4", "LAD3", "ESPI_IO3", "n/a", - "GPP_A5", "LFRAME#", "ESPI_CS0#", "n/a", - "GPP_A6", "SERIRQ", "n/a", "n/a", - "GPP_A7", "PIRQA#", "GSPI0_CS1#", "n/a", - "GPP_A8", "CLKRUN#", "n/a", "n/a", - "GPP_A9", "CLKOUT_LPC0", "ESPI_CLK", "n/a", - "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", - "GPP_A11", "PME#", "GSPI1_CS1#", "SD_VDD2_PWR_EN#", - "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", - "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", - "GPP_A14", "SUS_STAT#", "ESPI_RESET#", "n/a", - "GPP_A15", "SUSACK#", "n/a", "n/a", - "GPP_A16", "SD_1P8_SEL", "n/a", "n/a", - "GPP_A17", "SD_VDD1_PWR_EN#", "ISH_GP7", "n/a", - "GPP_A18", "ISH_GP0", "n/a", "n/a", - "GPP_A19", "ISH_GP1", "n/a", "n/a", - "GPP_A20", "ISH_GP2", "n/a", "n/a", - "GPP_A21", "ISH_GP3", "n/a", "n/a", - "GPP_A22", "ISH_GP4", "n/a", "n/a", - "GPP_A23", "ISH_GP5", "n/a", "n/a", - "GPIO_RSVD_0", "n/a", "n/a", "n/a", + "GPP_A0", "RCIN#", "TIME_SYNC1", "n/a", + "GPP_A1", "LAD0", "ESPI_IO0", "n/a", + "GPP_A2", "LAD1", "ESPI_IO1", "n/a", + "GPP_A3", "LAD2", "ESPI_IO2", "n/a", + "GPP_A4", "LAD3", "ESPI_IO3", "n/a", + "GPP_A5", "LFRAME#", "ESPI_CS0#", "n/a", + "GPP_A6", "SERIRQ", "n/a", "n/a", + "GPP_A7", "PIRQA#", "GSPI0_CS1#", "n/a", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "ESPI_CLK", "n/a", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "GSPI1_CS1#", "SD_VDD2_PWR_EN#", + "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "SUS_STAT#", "ESPI_RESET#", "n/a", + "GPP_A15", "SUSACK#", "n/a", "n/a", + "GPP_A16", "SD_1P8_SEL", "n/a", "n/a", + "GPP_A17", "SD_VDD1_PWR_EN#", "ISH_GP7", "n/a", + "GPP_A18", "ISH_GP0", "n/a", "n/a", + "GPP_A19", "ISH_GP1", "n/a", "n/a", + "GPP_A20", "ISH_GP2", "n/a", "n/a", + "GPP_A21", "ISH_GP3", "n/a", "n/a", + "GPP_A22", "ISH_GP4", "n/a", "n/a", + "GPP_A23", "ISH_GP5", "n/a", "n/a", + "ESPI_CLK_LOOPBK", "ESPI_CLK_LOOPBK", "n/a", "n/a", }; const struct gpio_group cannonlake_pch_lp_group_a = { @@ -39,32 +39,32 @@ }; const char *const cannonlake_pch_lp_group_b_names[] = { - "GPP_B0", "Reserved", "n/a", - "GPP_B1", "Reserved", "n/a", - "GPP_B2", "VRALERT#", "n/a", - "GPP_B3", "CPU_GP2", "n/a", - "GPP_B4", "CPU_GP3", "n/a", - "GPP_B5", "SRCCLKREQ0#", "n/a", - "GPP_B6", "SRCCLKREQ1#", "n/a", - "GPP_B7", "SRCCLKREQ2#", "n/a", - "GPP_B8", "SRCCLKREQ3#", "n/a", - "GPP_B9", "SRCCLKREQ4#", "n/a", - "GPP_B10", "SRCCLKREQ5#", "n/a", - "GPP_B11", "EXT_PWR_GATE#", "n/a", - "GPP_B12", "SLP_S0#", "n/a", - "GPP_B13", "PLTRST#", "n/a", - "GPP_B14", "SPKR", "n/a", - "GPP_B15", "GSPI0_CS0#", "n/a", - "GPP_B16", "GSPI0_CLK", "n/a", - "GPP_B17", "GSPI0_MISO", "n/a", - "GPP_B18", "GSPI0_MOSI", "n/a", - "GPP_B19", "GSPI1_CS0#", "n/a", - "GPP_B20", "GSPI1_CLK", "n/a", - "GPP_B21", "GSPI1_MISO", "n/a", - "GPP_B22", "GSPI1_MOSI", "n/a", - "GPP_B23", "SML1ALERT#", "PCHHOT#", - "GPIO_RSVD_1", "n/a", "n/a", - "GPIO_RSVD_2", "n/a", "n/a", + "GPP_B0", "CORE_VID0", "n/a", + "GPP_B1", "CORE_VID1", "n/a", + "GPP_B2", "VRALERT#", "n/a", + "GPP_B3", "CPU_GP2", "n/a", + "GPP_B4", "CPU_GP3", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", + "GPP_B11", "EXT_PWR_GATE#", "n/a", + "GPP_B12", "SLP_S0#", "n/a", + "GPP_B13", "PLTRST#", "n/a", + "GPP_B14", "SPKR", "n/a", + "GPP_B15", "GSPI0_CS0#", "n/a", + "GPP_B16", "GSPI0_CLK", "n/a", + "GPP_B17", "GSPI0_MISO", "n/a", + "GPP_B18", "GSPI0_MOSI", "n/a", + "GPP_B19", "GSPI1_CS0#", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", + "GSPI0_CLK_LOOPBK", "GSPI0_CLK_LOOPBK", "n/a", + "GSPI1_CLK_LOOPBK", "GSPI1_CLK_LOOPBK", "n/a", }; const struct gpio_group cannonlake_pch_lp_group_b = { @@ -109,31 +109,31 @@ }; const char *const cannonlake_pch_lp_group_d_names[] = { - "GPP_D0", "SPI1_CS#", "BK0", "SBK0", - "GPP_D1", "SPI1_CLK", "BK1", "SBK1", - "GPP_D2", "SPI1_MISO", "BK2", "SBK2", - "GPP_D3", "SPI1_MOSI", "BK3", "SBK3", - "GPP_D4", "IMGCLKOUT0", "BK4", "SBK4", - "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a", - "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a", - "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a", - "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a", - "GPP_D9", "ISH_SPI_CS#", "n/a", "GSPI2_CS0#", - "GPP_D10", "ISH_SPI_CLK", "n/a", "GSPI2_CLK", - "GPP_D11", "ISH_SPI_MISO", "n/a", "GSPI2_MISO", - "GPP_D12", "ISH_SPI_MOSI", "n/a", "GSPI2_MOSI", - "GPP_D13", "ISH_UART0_RXD", "SML0BDATA", "I2C4B_SDA", - "GPP_D14", "ISH_UART0_TXD", "SML0BCLK", "I2C4B_SCL", - "GPP_D15", "ISH_UART0_RTS#", "GSPI2_CS1#", "n/a", - "GPP_D16", "ISH_UART0_CTS#", "SML0BALERT", "n/a", - "GPP_D17", "DMIC_CLK1", "SNDW3_CLK", "n/a", - "GPP_D18", "DMIC_DATA1", "SNDW3_DATA", "n/a", - "GPP_D19", "DMIC_CLK0", "SNDW4_CLK", "n/a", - "GPP_D20", "DMIC_DATA0", "SNDW4_DATA", "n/a", - "GPP_D21", "SPI1_IO2", "n/a", "n/a", - "GPP_D22", "SPI1_IO3", "n/a", "n/a", - "GPP_D23", "I2S_MCLK", "n/a", "n/a", - "GPIO_RSVD_12", "n/a", "n/a", "n/a", + "GPP_D0", "SPI1_CS#", "BK0", "SBK0", + "GPP_D1", "SPI1_CLK", "BK1", "SBK1", + "GPP_D2", "SPI1_MISO", "BK2", "SBK2", + "GPP_D3", "SPI1_MOSI", "BK3", "SBK3", + "GPP_D4", "IMGCLKOUT0", "BK4", "SBK4", + "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a", + "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a", + "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a", + "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a", + "GPP_D9", "ISH_SPI_CS#", "n/a", "GSPI2_CS0#", + "GPP_D10", "ISH_SPI_CLK", "n/a", "GSPI2_CLK", + "GPP_D11", "ISH_SPI_MISO", "n/a", "GSPI2_MISO", + "GPP_D12", "ISH_SPI_MOSI", "n/a", "GSPI2_MOSI", + "GPP_D13", "ISH_UART0_RXD", "SML0BDATA", "I2C4B_SDA", + "GPP_D14", "ISH_UART0_TXD", "SML0BCLK", "I2C4B_SCL", + "GPP_D15", "ISH_UART0_RTS#", "GSPI2_CS1#", "n/a", + "GPP_D16", "ISH_UART0_CTS#", "SML0BALERT", "n/a", + "GPP_D17", "DMIC_CLK1", "SNDW3_CLK", "n/a", + "GPP_D18", "DMIC_DATA1", "SNDW3_DATA", "n/a", + "GPP_D19", "DMIC_CLK0", "SNDW4_CLK", "n/a", + "GPP_D20", "DMIC_DATA0", "SNDW4_DATA", "n/a", + "GPP_D21", "SPI1_IO2", "n/a", "n/a", + "GPP_D22", "SPI1_IO3", "n/a", "n/a", + "GPP_D23", "I2S_MCLK", "n/a", "n/a", + "GSPI2_CLK_LOOPBK", "GSPI2_CLK_LOOPBK", "n/a", "n/a", }; const struct gpio_group cannonlake_pch_lp_group_d = { -- To view, visit https://review.coreboot.org/c/coreboot/+/45200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86c7159d9f48560c41efdfe49f162aef00499d13 Gerrit-Change-Number: 45200 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso: Use common SMM save state ops
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37019 ) Change subject: soc/amd/picasso: Use common SMM save state ops ...................................................................... soc/amd/picasso: Use common SMM save state ops Change-Id: I9eb42b9f9b14925a682356e21bbb0d2ccaeaafec Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/picasso/smihandler.c 1 file changed, 24 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37019/1 diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 39c2dfd..b04eddb 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <cpu/x86/cache.h> -#include <cpu/amd/amd64_save_state.h> #include <arch/acpi.h> #include <arch/hlt.h> #include <device/pci_def.h> @@ -41,17 +40,18 @@ SMM_IO_TRAP_PORT_ADDRESS_MASK); } -static void *find_save_state(int cmd) +static int find_save_state_node(int cmd) { int core; - amd64_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); u32 smm_io_trap; u8 reg_al; + u64 rax; /* Check all nodes looking for the one that issued the IO */ for (core = 0; core < CONFIG_MAX_CPUS; core++) { - state = smm_get_save_state(core); - smm_io_trap = state->smm_io_trap_offset; + if (ops->get_io_trap(core, &smm_io_trap)) + continue; /* Check for Valid IO Trap Word (bit1==1) */ if (!(smm_io_trap & SMM_IO_TRAP_VALID)) continue; @@ -62,30 +62,39 @@ if (pm_acpi_smi_cmd_port() != get_io_address(smm_io_trap)) continue; /* Check AL against the requested command */ - reg_al = state->rax; + if (ops->get_reg(core, RAX, &rax)) + continue; + reg_al = rax; if (reg_al == cmd) - return state; + return core; } - return NULL; + return -1; } static void southbridge_smi_gsmi(void) { + u32 ret, param; u8 sub_command; - amd64_smm_state_save_area_t *io_smi; - u32 reg_ebx; + int node = find_save_state_node(APM_CNT_ELOG_GSMI); + const struct smm_save_state_ops *ops = get_save_state_ops(); - io_smi = find_save_state(APM_CNT_ELOG_GSMI); - if (!io_smi) + if (node < -1) return; + /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; + uint64_t reg; + if (ops->get_reg(node, RAX, &reg)) + return; + sub_command = (u8)(reg >> 8); /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; + if (ops->get_reg(node, RBX, &reg)) + return; + param = reg & UINT32_MAX; /* drivers/elog/gsmi.c */ - io_smi->rax = gsmi_exec(sub_command, &reg_ebx); + ret = gsmi_exec(sub_command, (u32 *)param); + ops->set_reg(node, RAX, reg); } static void sb_apmc_smi_handler(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/37019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9eb42b9f9b14925a682356e21bbb0d2ccaeaafec Gerrit-Change-Number: 37019 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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