coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/xeon_sp: Enable SMI handler
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded a new patch set (#26) to the change originally created by Rocky Phagura. ( https://review.coreboot.org/c/coreboot/+/46231 ) Change subject: soc/intel/xeon_sp: Enable SMI handler ...................................................................... soc/intel/xeon_sp: Enable SMI handler SMI handler was not installed for Xeon_sp platforms. This enables SMM relocation and SMI handling. TESTED: - SMRR are correctly set - The save state revision is correct (0x00030101) - SMI's are properly generated and handled - SMM MSR save state are not supported, so relocate SMM on all cores in series - Verified on OCP/Deltalake mainboard. NOTE: - Code for accessing a CPU save state is not working for SMMLOADERV2, so some SMM features like GSMI, SMMSTORE, updating the ACPI GNVS pointer are not supported. - This hooks up to some soc/intel/common like TCO and ACPI GNVS. GNVS is broken and needs to be fixed separately. It is unknown if TCO is supported. This might require a cleanup in the future. Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Signed-off-by: Rocky Phagura <rphagura(a)fb.com> Signed-off-by: Christian Walter <christian.walter(a)9elements.com> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/Makefile.inc M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/smbus.h A src/soc/intel/xeon_sp/include/soc/smmrelocate.h M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/skx/Makefile.inc M src/soc/intel/xeon_sp/skx/cpu.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/smmrelocate.c 14 files changed, 226 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46231/26 -- To view, visit https://review.coreboot.org/c/coreboot/+/46231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Gerrit-Change-Number: 46231 Gerrit-PatchSet: 26 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Documentation/releases: Add ASan to 4.13 relnotes
by Harshit Sharma (Code Review) 11 Nov '20

11 Nov '20

Harshit Sharma has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45118 ) Change subject: Documentation/releases: Add ASan to 4.13 relnotes ...................................................................... Documentation/releases: Add ASan to 4.13 relnotes Change-Id: I2953729c69dfcfa8b34192b3e1623fdfad87ca3a Signed-off-by: Harshit Sharma <harshitsharmajs(a)gmail.com> --- M Documentation/releases/coreboot-4.13-relnotes.md 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/45118/1 diff --git a/Documentation/releases/coreboot-4.13-relnotes.md b/Documentation/releases/coreboot-4.13-relnotes.md index dcc8bf4..388d291 100644 --- a/Documentation/releases/coreboot-4.13-relnotes.md +++ b/Documentation/releases/coreboot-4.13-relnotes.md @@ -49,4 +49,13 @@ CPU threads as possible limited only by SMRAM space and not by 64K. By default this loader version is disabled. Please see cpu/x86/Kconfig for more info. +### Address Sanitizer + +coreboot now has an in-built Address Sanitizer, a runtime memory debugger +designed to find out-of-bounds access and use-after-scope bugs. It is made +available on all x86 platforms in ramstage and on QEMU i440fx, Intel Apollo +Lake, and Haswell in romstage. Further, it can be enabled in romstage on other +x86 platforms as well. Refer [ASan documentation](../technotes/asan.md) for +more info. + ### Add significant changes here -- To view, visit https://review.coreboot.org/c/coreboot/+/45118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2953729c69dfcfa8b34192b3e1623fdfad87ca3a Gerrit-Change-Number: 45118 Gerrit-PatchSet: 1 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Enable SMI handler
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded a new patch set (#25) to the change originally created by Rocky Phagura. ( https://review.coreboot.org/c/coreboot/+/46231 ) Change subject: soc/intel/xeon_sp: Enable SMI handler ...................................................................... soc/intel/xeon_sp: Enable SMI handler SMI handler was not installed for Xeon_sp platforms. This enables SMM relocation and SMI handling. TESTED: - SMRR are correctly set - The save state revision is correct (0x00030101) - SMI's are properly generated and handled - SMM save state MSR don't work, so relocate SMM on all cores in series - Verified on OCP/Deltalake mainboard. NOTE: - Code for accessing a CPU save state is not working for SMMLOADERV2 Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Signed-off-by: Rocky Phagura <rphagura(a)fb.com> Signed-off-by: Christian Walter <christian.walter(a)9elements.com> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/Makefile.inc M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/smbus.h A src/soc/intel/xeon_sp/include/soc/smmrelocate.h M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/skx/Makefile.inc M src/soc/intel/xeon_sp/skx/cpu.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/smmrelocate.c 14 files changed, 226 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46231/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/46231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Gerrit-Change-Number: 46231 Gerrit-PatchSet: 25 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sb/intel/lynxpoint/sata.c: Simplify RMW operations
by Angel Pons (Code Review) 11 Nov '20

11 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47030 ) Change subject: sb/intel/lynxpoint/sata.c: Simplify RMW operations ...................................................................... sb/intel/lynxpoint/sata.c: Simplify RMW operations Introduce the `sir_unset_and_set_mask` helper and update the one PCI read-modify-write operation that is somehow not reproducible. Change-Id: I30ad6ef8ad97ee0a8dc2297fba5bbbfe24f00f1c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/sata.c 1 file changed, 13 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/47030/1 diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index d0aaa99..4174e1f 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -25,10 +25,17 @@ pci_write_config32(dev, SATA_SIRD, value); } +static inline void sir_unset_and_set_mask(struct device *dev, int idx, u32 unset, u32 set) +{ + pci_write_config32(dev, SATA_SIRI, idx); + + const u32 value = pci_read_config32(dev, SATA_SIRD) & ~unset; + pci_write_config32(dev, SATA_SIRD, value | set); +} + static void sata_init(struct device *dev) { u32 reg32; - u16 reg16; u32 *abar; @@ -70,10 +77,7 @@ pci_write_config32(dev, IDE_CONFIG, reg32); /* for AHCI, Port Enable is managed in memory mapped space */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; - reg16 |= 0x8000 | config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); + pci_update_config16(dev, 0x92, ~0x3f, 0x8000 | config->sata_port_map); udelay(2); /* Setup register 98h */ @@ -174,25 +178,16 @@ sir_write(dev, 0x64, 0x883c9001); /* Step 2: SIR 68h[15:0] = 880Ah */ - reg32 = sir_read(dev, 0x68); - reg32 &= 0xffff0000; - reg32 |= 0x880a; - sir_write(dev, 0x68, reg32); + sir_unset_and_set_mask(dev, 0x68, 0xffff, 0x880a); /* Step 3: SIR 60h[3] = 1 */ - reg32 = sir_read(dev, 0x60); - reg32 |= (1 << 3); - sir_write(dev, 0x60, reg32); + sir_unset_and_set_mask(dev, 0x60, 0, 1 << 3); /* Step 4: SIR 60h[0] = 1 */ - reg32 = sir_read(dev, 0x60); - reg32 |= (1 << 0); - sir_write(dev, 0x60, reg32); + sir_unset_and_set_mask(dev, 0x60, 0, 1 << 0); /* Step 5: SIR 60h[1] = 1 */ - reg32 = sir_read(dev, 0x60); - reg32 |= (1 << 1); - sir_write(dev, 0x60, reg32); + sir_unset_and_set_mask(dev, 0x60, 0, 1 << 1); /* Clock Gating */ sir_write(dev, 0x70, 0x3f00bf1f); -- To view, visit https://review.coreboot.org/c/coreboot/+/47030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30ad6ef8ad97ee0a8dc2297fba5bbbfe24f00f1c Gerrit-Change-Number: 47030 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/hp/folio_9480m: Drop `sata_ahci` from devtree
by Angel Pons (Code Review) 11 Nov '20

11 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47426 ) Change subject: mb/hp/folio_9480m: Drop `sata_ahci` from devtree ...................................................................... mb/hp/folio_9480m: Drop `sata_ahci` from devtree Commit 8084b38568 (sb/intel/lynxpoint/sata: Always use AHCI mode) dropped the devtree option, but missed this recently-added mainboard. Change-Id: I6ab3a763c0bcd7431193c48e473639589b1a1e1a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/hp/folio_9480m/devicetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/47426/1 diff --git a/src/mainboard/hp/folio_9480m/devicetree.cb b/src/mainboard/hp/folio_9480m/devicetree.cb index bd81d38..140aa84 100644 --- a/src/mainboard/hp/folio_9480m/devicetree.cb +++ b/src/mainboard/hp/folio_9480m/devicetree.cb @@ -36,7 +36,6 @@ register "gen2_dec" = "0x000c0101" register "gen4_dec" = "0x000402e9" register "xhci_default" = "1" - register "sata_ahci" = "1" register "sata_port1_gen3_dtle" = "0x6" # SATA(1), M.2(3) register "sata_port_map" = "0xa" -- To view, visit https://review.coreboot.org/c/coreboot/+/47426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ab3a763c0bcd7431193c48e473639589b1a1e1a Gerrit-Change-Number: 47426 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: WIP: mediatek/mt8192: spm: Add checks
by Nicolas Boichat (Code Review) 11 Nov '20

11 Nov '20

Nicolas Boichat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47283 ) Change subject: WIP: mediatek/mt8192: spm: Add checks ...................................................................... WIP: mediatek/mt8192: spm: Add checks 16-byte alignement is critical for program section, so let's assume it also is for the data section (before we accidentally hit the issue again, which is very unlikely as the 21 bytes of data would need to stride over a 4kb boundary). Also, add assertions to make sure the offsets are valid. BUG=b:172177570 TEST=Asurada boots up to shell, suspend works Signed-off-by: Nicolas Boichat <drinkcat(a)chromium.org> Change-Id: I1d0643368e4fb04e23b0fc1daef98f4b548dabc6 --- M 3rdparty/amd_blobs M 3rdparty/blobs M src/soc/mediatek/mt8192/spm.c 3 files changed, 17 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/47283/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 335f577..539d31a 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 335f577697f7d27353a84b8a156a67a1dbad255f +Subproject commit 539d31ab9ea89084fa5edf7cc9ac3122786d5454 diff --git a/3rdparty/blobs b/3rdparty/blobs index 0839a7c..5e8dd64 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 0839a7cb848f783b42aa133606c9e109174c4a55 +Subproject commit 5e8dd6456365461e725b53968ef8b82656d86560 diff --git a/src/soc/mediatek/mt8192/spm.c b/src/soc/mediatek/mt8192/spm.c index 4847377..b10268c 100644 --- a/src/soc/mediatek/mt8192/spm.c +++ b/src/soc/mediatek/mt8192/spm.c @@ -430,16 +430,22 @@ 0x1f17618b, 0x61acb7ed, 0x01a8f1a5, 0x1100040c, 0x00a041be, 0x48fc1f1f, 0x01a8f1a5, 0x1100040c, 0xf1a581b8, 0x000c01a8, 0x31be1120, 0x60ee1f1f, 0x01a8d1a5, 0x1140000c, 0x20688314, 0x0600800f, 0x07800000, 0xcfa58049, - 0x67670007, 0x3f20e74b, 0x01000100, 0x01000201, 0x02010201, 0x01000402, + 0x67670007, 0x3f20e74b, /* End of program */ + /* Padding to 16-byte alignment (14 bytes) */ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, + /* Data */ + 0x01000100, 0x01000201, 0x02010201, 0x01000402, 0x02010402, 0x04020402, 0x01000803, 0x02010803, 0x04020803, 0x01001004, 0x02011004, 0x04021004, 0x08031004, 0x01002005, 0x02012005, 0x04022005, 0x08032005, 0x01004006, 0x02014006, 0x04024006, 0x08034006 }; -static struct spm_desc spm_firmware = { +static const struct spm_desc spm_firmware = { .version = "pcm_suspend_v1.45_20201028_mtcmosapi", - .pmem_words = 0x9c2, - .total_words = 0x9d7, + .pmem_words = 0x9d0, + .total_words = 0x9e5, .pmem_start = 0x10000000, .dmem_start = 0x10003800 }; @@ -937,6 +943,11 @@ pmem_start = spm_firmware.pmem_start; dmem_start = spm_firmware.dmem_start; + /* DMA needs 16-byte aligned source data. */ + assert((ptr % 16) == 0); + assert((pmem_words % 16) == 0); + assert(total_words == ARRAY_SIZE(spm_firmware_binary)); + /* tell IM where is PCM code (use slave mode if code existed) */ if (read32(&mtk_spm->md32pcm_dma0_src) != ptr || read32(&mtk_spm->md32pcm_dma0_dst) != pmem_start || -- To view, visit https://review.coreboot.org/c/coreboot/+/47283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d0643368e4fb04e23b0fc1daef98f4b548dabc6 Gerrit-Change-Number: 47283 Gerrit-PatchSet: 1 Gerrit-Owner: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mt8192/mcupm.c: use load_blob_file to load the blob file
by Yidi Lin (Code Review) 11 Nov '20

11 Nov '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46931 ) Change subject: mt8192/mcupm.c: use load_blob_file to load the blob file ...................................................................... mt8192/mcupm.c: use load_blob_file to load the blob file Use load_blob_file to load the blob file. TEST=1. emerge-asurada coreboot chromeos-bootimage; 2. See following log during booting. load_blob_file: Load mcupm.bin in 35 msecs, size 115668 bytes 3. Test suspend/resume by: a. suspend (on DUT): echo mem > /sys/power/stat b. resume (on host): dut-control power_state:on Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: I871cb3486ddf1346cf1aad16057192aa769918db --- M src/soc/mediatek/mt8192/mcupm.c 1 file changed, 4 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46931/1 diff --git a/src/soc/mediatek/mt8192/mcupm.c b/src/soc/mediatek/mt8192/mcupm.c index 9391b05..df4111f 100644 --- a/src/soc/mediatek/mt8192/mcupm.c +++ b/src/soc/mediatek/mt8192/mcupm.c @@ -1,31 +1,22 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/barrier.h> -#include <cbfs.h> #include <console/console.h> #include <device/mmio.h> #include <soc/mcupm.h> -#include <string.h> +#include <soc/mtlib_common.h> #define ABNORMALBOOT_REG (0x0C55FAA0) -#define BUF_SIZE (128 * KiB) -static uint8_t mcupm_bin[BUF_SIZE] __aligned(8); +#define MCUPM_BLOB_FILE "mcupm.bin" void mcupm_init(void) { - const char *file_name = "mcupm.bin"; - size_t fw_size = cbfs_boot_load_file(file_name, - mcupm_bin, - sizeof(mcupm_bin), - CBFS_TYPE_RAW); - - if (fw_size == 0) - die("MCUPM file :mcupm.bin not found."); + if (load_blob_file(MCUPM_BLOB_FILE, MCUPM_SRAM_BASE)) + die("MCUPM file :%s not found.", MCUPM_BLOB_FILE); write32(&mt8192_mcupm->sw_rstn, 0x0); /* Clear abnormal boot register */ write32((void *)ABNORMALBOOT_REG, 0x0); - memcpy((void *)MCUPM_SRAM_BASE, mcupm_bin, fw_size); /* Memory barrier to ensure that all fw code is loaded * before we release the reset pin. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I871cb3486ddf1346cf1aad16057192aa769918db Gerrit-Change-Number: 46931 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: DO-NOT-SUBMIT: ignore changes under 3rdparty folder
by Yidi Lin (Code Review) 11 Nov '20

11 Nov '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46412 ) Change subject: DO-NOT-SUBMIT: ignore changes under 3rdparty folder ...................................................................... DO-NOT-SUBMIT: ignore changes under 3rdparty folder Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: I1651e27f2875647d9cd1b50c6520c7c8c74f2488 --- M .gitmodules M 3rdparty/amd_blobs M 3rdparty/blobs M 3rdparty/intel-microcode M 3rdparty/qc_blobs 5 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/46412/1 diff --git a/.gitmodules b/.gitmodules index 4350a2c..626bf52 100644 --- a/.gitmodules +++ b/.gitmodules @@ -2,7 +2,7 @@ path = 3rdparty/blobs url = ../blobs.git update = none - ignore = dirty + ignore = all [submodule "util/nvidia-cbootimage"] path = util/nvidia/cbootimage url = ../nvidia-cbootimage.git @@ -25,7 +25,7 @@ path = 3rdparty/fsp url = ../fsp.git update = none - ignore = dirty + ignore = all [submodule "opensbi"] path = 3rdparty/opensbi url = ../opensbi.git @@ -33,7 +33,7 @@ path = 3rdparty/intel-microcode url = ../intel-microcode.git update = none - ignore = dirty + ignore = all [submodule "3rdparty/ffs"] path = 3rdparty/ffs url = ../ffs.git @@ -41,7 +41,7 @@ path = 3rdparty/amd_blobs url = ../amd_blobs update = none - ignore = dirty + ignore = all [submodule "3rdparty/cmocka"] path = 3rdparty/cmocka url = ../cmocka.git @@ -50,7 +50,7 @@ path = 3rdparty/qc_blobs url = ../qc_blobs.git update = none - ignore = dirty + ignore = all [submodule "3rdparty/intel-sec-tools"] path = 3rdparty/intel-sec-tools url = ../9esec-security-tooling.git diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index e393a88..335f577 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit e393a885c89f8ee3f05242a9e42578c60931b49d +Subproject commit 335f577697f7d27353a84b8a156a67a1dbad255f diff --git a/3rdparty/blobs b/3rdparty/blobs index 1aff9c3..96ae35c 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 1aff9c32eb15fc0e9da2f389f9b77e06d6fd3a21 +Subproject commit 96ae35c462d903d6940d982e61bea697103b7af6 diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 0e4288f..ee319ae 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 0e4288f81f806620c65f70ee2bcf94b69d574096 +Subproject commit ee319ae7bc59e88b60142f40a9ec1b46656de4db diff --git a/3rdparty/qc_blobs b/3rdparty/qc_blobs index 6b7fe49..11b212c 160000 --- a/3rdparty/qc_blobs +++ b/3rdparty/qc_blobs @@ -1 +1 @@ -Subproject commit 6b7fe498eb782b8f9758f28dd53bb0697be0d0b0 +Subproject commit 11b212c273b930885d1bee0b00a223a73628c852 -- To view, visit https://review.coreboot.org/c/coreboot/+/46412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1651e27f2875647d9cd1b50c6520c7c8c74f2488 Gerrit-Change-Number: 46412 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: TEST
by Raymond Chung (Code Review) 11 Nov '20

11 Nov '20

Raymond Chung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47437 ) Change subject: TEST ...................................................................... TEST Change-Id: I6774e110d6b6980c814460648680ee352c45e206 Signed-off-by: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> --- M src/mainboard/google/volteer/variants/lindar/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/47437/1 diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index 87ca0a3..b078fa8 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -1,5 +1,5 @@ chip soc/intel/tigerlake - # USB Port Config + # USB Port Config register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C C1 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera -- To view, visit https://review.coreboot.org/c/coreboot/+/47437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6774e110d6b6980c814460648680ee352c45e206 Gerrit-Change-Number: 47437 Gerrit-PatchSet: 1 Gerrit-Owner: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Create drobit variant
by Frank Chu (Code Review) 11 Nov '20

11 Nov '20

Hello Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47435 to look at the new patch set (#2). Change subject: mb/google/volteer: Create drobit variant ...................................................................... mb/google/volteer: Create drobit variant Create the drobit variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:171947885 BRANCH=none TEST=emerge-volteer coreboot Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I290b8549a3559b7901518f6c3a75305ee3e572ad --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/drobit/include/variant/ec.h A src/mainboard/google/volteer/variants/drobit/include/variant/gpio.h A src/mainboard/google/volteer/variants/drobit/memory/Makefile.inc A src/mainboard/google/volteer/variants/drobit/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/drobit/memory/mem_parts_used.txt A src/mainboard/google/volteer/variants/drobit/overridetree.cb 8 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/47435/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I290b8549a3559b7901518f6c3a75305ee3e572ad Gerrit-Change-Number: 47435 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2020