coreboot-gerrit November 2020

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Change in coreboot[master]: mb/scaleway/tagada: Don't change FIAMUX when Security Override is set
by Julien Viard de Galbert (Code Review) 11 Nov '20

11 Nov '20

Hello build bot (Jenkins), Patrick Georgi, Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/25443 to look at the new patch set (#22). Change subject: mb/scaleway/tagada: Don't change FIAMUX when Security Override is set ...................................................................... mb/scaleway/tagada: Don't change FIAMUX when Security Override is set This will not enable M.2 SATA drive if the ME config was lost (For instance after flashing a full flash factory image) This is required so that the system can boot without FIA MUX error during flash update procedure. Change-Id: I55a8bcdc30bc67af2d3e9ccb8844eac599727108 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/mainboard/scaleway/tagada/hsio.c 1 file changed, 35 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/25443/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/25443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55a8bcdc30bc67af2d3e9ccb8844eac599727108 Gerrit-Change-Number: 25443 Gerrit-PatchSet: 22 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock
by Julien Viard de Galbert (Code Review) 11 Nov '20

11 Nov '20

Hello build bot (Jenkins), David Guckian, Patrick Georgi, Steve Mooney, Paul Menzel, Vanessa Eusebio, Patrick Rudolph, David Guckian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/25442 to look at the new patch set (#22). Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock ...................................................................... soc/intel/denverton_ns: Implement PCIe post config + lock - Configure PCIe maximum payload size to fix Intel SSD - Lock Down PCIe Configuration Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/denverton_ns/lpc.c 1 file changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/25442/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/25442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd Gerrit-Change-Number: 25442 Gerrit-PatchSet: 22 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian <d.guckian20(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Steve Mooney Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/denverton_ns: Lock SPIBAR
by Julien Viard de Galbert (Code Review) 11 Nov '20

11 Nov '20

Hello build bot (Jenkins), David Guckian, Patrick Georgi, Steve Mooney, Paul Menzel, Vanessa Eusebio, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/25441 to look at the new patch set (#21). Change subject: soc/intel/denverton_ns: Lock SPIBAR ...................................................................... soc/intel/denverton_ns: Lock SPIBAR - Allow flash access when "Security Override" is set. - Don't lock when relax_security is set. Change-Id: I6934918d0c70245f03a1642f9a05e0110a205bc9 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/denverton_ns/lpc.c 2 files changed, 57 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/25441/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/25441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6934918d0c70245f03a1642f9a05e0110a205bc9 Gerrit-Change-Number: 25441 Gerrit-PatchSet: 21 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Steve Mooney Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/denverton_ns: Generate ACPI DMAR Table
by Julien Viard de Galbert (Code Review) 11 Nov '20

11 Nov '20

Hello build bot (Jenkins), David Guckian, Patrick Georgi, Paul Menzel, Vanessa Eusebio, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/25446 to look at the new patch set (#21). Change subject: soc/intel/denverton_ns: Generate ACPI DMAR Table ...................................................................... soc/intel/denverton_ns: Generate ACPI DMAR Table - Write ACPI DMAR Table if VT-d is enabled. - The entries are defined to follow FSP settings. Change-Id: I263b03b96280599266d4c5e193583ecdfe9697b7 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/include/soc/acpi.h M src/soc/intel/denverton_ns/include/soc/iomap.h M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/denverton_ns/include/soc/systemagent.h M src/soc/intel/denverton_ns/systemagent.c 6 files changed, 81 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/25446/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/25446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I263b03b96280599266d4c5e193583ecdfe9697b7 Gerrit-Change-Number: 25446 Gerrit-PatchSet: 21 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/denverton_ns: Initialize thermal configuration
by Julien Viard de Galbert (Code Review) 11 Nov '20

11 Nov '20

Hello build bot (Jenkins), David Guckian, Patrick Georgi, Steve Mooney, Paul Menzel, Vanessa Eusebio, Sumeet R Pawnikar, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/25439 to look at the new patch set (#21). Change subject: soc/intel/denverton_ns: Initialize thermal configuration ...................................................................... soc/intel/denverton_ns: Initialize thermal configuration Change-Id: I7e1b924154256f8f82ded3d0fa155b3e836d9375 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/denverton_ns/include/soc/msr.h 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/25439/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/25439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e1b924154256f8f82ded3d0fa155b3e836d9375 Gerrit-Change-Number: 25439 Gerrit-PatchSet: 21 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Steve Mooney Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes
by Julien Viard de Galbert (Code Review) 11 Nov '20

11 Nov '20

Hello build bot (Jenkins), Patrick Georgi, Paul Menzel, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/25436 to look at the new patch set (#21). Change subject: mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes ...................................................................... mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes Change-Id: Ic3ed97fc2b54d4974ec0b41b9f207fe3d49d2cce Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- A src/mainboard/scaleway/tagada/gpio_defs.h M src/mainboard/scaleway/tagada/hsio.c M src/mainboard/scaleway/tagada/hsio.h 3 files changed, 89 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/25436/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/25436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3ed97fc2b54d4974ec0b41b9f207fe3d49d2cce Gerrit-Change-Number: 25436 Gerrit-PatchSet: 21 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/denverton_ns: Enable MC Exception
by Julien Viard de Galbert (Code Review) 11 Nov '20

11 Nov '20

Hello Felix Singer, build bot (Jenkins), Patrick Georgi, David Guckian, Paul Menzel, Vanessa Eusebio, Angel Pons, Mimoja, Patrick Rudolph, David Guckian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/25434 to look at the new patch set (#19). Change subject: soc/intel/denverton_ns: Enable MC Exception ...................................................................... soc/intel/denverton_ns: Enable MC Exception Change-Id: I9773c61d06bb6c68612e498a35b5ad22cd5a8a6e Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/denverton_ns/cpu.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/25434/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/25434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9773c61d06bb6c68612e498a35b5ad22cd5a8a6e Gerrit-Change-Number: 25434 Gerrit-PatchSet: 19 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <d.guckian20(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [RFC] Tag boards with a new MAINBOARD_HAS_SUPERIO_UART symbol
by Paul Menzel (Code Review) 11 Nov '20

11 Nov '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37726 ) Change subject: [RFC] Tag boards with a new MAINBOARD_HAS_SUPERIO_UART symbol ...................................................................... Patch Set 1: I like the idea. -- To view, visit https://review.coreboot.org/c/coreboot/+/37726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c93ed77afc7fe226ddc19d6745d75876031b170 Gerrit-Change-Number: 37726 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 11 Nov 2020 21:39:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS
by Shreesh Chhabbi (Code Review) 11 Nov '20

11 Nov '20

Hello Shreesh Chhabbi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47258 to review the following change. Change subject: mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS ...................................................................... mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS Change-Id: Ifc77856e26ab26f9fbb2693f70c751f43337421b Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> --- M src/mainboard/google/volteer/Kconfig.name 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/47258/1 diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index d8f1b44..93f8628 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -4,14 +4,14 @@ bool "-> Delbin" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU - select USE_CAR_NEM_ENHANCED_V2 + select USE_CAR_NEM_ENHANCED_V1 select DRIVERS_GENESYSLOGIC_GL9755 config BOARD_GOOGLE_ELDRID bool "-> Eldrid" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU - select USE_CAR_NEM_ENHANCED_V2 + select USE_CAR_NEM_ENHANCED_V1 config BOARD_GOOGLE_HALVOR bool "-> Halvor" @@ -32,7 +32,7 @@ bool "-> Terrador" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU - select USE_CAR_NEM_ENHANCED_V2 + select USE_CAR_NEM_ENHANCED_V1 config BOARD_GOOGLE_TODOR bool "-> Todor" @@ -55,7 +55,7 @@ select BOARD_GOOGLE_BASEBOARD_VOLTEER select VARIANT_HAS_MIPI_CAMERA select SOC_INTEL_CSE_LITE_SKU - select USE_CAR_NEM_ENHANCED_V2 + select USE_CAR_NEM_ENHANCED_V1 select DRIVERS_GENESYSLOGIC_GL9755 # Reworked Volteer2 prototype, Haven chip replaced with Dauntless demo board @@ -64,14 +64,14 @@ select BOARD_GOOGLE_BASEBOARD_VOLTEER select VARIANT_HAS_MIPI_CAMERA select SOC_INTEL_CSE_LITE_SKU - select USE_CAR_NEM_ENHANCED_V2 + select USE_CAR_NEM_ENHANCED_V1 select DRIVERS_GENESYSLOGIC_GL9755 config BOARD_GOOGLE_VOXEL bool "-> Voxel" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU - select USE_CAR_NEM_ENHANCED_V2 + select USE_CAR_NEM_ENHANCED_V1 config BOARD_GOOGLE_BOLDAR bool "-> Boldar" -- To view, visit https://review.coreboot.org/c/coreboot/+/47258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc77856e26ab26f9fbb2693f70c751f43337421b Gerrit-Change-Number: 47258 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
by Shreesh Chhabbi (Code Review) 11 Nov '20

11 Nov '20

Hello Shreesh Chhabbi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47259 to review the following change. Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode ...................................................................... soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47259/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index ed35bd6..8d88b7b 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -23,7 +23,8 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE - select INTEL_CAR_NEM + select INTEL_CAR_NEM if !INTEL_CAR_NEM_ENHANCED + select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC -- To view, visit https://review.coreboot.org/c/coreboot/+/47259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5 Gerrit-Change-Number: 47259 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020