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Change subject: soc/intel/denverton_ns: Initialize thermal configuration
......................................................................
soc/intel/denverton_ns: Initialize thermal configuration
Change-Id: I7e1b924154256f8f82ded3d0fa155b3e836d9375
Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net>
---
M src/soc/intel/denverton_ns/cpu.c
M src/soc/intel/denverton_ns/include/soc/msr.h
2 files changed, 20 insertions(+), 0 deletions(-)
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/denverton_ns: Generate ACPI DMAR Table
......................................................................
soc/intel/denverton_ns: Generate ACPI DMAR Table
- Write ACPI DMAR Table if VT-d is enabled.
- The entries are defined to follow FSP settings.
Change-Id: I263b03b96280599266d4c5e193583ecdfe9697b7
Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net>
---
M src/soc/intel/denverton_ns/acpi.c
M src/soc/intel/denverton_ns/include/soc/acpi.h
M src/soc/intel/denverton_ns/include/soc/iomap.h
M src/soc/intel/denverton_ns/include/soc/pci_devs.h
M src/soc/intel/denverton_ns/include/soc/systemagent.h
M src/soc/intel/denverton_ns/systemagent.c
6 files changed, 81 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/25446/21
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Change subject: soc/intel/denverton_ns: Lock SPIBAR
......................................................................
soc/intel/denverton_ns: Lock SPIBAR
- Allow flash access when "Security Override" is set.
- Don't lock when relax_security is set.
Change-Id: I6934918d0c70245f03a1642f9a05e0110a205bc9
Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net>
---
M src/soc/intel/common/block/fast_spi/fast_spi_def.h
M src/soc/intel/denverton_ns/lpc.c
2 files changed, 57 insertions(+), 1 deletion(-)
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Hello build bot (Jenkins), David Guckian, Patrick Georgi, Steve Mooney, Paul Menzel, Vanessa Eusebio, Patrick Rudolph, David Guckian,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock
......................................................................
soc/intel/denverton_ns: Implement PCIe post config + lock
- Configure PCIe maximum payload size to fix Intel SSD
- Lock Down PCIe Configuration
Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd
Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net>
---
M src/soc/intel/denverton_ns/lpc.c
1 file changed, 35 insertions(+), 0 deletions(-)
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Hello build bot (Jenkins), Patrick Georgi, Paul Menzel,
I'd like you to reexamine a change. Please visit
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Change subject: mb/scaleway/tagada: Don't change FIAMUX when Security Override is set
......................................................................
mb/scaleway/tagada: Don't change FIAMUX when Security Override is set
This will not enable M.2 SATA drive if the ME config was lost
(For instance after flashing a full flash factory image)
This is required so that the system can boot without FIA MUX error
during flash update procedure.
Change-Id: I55a8bcdc30bc67af2d3e9ccb8844eac599727108
Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net>
---
M src/mainboard/scaleway/tagada/hsio.c
1 file changed, 35 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/25443/22
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37726 )
Change subject: [RFC] Tag boards with a new MAINBOARD_HAS_SUPERIO_UART symbol
......................................................................
Patch Set 1:
I like the idea.
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Gerrit-Comment-Date: Wed, 11 Nov 2020 21:39:30 +0000
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Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47453 )
Change subject: util/futility: Don't refresh the binary all the time
......................................................................
util/futility: Don't refresh the binary all the time
Due to the phony dependency to check for openssl, vboot-futility
was always rebuilt, and because it was newer than coreboot-futility,
it was always copied over.
Do that in parallel often enough and you run into race conditions,
as we did on our builders. Mark check-openssl-presence as order-only
dependency so that it's executed (and can bail out) but doesn't force
regeneration of vboot-futility.
Change-Id: Ib7fb798096d423d6b6cba5d199e12fe5917c3b41
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
M util/futility/Makefile.inc
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/47453/1
diff --git a/util/futility/Makefile.inc b/util/futility/Makefile.inc
index ed185ce..9890339 100644
--- a/util/futility/Makefile.inc
+++ b/util/futility/Makefile.inc
@@ -4,7 +4,7 @@
HOSTPKGCONFIG ?= pkg-config
-$(VBOOT_FUTILITY): check-openssl-presence
+$(VBOOT_FUTILITY): | check-openssl-presence
@printf " MAKE $(subst $(objutil)/,,$(@))\n"
unset CFLAGS LDFLAGS; $(MAKE) -C $(VBOOT_SOURCE) \
BUILD=$(VBOOT_HOST_BUILD) \
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25437 )
Change subject: FSP 2.0: Add fsp_relax_security
......................................................................
Patch Set 20:
(1 comment)
https://review.coreboot.org/c/coreboot/+/25437/18/src/drivers/intel/fsp2_0/…
File src/drivers/intel/fsp2_0/notify.c:
https://review.coreboot.org/c/coreboot/+/25437/18/src/drivers/intel/fsp2_0/…
PS18, Line 70: __attribute__((weak)) bool fsp_relax_security(void)
> Huh? Tbh I'm not sure how that would be used, anyway. […]
Ah, I missed the bmcInfo patch and I don't know bmcInfo, yet \o/ Soo... just that I get that right... is the plan to set that mode via BMC?
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