coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig
by Michael Niewöhner (Code Review) 12 Nov '20

12 Nov '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Michał Żygowski, Frans Hendriks, Tim Wawrzynczak, Subrata Banik, Aamir Bohra, Patrick Rudolph, Wim Vervoorn, Piotr Król, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45955 to look at the new patch set (#34). Change subject: soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig ...................................................................... soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig Select `PM_ACPI_TIMER_OPTIONAL` to enable the new PM ACPI Kconfig and set the FSP option for PM ACPI timer enablement from its value instead of using the old devicetree option. Also drop the obsolete devicetree option from soc code and from the mainboards and add a corresponding Kconfig entry instead. Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/facebook/monolith/Kconfig M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/Kconfig M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/Kconfig M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/Kconfig M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/kunimitsu/Kconfig M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/libretrend/lt1000/Kconfig M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/Kconfig M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 40 files changed, 41 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/45955/34 -- To view, visit https://review.coreboot.org/c/coreboot/+/45955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f Gerrit-Change-Number: 45955 Gerrit-PatchSet: 34 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
by Michael Niewöhner (Code Review) 12 Nov '20

12 Nov '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Aamir Bohra, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45952 to look at the new patch set (#30). Change subject: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer ...................................................................... soc/intel/common: add Kconfig to enable/disable the ACPI PM timer Currently, the ACPI PM timer state gets set in devicetree by the option PmTimerDisabled. However, it is not board design dependent. Thus, add a user-selectable Kconfig option. Disabling the PM ACPI Timer is only valid when PM Timer emulation is supported and is only possible, when there is a hardware PM Timer (APL does not have one for example). SoCs, where the hardware PM Timer can be disabled must select `PM_ACPI_TIMER_OPTIONAL`. This new Kconfig gets used in the follow-up commits of this series. Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/common/block/pmc/Kconfig 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/45952/30 -- To view, visit https://review.coreboot.org/c/coreboot/+/45952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917 Gerrit-Change-Number: 45952 Gerrit-PatchSet: 30 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards
by Michael Niewöhner (Code Review) 12 Nov '20

12 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47138 ) Change subject: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block… File src/soc/intel/common/block/acpi/acpi/pep.asl: https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block… PS8, Line 23: DEVY > actually I did this to keep the stuff below better readable, but sure, we could move it down, too Done -- To view, visit https://review.coreboot.org/c/coreboot/+/47138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac Gerrit-Change-Number: 47138 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 12 Nov 2020 10:44:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: drop the southridge scope around PEPD
by Michael Niewöhner (Code Review) 12 Nov '20

12 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47246 ) Change subject: soc/intel/common/acpi: drop the southridge scope around PEPD ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/47246/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47246/2//COMMIT_MSG@9 PS2, Line 9: PEPD will get included directly in the southbridge. > I agree with Michael. Also, other devices in this directory also don't […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/47246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb7a40e476966a7aca36bee055ee71d181508b87 Gerrit-Change-Number: 47246 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 12 Nov 2020 10:43:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1
by Caveh Jalali (Code Review) 12 Nov '20

12 Nov '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47501 ) Change subject: mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1 ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/47501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Gerrit-Change-Number: 47501 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 12 Nov 2020 10:06:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: WIP: load spm firmware from cbfs
by Yidi Lin (Code Review) 12 Nov '20

12 Nov '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47287 ) Change subject: WIP: load spm firmware from cbfs ...................................................................... WIP: load spm firmware from cbfs use mpufw_reserved region for experiment Change-Id: I563c2d959cc2b597fee137ef1c53ee028e3c20c0 Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> --- M 3rdparty/amd_blobs M 3rdparty/blobs M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/spm.h A src/soc/mediatek/mt8192/include/soc/symbols.h M src/soc/mediatek/mt8192/mmu_operations.c M src/soc/mediatek/mt8192/spm.c 7 files changed, 115 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/47287/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 335f577..539d31a 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 335f577697f7d27353a84b8a156a67a1dbad255f +Subproject commit 539d31ab9ea89084fa5edf7cc9ac3122786d5454 diff --git a/3rdparty/blobs b/3rdparty/blobs index 0839a7c..5e8dd64 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 0839a7cb848f783b42aa133606c9e109174c4a55 +Subproject commit 5e8dd6456365461e725b53968ef8b82656d86560 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index ca66095..f348a20 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -31,7 +31,7 @@ romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c -romstage-y += ../common/mmu_operations.c +romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-y += memory.c dramc_param.c ../common/memory_test.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c diff --git a/src/soc/mediatek/mt8192/include/soc/spm.h b/src/soc/mediatek/mt8192/include/soc/spm.h index 53b86e5..1ff8fd2 100644 --- a/src/soc/mediatek/mt8192/include/soc/spm.h +++ b/src/soc/mediatek/mt8192/include/soc/spm.h @@ -659,14 +659,19 @@ static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; -struct spm_desc { - const char *version; +struct pcm_desc { u32 pmem_words; u32 total_words; u32 pmem_start; u32 dmem_start; }; +struct dyna_load_pcm { + u32 *buf; /* binary array */ + struct pcm_desc desc; +}; + + int spm_init(void); #endif /* SOC_MEDIATEK_MT8192_SPM_H */ diff --git a/src/soc/mediatek/mt8192/include/soc/symbols.h b/src/soc/mediatek/mt8192/include/soc/symbols.h new file mode 100644 index 0000000..87a87d3 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/symbols.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_MEDIATEK_MT8192_SYMBOLS_H_ +#define _SOC_MEDIATEK_MT8192_SYMBOLS_H_ +#include <symbols.h> + +DECLARE_REGION(mpufw_reserved) + +#endif /* _SOC_MEDIATEK_MT8192_SYMBOLS_H_ */ diff --git a/src/soc/mediatek/mt8192/mmu_operations.c b/src/soc/mediatek/mt8192/mmu_operations.c index fb3620e..482eaae 100644 --- a/src/soc/mediatek/mt8192/mmu_operations.c +++ b/src/soc/mediatek/mt8192/mmu_operations.c @@ -3,6 +3,8 @@ #include <device/mmio.h> #include <soc/mcucfg.h> #include <soc/mmu_operations.h> +#include <soc/symbols.h> +#include <console/console.h> DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9) DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8) @@ -28,3 +30,11 @@ MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); dsb(); } + +void mtk_soc_after_dram(void) +{ + mmu_config_range(_mpufw_reserved, REGION_SIZE(mpufw_reserved), + NONSECURE_UNCACHED_MEM); + + printk(BIOS_ERR, "%s mpufw_reserved%p\n", __func__, _mpufw_reserved); +} diff --git a/src/soc/mediatek/mt8192/spm.c b/src/soc/mediatek/mt8192/spm.c index 5613027..58a4a16 100644 --- a/src/soc/mediatek/mt8192/spm.c +++ b/src/soc/mediatek/mt8192/spm.c @@ -6,8 +6,13 @@ #include <delay.h> #include <device/mmio.h> #include <soc/spm.h> +#include <soc/symbols.h> #include <timer.h> +#if 0 +#define BUF_SIZE (16 * KiB) +static u32 spm_bin[BUF_SIZE / 4] __aligned(8); + static const u32 spm_firmware_binary[] = { 0x3200001e, 0x6a00001e, 0x6e00001e, 0x6800001e, 0x6200001e, 0x6000001e, 0x5e00001e, 0x5c00001e, 0x6000001e, 0x5800001e, 0x5600001e, 0x5400001e, @@ -438,6 +443,7 @@ .pmem_start = 0x10000000, .dmem_start = 0x10003800 }; +#endif static struct pwr_ctrl spm_init_ctrl = { /* Auto-gen Start */ @@ -914,7 +920,7 @@ RG_AHBMIF_APBEN_LSB | REG_MD32_APB_INTERNAL_EN_LSB); } -static void spm_kick_im_to_fetch(void) +static void spm_kick_im_to_fetch(struct dyna_load_pcm *pcm) { uintptr_t ptr; u32 pmem_words; @@ -923,11 +929,25 @@ u32 dmem_start; u32 con0; +#if 0 ptr = (uintptr_t) spm_firmware_binary + 0x40000000; pmem_words = spm_firmware.pmem_words; total_words = spm_firmware.total_words; pmem_start = spm_firmware.pmem_start; dmem_start = spm_firmware.dmem_start; +#endif + //memcpy(spm_bin, pcm->buf, pcm->desc.total_words * sizeof(u32)); + ptr = (uintptr_t) pcm->buf + 0x40000000; + //ptr = (uintptr_t) spm_bin + 0x40000000; + pmem_words = pcm->desc.pmem_words; + total_words = pcm->desc.total_words; + pmem_start = pcm->desc.pmem_start; + dmem_start = pcm->desc.dmem_start; + + for (int i = 0; i < 32; i++) + printk(BIOS_ERR, "%#x\n", pcm->buf[i]); + + printk(BIOS_ERR, "%#x %#x %#x %#x\n", pmem_words, total_words, pmem_start, dmem_start); /* tell IM where is PCM code (use slave mode if code existed) */ if (read32(&mtk_spm->md32pcm_dma0_src) != ptr || @@ -968,6 +988,61 @@ write32(&mtk_spm->pcm_pwr_io_en, 0); } +static int spm_load_firmware(struct dyna_load_pcm *pcm) +{ + struct stopwatch sw; + const char *file_name = "spm_firmware.bin"; + size_t file_size; + int copy_size, offset; + u16 firmware_size; + + stopwatch_init(&sw); + + file_size = cbfs_boot_load_file(file_name, _mpufw_reserved, + REGION_SIZE(mpufw_reserved), CBFS_TYPE_RAW); + + mb(); + + if (file_size == 0) { + printk(BIOS_ERR, "SPM binary %s not found\n", file_name); + return -1; + } + + /* + * spmfw layout: + * u16 firmware_size + * u32 binary[firmware_size] + * struct pcm_desc descriptor + * char *version + */ + + /* firmware size */ + offset = 0; + copy_size = sizeof(firmware_size); + memcpy(&firmware_size, _mpufw_reserved + offset, copy_size); + printk(BIOS_DEBUG, "SPM: binary array size = 0x%x\n", firmware_size); + + /* binary */ + offset += 16; /* binary start offset */ + copy_size = firmware_size * sizeof(u32); + assert(offset < file_size); + pcm->buf = (u32 *)(_mpufw_reserved + offset); + + /* descriptor */ + offset += copy_size; + assert(offset < file_size); + copy_size = sizeof(struct pcm_desc); + memcpy((void *)&(pcm->desc.pmem_words), _mpufw_reserved + offset, copy_size); + + /* version */ + offset += copy_size; + assert(offset < file_size); + printk(BIOS_INFO, "spmfw version = %s and is loaded in %ld msecs\n", + (_mpufw_reserved + offset), stopwatch_duration_msecs(&sw)); + + return 0; +} + static void spm_set_wakeup_event(struct pwr_ctrl *pwrctrl) { u32 val, mask, isr; @@ -1064,6 +1139,7 @@ int spm_init(void) { + struct dyna_load_pcm pcm; struct stopwatch sw; stopwatch_init(&sw); @@ -1071,14 +1147,20 @@ spm_register_init(); spm_set_power_control(&spm_init_ctrl); spm_set_sysclk_settle(); + + if (spm_load_firmware(&pcm)) { + printk(BIOS_ERR, "SPM: firmware is not ready\n"); + return -1; + } + spm_reset_and_init_pcm(); - spm_kick_im_to_fetch(); + spm_kick_im_to_fetch(&pcm); spm_init_pcm_register(); spm_set_wakeup_event(&spm_init_ctrl); spm_kick_pcm_to_run(&spm_init_ctrl); - printk(BIOS_INFO, "SPM: %s done in %ld msecs, %s, spm pc = 0x%x\n", - __func__, stopwatch_duration_msecs(&sw), spm_firmware.version, + printk(BIOS_INFO, "SPM: %s done in %ld msecs, spm pc = 0x%x\n", + __func__, stopwatch_duration_msecs(&sw), read32(&mtk_spm->md32pcm_pc)); return 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/47287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I563c2d959cc2b597fee137ef1c53ee028e3c20c0 Gerrit-Change-Number: 47287 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/*/Kconfig: Annotate closing #endif with corresponding condition
by Paul Menzel (Code Review) 12 Nov '20

12 Nov '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47477 ) Change subject: mb/*/Kconfig: Annotate closing #endif with corresponding condition ...................................................................... mb/*/Kconfig: Annotate closing #endif with corresponding condition It’s common to annotate the closing #endif, so do it for these four files. Change-Id: Ia5d071e1f544c9dea5af9c6bc3c605d9a0c5c0f5 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/clevo/Kconfig M src/mainboard/razer/Kconfig M src/mainboard/system76/Kconfig M src/mainboard/up/Kconfig 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/47477/1 diff --git a/src/mainboard/clevo/Kconfig b/src/mainboard/clevo/Kconfig index d5ae6c1..96a5cbf 100644 --- a/src/mainboard/clevo/Kconfig +++ b/src/mainboard/clevo/Kconfig @@ -12,4 +12,4 @@ config MAINBOARD_VENDOR default "Clevo" -endif +endif #VENDOR_CLEVO diff --git a/src/mainboard/razer/Kconfig b/src/mainboard/razer/Kconfig index 9d96888..9f9c6fd 100644 --- a/src/mainboard/razer/Kconfig +++ b/src/mainboard/razer/Kconfig @@ -12,4 +12,4 @@ config MAINBOARD_VENDOR default "RAZER" -endif +endif # VENDOR_RAZER diff --git a/src/mainboard/system76/Kconfig b/src/mainboard/system76/Kconfig index 785d117..296f701 100644 --- a/src/mainboard/system76/Kconfig +++ b/src/mainboard/system76/Kconfig @@ -12,4 +12,4 @@ config MAINBOARD_VENDOR default "System76" -endif +endif # VENDOR_SYSTEM76 diff --git a/src/mainboard/up/Kconfig b/src/mainboard/up/Kconfig index aa8eda6..fdb3e71 100644 --- a/src/mainboard/up/Kconfig +++ b/src/mainboard/up/Kconfig @@ -12,4 +12,4 @@ config MAINBOARD_VENDOR default "UP" -endif +endif # VENDOR_UP -- To view, visit https://review.coreboot.org/c/coreboot/+/47477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5d071e1f544c9dea5af9c6bc3c605d9a0c5c0f5 Gerrit-Change-Number: 47477 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/x4x: allow to force RAM timings ignoring SPD values
by Angel Pons (Code Review) 12 Nov '20

12 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28200 ) Change subject: nb/intel/x4x: allow to force RAM timings ignoring SPD values ...................................................................... Patch Set 1: (4 comments) https://review.coreboot.org/c/coreboot/+/28200/1/src/northbridge/intel/x4x/… File src/northbridge/intel/x4x/Kconfig: https://review.coreboot.org/c/coreboot/+/28200/1/src/northbridge/intel/x4x/… PS1, Line 49: bool "Ignore RAM timing values stored in SPD EEPROMs" This option should be in an "Overclocking" menu https://review.coreboot.org/c/coreboot/+/28200/1/src/northbridge/intel/x4x/… File src/northbridge/intel/x4x/raminit.c: https://review.coreboot.org/c/coreboot/+/28200/1/src/northbridge/intel/x4x/… PS1, Line 116: if (IS_ENABLED(CONFIG_RAMINIT_FORCE)) { You'd still want to use a sticky scratchpad register to recover from non-working values. If hardcoded timings don't work: - Write a certain value in a sticky scratchpad register to indicate failure. - Do a FULL reset. Yes, the one that powers off then on; it's the only way to reset DDR2. - When reaching this part again, check if the scratchpad has the "failure value". If so, use the SPD timings instead of the hardcoded timings. https://review.coreboot.org/c/coreboot/+/28200/1/src/northbridge/intel/x4x/… PS1, Line 119: "Overriding probed memory timings:" : "tclk=%d, CAS=%d\n", CONFIG_RAMINIT_FORCE_TCK, : CONFIG_RAMINIT_FORCE_CL); Tried printing the values that get decoded from the SPDs? Also, I'm not sure how this raminit handles the other timings (they need to be adjusted when the tCK is changed). https://review.coreboot.org/c/coreboot/+/28200/1/src/northbridge/intel/x4x/… PS1, Line 132: if ((s->selected_timings.CAS < 3) || (s->selected_timings.tclk == 0)) You would still want to keep this check in place. -- To view, visit https://review.coreboot.org/c/coreboot/+/28200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0bb1ff22c89e62c62b53211ca2544430f6cfee0 Gerrit-Change-Number: 28200 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan T <stefan.tauner(a)gmx.at> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Stefan T <stefan.tauner(a)gmx.at> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 12 Nov 2020 09:29:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: MAKE: MOAAAAAR $$$$$$$$
by Paul Menzel (Code Review) 12 Nov '20

12 Nov '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29639 ) Change subject: MAKE: MOAAAAAR $$$$$$$$ ...................................................................... Patch Set 1: Is this still needed? -- To view, visit https://review.coreboot.org/c/coreboot/+/29639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19d3016e67f8930345e0da9564abcc5e5f8ab365 Gerrit-Change-Number: 29639 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 12 Nov 2020 07:38:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/intelp2m: Cleanup SCI, SMI macro generation and update comments
by Paul Menzel (Code Review) 12 Nov '20

12 Nov '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47314 ) Change subject: util/intelp2m: Cleanup SCI, SMI macro generation and update comments ...................................................................... Patch Set 4: (3 comments) https://review.coreboot.org/c/coreboot/+/47314/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47314/4//COMMIT_MSG@7 PS4, Line 7: Cleanup The verb is spelled with a space: Clean up. https://review.coreboot.org/c/coreboot/+/47314/4//COMMIT_MSG@9 PS4, Line 9: fix-up fix up https://review.coreboot.org/c/coreboot/+/47314/4//COMMIT_MSG@10 PS4, Line 10: CB:45008 As git is operated using commit SHA’s, it’d be great if you could add that hash too. -- To view, visit https://review.coreboot.org/c/coreboot/+/47314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie49874d4abbdc7d1a18d63a62ccbce970ce78233 Gerrit-Change-Number: 47314 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 12 Nov 2020 07:29:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2020