coreboot-gerrit October 2020

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Change in coreboot[master]: mb/clevo/kbl-u: Install Intel VGA INT15 handler
by Paul Menzel (Code Review) 23 Apr '21

23 Apr '21

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43852 ) Change subject: mb/clevo/kbl-u: Install Intel VGA INT15 handler ...................................................................... mb/clevo/kbl-u: Install Intel VGA INT15 handler Timestamp - Option ROM initialization: 77806110188 FMAP: area COREBOOT found @ 350200 (4914688 bytes) CBFS: Locating 'pci8086,5916.rom' CBFS: Found @ offset 11ce00 size 10000 In CBFS, ROM address for PCI: 00:02.0 = 0xffc6d048 PCI ROM image, vendor ID 8086, device ID 0406, ID mismatch: vendor ID 8086, device ID 5916 Copying VGA ROM Image from 0xffc6d048 to 0xc0000, 0x10000 bytes Timestamp - Option ROM copy done: 77877204844 Calling Option ROM... Unsupported software interrupt #0x15 eax 0x1905f34 Unsupported software interrupt #0x15 eax 0x5f51 Unsupported software interrupt #0x15 eax 0x5f40 Unsupported software interrupt #0x15 eax 0x5f52 Unsupported software interrupt #0x15 eax 0x5f49 Unsupported software interrupt #0x15 eax 0x3a95f49 Unsupported software interrupt #0x15 eax 0x5f14 Unsupported software interrupt #0x15 eax 0x405f35 ... Option ROM returned. VGA Option ROM was run Timestamp - Option ROM run done: 78406420234 PCI: 00:02.0 init finished in 210 msecs Change-Id: I126481c745ae701dc438ac664be0f8ff5f6250c1 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- A src/mainboard/clevo/kbl-u/mainboard.c 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/43852/1 diff --git a/src/mainboard/clevo/kbl-u/mainboard.c b/src/mainboard/clevo/kbl-u/mainboard.c new file mode 100644 index 0000000..01cfef4 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/mainboard.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, + GMA_INT15_PANEL_FIT_CENTERING, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/43852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I126481c745ae701dc438ac664be0f8ff5f6250c1 Gerrit-Change-Number: 43852 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] mainboard/acer: Add TravelMate X314
by Felix Singer (Code Review) 23 Apr '21

23 Apr '21

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35461 ) Change subject: [WIP] mainboard/acer: Add TravelMate X314 ...................................................................... [WIP] mainboard/acer: Add TravelMate X314 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: Ia9a1c3492aa41ef20a4408cc91370b8f94adbe47 --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/travelmate-x314/Kconfig A src/mainboard/acer/travelmate-x314/Kconfig.name A src/mainboard/acer/travelmate-x314/acpi_tables.c A src/mainboard/acer/travelmate-x314/board_info.txt A src/mainboard/acer/travelmate-x314/devicetree.cb A src/mainboard/acer/travelmate-x314/dsdt.asl 8 files changed, 211 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/35461/1 diff --git a/src/mainboard/acer/Kconfig b/src/mainboard/acer/Kconfig new file mode 100644 index 0000000..28a2945 --- /dev/null +++ b/src/mainboard/acer/Kconfig @@ -0,0 +1,28 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +if VENDOR_ACER + +choice + prompt "Mainboard model" + +source "src/mainboard/acer/*/Kconfig.name" + +endchoice + +source "src/mainboard/acer/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Acer" + +endif # VENDOR_ACER diff --git a/src/mainboard/acer/Kconfig.name b/src/mainboard/acer/Kconfig.name new file mode 100644 index 0000000..bb177f9 --- /dev/null +++ b/src/mainboard/acer/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_ACER + bool "Acer" diff --git a/src/mainboard/acer/travelmate-x314/Kconfig b/src/mainboard/acer/travelmate-x314/Kconfig new file mode 100644 index 0000000..8b71cbd --- /dev/null +++ b/src/mainboard/acer/travelmate-x314/Kconfig @@ -0,0 +1,70 @@ +if BOARD_ACER_TRAVELMATE_X314 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_SMI_HANDLER + select ONBOARD_VGA_IS_PRIMARY + select SOC_INTEL_WHISKEYLAKE +# select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_VENDOR + string + default "Acer" + +config MAINBOARD_FAMILY + string + default "TravelMate" + +config MAINBOARD_PART_NUMBER + string + default "X314" + +config MAINBOARD_VERSION + string + default "1.0" + +config MAINBOARD_DIR + string + default "acer/travelmate-x314" + +config SUBSYSTEM_VENDOR_ID + hex + default 0xdead + +config SUBSYSTEM_DEVICE_ID + hex + default 0xbeef + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_ID + string + default "8086,3ea0" + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config PXE_ROM_ID + string + default "dead,beef" + +config POST_DEVICE + bool + default n + +config CONSOLE_POST + bool + default y + +endif # BOARD_ACER_TRAVELMATE_X314 diff --git a/src/mainboard/acer/travelmate-x314/Kconfig.name b/src/mainboard/acer/travelmate-x314/Kconfig.name new file mode 100644 index 0000000..61b4b2c --- /dev/null +++ b/src/mainboard/acer/travelmate-x314/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ACER_TRAVELMATE_X314 + bool "TravelMate X314" diff --git a/src/mainboard/acer/travelmate-x314/acpi_tables.c b/src/mainboard/acer/travelmate-x314/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/acer/travelmate-x314/acpi_tables.c diff --git a/src/mainboard/acer/travelmate-x314/board_info.txt b/src/mainboard/acer/travelmate-x314/board_info.txt new file mode 100644 index 0000000..92ee253 --- /dev/null +++ b/src/mainboard/acer/travelmate-x314/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Acer +Board name: TravelMate X314 +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2019 diff --git a/src/mainboard/acer/travelmate-x314/devicetree.cb b/src/mainboard/acer/travelmate-x314/devicetree.cb new file mode 100644 index 0000000..7c519b0 --- /dev/null +++ b/src/mainboard/acer/travelmate-x314/devicetree.cb @@ -0,0 +1,57 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.5 on end # SDCard + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 on end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 on end # eMMC + device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 + device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/acer/travelmate-x314/dsdt.asl b/src/mainboard/acer/travelmate-x314/dsdt.asl new file mode 100644 index 0000000..daddd97 --- /dev/null +++ b/src/mainboard/acer/travelmate-x314/dsdt.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2018 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/cannonlake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/cannonlake/acpi/globalnvs.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> + } + } + + // Chipset specific sleep states + #include <soc/intel/cannonlake/acpi/sleepstates.asl> +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9a1c3492aa41ef20a4408cc91370b8f94adbe47 Gerrit-Change-Number: 35461 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset...
by Usha P (Code Review) 22 Apr '21

22 Apr '21

Usha P has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40363 ) Change subject: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values ...................................................................... soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values Add PCIEXBAR register LENGTH offset values to accommodate new SoC implementation. Changes: 1. The major delta is 0x60:PCIEXBAR register LENGTH offset definition has been changed for latest SoC. 2. Common code takes care of setting the right value for pciex length. TEST=Able to build CNL, SKL, APL platforms. Change-Id: I75619be7614f58c96670ef86485d49d4da06ad91 Signed-off-by: Usha P <usha.p(a)intel.com> --- M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent_def.h M src/soc/intel/common/block/systemagent/systemagent_early.c 3 files changed, 44 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/40363/1 diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 6d88cbc..db0cdbd 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -11,12 +11,28 @@ config SA_PCIEX_LENGTH_MIB hex - default 0x10000000 if (PCIEX_LENGTH_256MB) - default 0x8000000 if (PCIEX_LENGTH_128MB) - default 0x4000000 if (PCIEX_LENGTH_64MB) - default 0x10000000 + default 0x1000 if (PCIEX_LENGTH_4096MB) + default 0x800 if (PCIEX_LENGTH_2048MB) + default 0x400 if (PCIEX_LENGTH_1024MB) + default 0x200 if (PCIEX_LENGTH_512MB) + default 0x100 if (PCIEX_LENGTH_256MB) + default 0x80 if (PCIEX_LENGTH_128MB) + default 0x40 if (PCIEX_LENGTH_64MB) + default 0x100 help - This option allows you to select length of PCIEX region. + This option allows you to select length of PCIEX region in MiB. + +config PCIEX_LENGTH_4096MB + bool + +config PCIEX_LENGTH_2048MB + bool + +config PCIEX_LENGTH_1024MB + bool + +config PCIEX_LENGTH_512MB + bool config PCIEX_LENGTH_256MB bool diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h index 03f4de4..91595c2 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_def.h +++ b/src/soc/intel/common/block/systemagent/systemagent_def.h @@ -19,6 +19,10 @@ #define DPR_PRS (1 << 1) #define DPR_SIZE_MASK 0xff0 +#define PCIEXBAR_LENGTH_4096MB 6 +#define PCIEXBAR_LENGTH_2048MB 5 +#define PCIEXBAR_LENGTH_1024MB 4 +#define PCIEXBAR_LENGTH_512MB 3 #define PCIEXBAR_LENGTH_64MB 2 #define PCIEXBAR_LENGTH_128MB 1 #define PCIEXBAR_LENGTH_256MB 0 diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 79a6628..ff806ac 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -28,13 +28,29 @@ /* Get PCI Express Region Length */ switch (CONFIG_SA_PCIEX_LENGTH_MIB) { - case 256 * MiB: + /* + * Length of PCIEXBAR region would be more than 256MB if + * PCIEXBAR.LENGTH width is 3. + */ + case 4096: + pciexbar_length = PCIEXBAR_LENGTH_4096MB; + break; + case 2048: + pciexbar_length = PCIEXBAR_LENGTH_2048MB; + break; + case 1024: + pciexbar_length = PCIEXBAR_LENGTH_1024MB; + break; + case 512: + pciexbar_length = PCIEXBAR_LENGTH_512MB; + break; + case 256: pciexbar_length = PCIEXBAR_LENGTH_256MB; break; - case 128 * MiB: + case 128: pciexbar_length = PCIEXBAR_LENGTH_128MB; break; - case 64 * MiB: + case 64: pciexbar_length = PCIEXBAR_LENGTH_64MB; break; default: -- To view, visit https://review.coreboot.org/c/coreboot/+/40363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75619be7614f58c96670ef86485d49d4da06ad91 Gerrit-Change-Number: 40363 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: generate ACPI BERT table
by Jonathan Zhang (Code Review) 21 Apr '21

21 Apr '21

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45392 ) Change subject: soc/intel/xeon_sp/cpx: generate ACPI BERT table ...................................................................... soc/intel/xeon_sp/cpx: generate ACPI BERT table This is a WIP patch to prove that the BERT memory region put directly above CBMEM top works well for the purpose. Right now dummy error records is used, next step is to get error record raw data from PREV_BOOT_ERR_SRC_HOB. Select ACPI_BERT as default, configure ACPI_BERT_SIZE. BERT memory region is placed directly above CBMEM top, with the size of CONFIG_ACPI_BERT_SIZE. Set up e820 memory entry for it as reserved. If ACPI_BERT is selected, fill in APEI BERT with dummy error record. When there are error records in APEI BERT region, generate ACPI BERT table. TESTED=booted on DeltaLake DVT, following are boot log excepts: BIOS-e820: [mem 0x0000000000000000-0x0000000000000fff] type 16 BIOS-e820: [mem 0x0000000000001000-0x000000000009ffff] usable BIOS-e820: [mem 0x00000000000a0000-0x00000000000fffff] reserved BIOS-e820: [mem 0x0000000000100000-0x00000000752b1fff] usable BIOS-e820: [mem 0x00000000752b2000-0x00000000777fbfff] type 16 BIOS-e820: [mem 0x00000000777fc000-0x00000000777fffff] reserved <-- BERT region BIOS-e820: [mem 0x0000000078000000-0x000000008fffffff] reserved BIOS-e820: [mem 0x00000000fd000000-0x00000000fdffffff] reserved BIOS-e820: [mem 0x00000000fed40000-0x00000000fed44fff] reserved BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved BIOS-e820: [mem 0x0000000100000000-0x000000183fffffff] usable ... [ 13.624688] BERT: Error records from previous boot: [ 13.634676] [Hardware Error]: event severity: fatal [ 13.644666] [Hardware Error]: precise tstamp: 2020-09-15 02:15:53 [ 13.657329] [Hardware Error]: Error 0, type: fatal [ 13.667317] [Hardware Error]: section_type: general processor error [ 13.680509] [Hardware Error]: processor_type: 0, IA32/X64 [ 13.691919] [Hardware Error]: error_type: 0x02 [ 13.701368] [Hardware Error]: TLB error [ 13.709578] [Hardware Error]: version_info: 0x000000000005065b [ 13.721885] [Hardware Error]: processor_id: 0x0000000000000000 Change-Id: Ifb23883a6f0d4d737ba08e256fb927e9965cb803 Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> --- M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/uncore.c 3 files changed, 82 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/45392/1 diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 8e7e6f1..bba1eb3 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -87,4 +87,20 @@ int default 512 +config ACPI_BERT + bool "Build ACPI BERT Table" + default y + depends on HAVE_ACPI_TABLES + help + Report Machine Check errors identified in POST to the OS in an + ACPI Boot Error Record Table. + +config ACPI_BERT_SIZE + hex + default 0x4000 if ACPI_BERT + default 0x0 + help + Specify the amount of DRAM reserved for gathering the BERT error + records. + endif diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 1328257..3abc530 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -2,6 +2,7 @@ #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> +#include <arch/bert_storage.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <assert.h> @@ -12,6 +13,7 @@ #include <cpu/x86/smm.h> #include <device/pci.h> #include <intelblocks/acpi.h> +#include <lib.h> #include <hob_iiouds.h> #include <hob_memmap.h> #include <soc/acpi.h> @@ -878,6 +880,37 @@ return current; } +#ifdef CONFIG_ACPI_BERT +void bert_reserved_region(void **start, size_t *size) +{ + *start = cbmem_top(); + *size = CONFIG_ACPI_BERT_SIZE; + assert(*start); + memset(*start, 0, *size); + printk(BIOS_INFO, "Reserved BERT region base: %p, size: 0x%lx\n", *start, *size); +} + +static bool fill_bert_region(void) +{ + acpi_generic_error_status_t *status; + acpi_hest_generic_data_v300_t *gen_entry; + cper_proc_generic_error_section_t *gen_sec; + + status = bert_new_event(&CPER_SEC_PROC_GENERIC_GUID); + if (!status){ + printk(BIOS_ERR, "Error: Not enough room in BERT region for Machine Check error\n"); + return false; + } + + gen_entry = acpi_hest_generic_data3(status); + gen_sec = section_of_acpientry(gen_sec, gen_entry); + gen_sec->error_type = GENPROC_ERRTYPE_TLB; + gen_sec->validation |= GENPROC_VALID_PROC_ERR_TYPE; + + return true; +} +#endif + unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) @@ -885,6 +918,7 @@ acpi_srat_t *srat; acpi_slit_t *slit; acpi_dmar_t *dmar; + acpi_bert_t *bert; const struct soc_intel_xeon_sp_cpx_config *const config = config_of(device); @@ -917,5 +951,26 @@ acpi_add_table(rsdp, dmar); } + if (CONFIG(ACPI_BERT)) { + /* Fill BERT region. Return if not filled in. */ + if(!fill_bert_region()) + return current; + + void *rgn = NULL; + size_t size = 0; + bert_errors_region(&rgn, &size); + printk(BIOS_INFO, "BERT region base: %p, error record size: 0x%lx\n", rgn, size); + /* Add BERT table */ + if (rgn && size) { + hexdump(rgn, size); + current = ALIGN(current, 8); + bert = (acpi_bert_t *)current; + acpi_write_bert(bert, (uintptr_t)rgn, size); + acpi_add_table(rsdp, (void *)current); + current += bert->header.length; + } else { + printk(BIOS_ERR, "BERT region is not filled.\n"); + } + } return current; } diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index a549acb..d640c1d 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -153,6 +153,7 @@ uint64_t mc_values[NUM_MAP_ENTRIES]; struct resource *resource; int index = *res_count; + uintptr_t cbmem_top_addr = (uintptr_t)cbmem_top(); fsp_find_reserved_memory(&fsp_mem); @@ -162,7 +163,7 @@ top_of_ram = range_entry_base(&fsp_mem) - 1; printk(BIOS_SPEW, "cbmem_top: 0x%lx, fsp range: [0x%llx - 0x%llx], top_of_ram: 0x%llx\n", - (uintptr_t) cbmem_top(), range_entry_base(&fsp_mem), + cbmem_top_addr, range_entry_base(&fsp_mem), range_entry_end(&fsp_mem), top_of_ram); /* Conventional Memory (DOS region, 0x0 to 0x9FFFF) */ @@ -178,8 +179,7 @@ ram_resource(dev, index++, base_kb, size_kb); /* - * FSP meomoy, CBMem regions are already added as reserved - * Add TSEG and MESEG Regions as reserved memory + * FSP memory, CBMem regions are already added as reserved * src/drivers/intel/fsp2_0/memory_init.c sets CBMEM reserved size * arch_upd->BootLoaderTolumSize = cbmem_overhead_size(); == 2 * CBMEM_ROOT_MIN_SIZE * typically 0x2000 @@ -192,6 +192,14 @@ * FspBootLoaderTolum Size : 2000 */ + /* Mark APEI BERT region as reserved */ + if (CONFIG(ACPI_BERT)) { + base_kb = (cbmem_top_addr >> 10); + size_kb = (CONFIG_ACPI_BERT_SIZE >> 10); + LOG_MEM_RESOURCE("apei_bert", dev, index, base_kb, size_kb); + mmio_resource(dev, index++, base_kb, size_kb); + } + /* Mark TSEG/SMM region as reserved */ base_kb = (mc_values[TSEG_BASE_REG] >> 10); size_kb = (mc_values[TSEG_LIMIT_REG] - mc_values[TSEG_BASE_REG] + 1) >> 10; -- To view, visit https://review.coreboot.org/c/coreboot/+/45392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb23883a6f0d4d737ba08e256fb927e9965cb803 Gerrit-Change-Number: 45392 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: soc/intel/skylake: lock TCO base address on pch finalize
by Michael Niewöhner (Code Review) 21 Apr '21

21 Apr '21

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35525 ) Change subject: soc/intel/skylake: lock TCO base address on pch finalize ...................................................................... soc/intel/skylake: lock TCO base address on pch finalize This is a follow-up on I5bd95b3580adc0f4cffa667f8979b7cf08925720 which already locks TCO itself but does not lock the base address. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: Idab9419487e6e4cbdecd2efaa4772ff4960c9055 --- M src/soc/intel/common/block/smbus/tco.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/35525/1 diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 1a215eb..a3ebe24 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -34,6 +34,7 @@ #define TCOBASE 0x50 #define TCOCTL 0x54 #define TCO_BASE_EN (1 << 8) +#define TCO_BASE_LOCK (1 << 0) /* Get base address of TCO I/O registers. */ static uint16_t tco_get_bar(void) @@ -61,8 +62,13 @@ void tco_lockdown(void) { + uint32_t reg32; uint16_t tcocnt; + /* TCO base address lockdown */ + reg32 = pci_read_config32(dev, TCOCTL); + pci_write_config32(dev, TCOCTL, reg32 | TCO_BASE_LOCK); + /* TCO Lock down */ tcocnt = tco_read_reg(TCO1_CNT); tcocnt |= TCO_LOCK; -- To view, visit https://review.coreboot.org/c/coreboot/+/35525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idab9419487e6e4cbdecd2efaa4772ff4960c9055 Gerrit-Change-Number: 35525 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: [WIP]acpi: Get rid of boilerplate FADT
by Patrick Rudolph (Code Review) 19 Apr '21

19 Apr '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40036 ) Change subject: [WIP]acpi: Get rid of boilerplate FADT ...................................................................... [WIP]acpi: Get rid of boilerplate FADT Still not done.... Needs test on windows and Linux on all affected platforms, that is every x86 platform. Change-Id: If58fcf9a1c39c159dfa08339cb931e552d499747 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/acpi.c M src/arch/x86/include/arch/acpi.h M src/soc/intel/apollolake/acpi.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/skx/acpi.c M src/southbridge/amd/cimx/sb800/fadt.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 17 files changed, 407 insertions(+), 1,080 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/40036/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index e4932be..d540721 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -1249,6 +1249,17 @@ fadt->sleep_control_reg.bit_width = 8; fadt->sleep_status_reg.bit_width = 8; + if (CONFIG(ARCH_X86)) { + /* Set x86 defaults. A SoC can still overwrite those. */ + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = SYS_RESET; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = RST_CPU | SYS_RST; + } acpi_fill_fadt(fadt); header->checksum = @@ -1256,6 +1267,130 @@ } #endif +static void acpi_update_access_size(acpi_addr_t *reg) +{ + switch (DIV_ROUND_UP(reg->bit_width, 8)) { + case 0: + reg->access_size = ACPI_ACCESS_SIZE_UNDEFINED; + default: + case 1: + reg->access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + break; + case 2: + reg->access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + break; + case 4: + reg->access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + break; + case 8: + reg->access_size = ACPI_ACCESS_SIZE_QDWORD_ACCESS; + break; + } +} + +void acpi_fill_fadt_x86_pm(acpi_fadt_t *fadt, + u32 pm1a_evt_blk, + u32 pm1b_evt_blk, + u32 pm1a_cnt_blk, + u32 pm1b_cnt_blk, + u32 pm2_cnt_blk, + u32 pm_tmr_blk, + u32 gpe0_blk, + u32 gpe1_blk, + u8 pm1_evt_len, + u8 pm1_cnt_len, + u8 pm2_cnt_len, + u8 pm_tmr_len, + u8 gpe0_blk_len, + u8 gpe1_blk_len, + u8 gpe1_base) +{ + fadt->pm1a_evt_blk = pm1a_evt_blk; + fadt->pm1b_evt_blk = pm1b_evt_blk; + fadt->pm1a_cnt_blk = pm1a_cnt_blk; + fadt->pm1b_cnt_blk = pm1b_cnt_blk; + fadt->pm2_cnt_blk = pm2_cnt_blk; + fadt->pm_tmr_blk = pm_tmr_blk; + fadt->gpe0_blk = gpe0_blk; + fadt->gpe1_blk = gpe1_blk; + fadt->gpe1_base = gpe1_base; + + fadt->pm1_evt_len = pm1_evt_len; + fadt->pm1_cnt_len = pm1_cnt_len; + fadt->pm2_cnt_len = pm2_cnt_len; + fadt->pm_tmr_len = pm_tmr_len; + fadt->gpe0_blk_len = gpe0_blk_len; + fadt->gpe1_blk_len = gpe1_blk_len; + + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = pm1a_evt_blk; + fadt->x_pm1a_evt_blk.addrh = 0x0; + acpi_update_access_size(&fadt->x_pm1a_evt_blk); + + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_evt_blk.bit_width = pm1_evt_len * 8; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1b_evt_blk.addrl = pm1b_evt_blk; + fadt->x_pm1b_evt_blk.addrh = 0x0; + acpi_update_access_size(&fadt->x_pm1b_evt_blk); + + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_cnt_blk.bit_width = pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = pm1a_cnt_blk; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + acpi_update_access_size(&fadt->x_pm1a_cnt_blk); + + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_cnt_blk.bit_width = pm1_cnt_len * 8; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1b_cnt_blk.addrl = pm1b_cnt_blk; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + acpi_update_access_size(&fadt->x_pm1b_cnt_blk); + + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm2_cnt_blk.bit_width = pm2_cnt_len * 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = pm2_cnt_blk; + fadt->x_pm2_cnt_blk.addrh = 0x0; + acpi_update_access_size(&fadt->x_pm2_cnt_blk); + + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = pm_tmr_blk; + fadt->x_pm_tmr_blk.addrh = 0x0; + acpi_update_access_size(&fadt->x_pm_tmr_blk); + + /* + * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. + * The bit_width field intentionally overflows here. + * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which + * seems to work fine on Linux 5.0 and Windows 10. + */ + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = gpe0_blk_len * 8; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_gpe0_blk.addrl = gpe0_blk; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe1_blk.bit_width = gpe1_blk_len * 8; + fadt->x_gpe1_blk.bit_offset = gpe1_base * 8; + fadt->x_gpe1_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_gpe1_blk.addrl = gpe1_blk; + fadt->x_gpe1_blk.addrh = 0x0; +} + unsigned long __weak fw_cfg_acpi_tables(unsigned long start) { return 0; diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 4351678..107ad86 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -844,6 +844,25 @@ #if CONFIG(COMMON_FADT) void acpi_fill_fadt(acpi_fadt_t *fadt); #endif +/** + * Fill in ACPI FADT fields used by a generic x86 platform. + * That is all PM* and GPE* are located in IO space. + */ +void acpi_fill_fadt_x86_pm(acpi_fadt_t *fadt, + u32 pm1a_evt_blk, + u32 pm1b_evt_blk, + u32 pm1a_cnt_blk, + u32 pm1b_cnt_blk, + u32 pm2_cnt_blk, + u32 pm_tmr_blk, + u32 gpe0_blk, + u32 gpe1_blk, + u8 pm1_evt_len, + u8 pm1_cnt_len, + u8 pm2_cnt_len, + u8 pm_tmr_len, + u8 gpe0_blk_len, + u8 gpe1_blk_len); void update_ssdt(void *ssdt); void update_ssdtx(void *ssdtx, int i); diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index fbfe33f..ef1c01d 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -152,10 +152,9 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { const struct soc_intel_apollolake_config *cfg; + const uint16_t pmbase = ACPI_BASE_ADDRESS; cfg = config_of_soc(); - fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR; - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; @@ -164,13 +163,25 @@ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.addrl = ACPI_BASE_ADDRESS + PM1_TMR; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - if (cfg->lpss_s0ix_enable) fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; + + acpi_fill_fadt_x86_pm(fadt, + pmbase + PM1_STS, + 0, + pmbase + PM1_CNT, + 0, + 0, + pmbase + PM1_TMR, + pmbase + GPE0_STS(0), + 0, + 4, + 2, + 0, + 4, + 2 * GPE0_REG_MAX, + 0, + 0); } static unsigned long soc_fill_dmar(unsigned long current) diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 84659c9..490cabc 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -176,17 +176,25 @@ const struct soc_intel_cannonlake_config *config; config = config_of_soc(); - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->pm_tmr_len = 4; - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; - fadt->x_pm_tmr_blk.addrh = 0x0; - if (config->s0ix_enable) fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; + + acpi_fill_fadt_x86_pm(fadt, + pmbase + PM1_STS, + 0, + pmbase + PM1_CNT, + 0, + 0, + pmbase + PM1_TMR, + pmbase + GPE0_STS(0), + 0, + 4, + 2, + 0, + 4, + 2 * GPE0_REG_MAX, + 0, + 0); } uint32_t soc_read_sci_irq_select(void) { diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index fe127a2..c729cc8 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -178,6 +178,17 @@ fadt->x_gpe1_blk.space_id = 1; + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm1b_cnt_blk = 0x0; + + fadt->gpe0_blk = pmbase + GPE0_STS(0); + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + soc_fill_fadt(fadt); } diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index d3e2853..fd8b934 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -132,7 +132,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { - u16 pmbase = get_pmbase(); + const u16 pmbase = get_pmbase(); /* System Management */ if (!CONFIG(HAVE_SMI_HANDLER)) { @@ -141,17 +141,6 @@ fadt->acpi_disable = 0x00; } - /* Power Control */ - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe1_blk = 0; - - /* Control Registers - Length */ - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 8; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; fadt->cst_cnt = 0; fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; @@ -171,75 +160,22 @@ ACPI_FADT_RESET_REGISTER | ACPI_FADT_SLEEP_TYPE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - /* Reset Register */ - fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xCF9; - fadt->reset_reg.addrh = 0x00; - fadt->reset_value = 6; - - /* PM1 Status & PM1 Enable */ - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; - fadt->x_pm1a_evt_blk.addrh = 0x00; - - fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; - fadt->x_pm1b_evt_blk.addrh = 0x00; - - /* PM1 Control Registers */ - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; - fadt->x_pm1a_cnt_blk.addrh = 0x00; - - fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; - fadt->x_pm1b_cnt_blk.addrh = 0x00; - - /* PM2 Control Registers */ - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; - fadt->x_pm2_cnt_blk.addrh = 0x00; - - /* PM1 Timer Register */ - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; - fadt->x_pm_tmr_blk.addrh = 0x00; - - /* General-Purpose Event Registers */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x00; - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; - fadt->x_gpe1_blk.addrh = 0x00; + acpi_fill_fadt_x86_pm(fadt, + pmbase + PM1_STS, + 0, + pmbase + PM1_CNT, + 0, + pmbase + PM2_CNT, + pmbase + PM1_TMR, + pmbase + GPE0_STS(0), + 0, + 4, + 2, + 1, + 4, + 2 * GPE0_REG_MAX * sizeof(uint32_t), + 0, + 0); motherboard_fill_fadt(fadt); } diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 550dd56..9e24017 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -234,8 +234,6 @@ const uint16_t pmbase = ACPI_BASE_ADDRESS; config_t *config = config_of_soc(); - fadt->header.revision = get_acpi_table_revision(FADT); - fadt->sci_int = acpi_sci_irq(); fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; @@ -243,23 +241,6 @@ fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0; - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe0_blk = pmbase + GPE0_STS(0); - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ - fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; @@ -282,75 +263,22 @@ if (config->s0ix_enable) fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; - fadt->x_pm_tmr_blk.addrh = 0x0; - - /* - * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. - * The bit_width field intentionally overflows here. - * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which - * seems to work fine on Linux 5.0 and Windows 10. - */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_fadt_x86_pm(fadt, + pmbase + PM1_STS, + 0, + pmbase + PM1_CNT, + 0, + pmbase + PM2_CNT, + pmbase + PM1_TMR, + pmbase + GPE0_STS(0), + 0, + 4, + 2, + 1, + 4, + 2 * GPE0_REG_MAX * sizeof(uint32_t), + 0, + 0); } static void write_c_state_entries(acpi_cstate_t *map, const int *set, size_t max_c_state) diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 48ad374..1688ae3 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -108,19 +108,6 @@ fadt->header.revision = get_acpi_table_revision(FADT); fadt->sci_int = SCI_INT_NUM; - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm1b_cnt_blk = 0x0; - - fadt->gpe0_blk = pmbase + GPE0_STS(0); - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - - /* GPE0 STS/EN pairs each 32 bits wide. */ - fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); - fadt->flush_size = 0x400; /* twice of cache size */ fadt->flush_stride = 0x10; /* Cache line width */ fadt->duty_offset = 1; @@ -129,26 +116,6 @@ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_RESET_REGISTER | ACPI_FADT_PLATFORM_CLOCK; - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.addrl = RST_CNT; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_value = RST_CPU | SYS_RST; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; - - fadt->x_pm1b_evt_blk.space_id = 1; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; - - fadt->x_pm1b_cnt_blk.space_id = 1; - - fadt->x_gpe1_blk.space_id = 1; - if (CONFIG(HAVE_SMI_HANDLER)) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; @@ -165,18 +132,19 @@ fadt->cst_cnt = 0; } - /* General-Purpose Event Registers */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0; - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0; - fadt->x_gpe1_blk.addrh = 0; + acpi_fill_fadt_x86_pm(fadt, + pmbase + PM1_STS, + 0, + pmbase + PM1_CNT, + 0, + 0, + 0, + pmbase + GPE0_STS(0), + 0, + 4, + 2, + 0, + 0, + 2 * GPE0_REG_MAX * sizeof(uint32_t), + 0); } diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index e9edc99..aab93b4 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -247,18 +247,6 @@ fadt->acpi_disable = 0x00; } - /* Power Control */ - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe1_blk = 0; - - /* Control Registers - Length */ - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ - fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; fadt->cst_cnt = 0; fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; @@ -278,75 +266,21 @@ ACPI_FADT_RESET_REGISTER | ACPI_FADT_SLEEP_TYPE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - /* Reset Register */ - fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xCF9; - fadt->reset_reg.addrh = 0x00; - fadt->reset_value = 6; - - /* PM1 Status & PM1 Enable */ - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; - fadt->x_pm1a_evt_blk.addrh = 0x00; - - fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; - fadt->x_pm1b_evt_blk.addrh = 0x00; - - /* PM1 Control Registers */ - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; - fadt->x_pm1a_cnt_blk.addrh = 0x00; - - fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; - fadt->x_pm1b_cnt_blk.addrh = 0x00; - - /* PM2 Control Registers */ - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; - fadt->x_pm2_cnt_blk.addrh = 0x00; - - /* PM1 Timer Register */ - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; - fadt->x_pm_tmr_blk.addrh = 0x00; - - /* General-Purpose Event Registers */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x00; - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; - fadt->x_gpe1_blk.addrh = 0x00; + acpi_fill_fadt_x86_pm(fadt, + pmbase + PM1_STS, + 0, + pmbase + PM1_CNT, + 0, + pmbase + PM2_CNT, + pmbase + PM1_TMR, + pmbase + GPE0_STS(0), + 0, + 4, + 2, + 1, + 4, + 2 * GPE0_REG_MAX * sizeof(uint32_t), + 0); motherboard_fill_fadt(fadt); } @@ -355,8 +289,6 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - fadt->header.revision = get_acpi_table_revision(FADT); - fadt->sci_int = acpi_sci_irq(); /* TODO: enabled SMM mode switch when SMM handlers are set up. @@ -370,23 +302,6 @@ fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0; - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe0_blk = pmbase + GPE0_STS(0); - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ - fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; @@ -406,69 +321,21 @@ ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_fadt_x86_pm(fadt, + pmbase + PM1_STS, + 0, + pmbase + PM1_CNT, + 0, + pmbase + PM2_CNT, + pmbase + PM1_TMR, + pmbase + GPE0_STS(0), + 0, + 4, + 2, + 1, + 4, + 2 * GPE0_REG_MAX * sizeof(uint32_t), + 0); soc_fill_fadt(fadt); } diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 08fbecb..5b3fee6 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -104,22 +104,6 @@ /* RTC_En_En, TMR_En_En, GBL_EN_EN */ outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ - fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS; - fadt->pm1b_evt_blk = 0x0000; - fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS; - fadt->pm1b_cnt_blk = 0x0000; - fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS; - fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS; - fadt->gpe0_blk = GPE0_BLK_ADDRESS; - fadt->gpe1_blk = 0; /* No gpe1 block in hudson1 */ - - fadt->pm1_evt_len = 4; /* 32 bits */ - fadt->pm1_cnt_len = 2; /* 16 bits */ - fadt->pm2_cnt_len = 1; /* 8 bits */ - fadt->pm_tmr_len = 4; /* 32 bits */ - fadt->gpe0_blk_len = 8; /* 64 bits */ - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; @@ -143,17 +127,6 @@ ACPI_FADT_S4_RTC_VALID | ACPI_FADT_REMOTE_POWER_ON; - /* Format is from 5.2.3.1: Generic Address Structure */ - /* reset_reg: see section 4.7.3.6 ACPI 3.0a spec */ - /* 8 bit write of value 0x06 to 0xCF9 in IO space */ - fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0x0; - fadt->reset_value = 6; - fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ @@ -162,66 +135,22 @@ fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff; fadt->x_dsdt_h = ((uint64_t)(uintptr_t)dsdt) >> 32; - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; - fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 8; /* Hudson 1 Pm2Control is 8 bits */ - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS; - fadt->x_pm_tmr_blk.addrh = 0x0; - - - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS; - fadt->x_gpe0_blk.addrh = 0x0; - - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_fadt_x86_pm(fadt, + PM1_EVT_BLK_ADDRESS, + 0x0000, + PM1_CNT_BLK_ADDRESS, + 0x0000, + ACPI_PMA_CNT_BLK_ADDRESS, + PM1_TMR_BLK_ADDRESS, + GPE0_BLK_ADDRESS, + 0, + 4, + 2, + 1, + 4, + 2 * sizeof(uint32_t), + 0, + 0); header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 8573c8b..b7192f9 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -77,23 +77,6 @@ fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ } - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; - fadt->pm1b_evt_blk = 0x0000; - fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; - fadt->pm1b_cnt_blk = 0x0000; - fadt->pm2_cnt_blk = 0x0000; - fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; - fadt->gpe0_blk = ACPI_GPE0_BLK; - fadt->gpe1_blk = 0x0000; /* No gpe1 block in hudson */ - - fadt->pm1_evt_len = 4; /* 32 bits */ - fadt->pm1_cnt_len = 2; /* 16 bits */ - fadt->pm2_cnt_len = 0; - fadt->pm_tmr_len = 4; /* 32 bits */ - fadt->gpe0_blk_len = 8; /* 64 bits */ - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ @@ -116,89 +99,31 @@ ACPI_FADT_S4_RTC_VALID | ACPI_FADT_REMOTE_POWER_ON; - /* Format is from 5.2.3.1: Generic Address Structure */ - /* reset_reg: see section 4.7.3.6 ACPI 3.0a spec */ - /* 8 bit write of value 0x06 to 0xCF9 in IO space */ - fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0x0; - - fadt->reset_value = 6; - - fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ - fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ - fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ fadt->x_firmware_ctl_h = 0; fadt->x_dsdt_l = (u32) dsdt; fadt->x_dsdt_h = 0; - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; - fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - /* * Note: Under this current AMD C state implementation, this is no longer * used and should not be reported to OS. */ - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 0; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = 0; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; - fadt->x_pm_tmr_blk.addrh = 0x0; - - - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; - fadt->x_gpe0_blk.addrh = 0x0; - - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_fadt_x86_pm(fadt, + ACPI_PM_EVT_BLK, + 0x0000, + ACPI_PM1_CNT_BLK, + 0x0000, + 0x0000, + ACPI_PM_TMR_BLK, + ACPI_GPE0_BLK, + 0x0000, + 4, + 2, + 0, + 4, + 2 * sizeof(uint32_t), + 0, + 0); header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); } diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 46ab5fc..9aec7db 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -717,22 +717,6 @@ fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0; - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; fadt->cst_cnt = 0; c2_latency = chip->c2_latency; if (!c2_latency) { @@ -765,70 +749,22 @@ fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED; } - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_fadt_x86_pm(fadt, + pmbase, + 0x0, + pmbase + 0x4, + 0x0, + pmbase + 0x50, + pmbase + 0x8, + pmbase + 0x20, + 0, + 4, + 2, + 1, + 4, + 2 * 2 * sizeof(uint32_t), + 0, + 0); } static const char *lpc_acpi_name(const struct device *dev) diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index db1071a..4b27b97 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -52,25 +52,6 @@ fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0x0; - fadt->pm1a_evt_blk = DEFAULT_PMBASE; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = DEFAULT_PMBASE + PMCNTRL; - fadt->pm1b_cnt_blk = 0x0; - - fadt->pm2_cnt_blk = 0; - fadt->pm_tmr_blk = DEFAULT_PMBASE + PMTMR; - fadt->gpe0_blk = DEFAULT_PMBASE + GPSTS; - fadt->gpe1_blk = 0x0; - fadt->gpe1_base = 0; - fadt->gpe1_blk_len = 0; - - /* *_len define register width in bytes */ - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 0; /* not supported */ - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 4; - fadt->cst_cnt = 0; /* smi command to indicate c state changed notification */ fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */ fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */ @@ -141,74 +122,22 @@ */ fadt->flags = 0xa5; - fadt->reset_reg.space_id = 0; - fadt->reset_reg.bit_width = 0; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = 0; - fadt->reset_reg.addrl = 0x0; - fadt->reset_reg.addrh = 0x0; - fadt->reset_value = 0; - - fadt->x_firmware_ctl_l = (uintptr_t)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (uintptr_t)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = 0; - fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_fadt_x86_pm(fadt, + DEFAULT_PMBASE, + 0, + DEFAULT_PMBASE + PMCNTRL, + 0, + 0, + DEFAULT_PMBASE + PMTMR, + DEFAULT_PMBASE + GPSTS, + 0, + 4, + 2, + 0, + 4, + 2 * sizeof(uint16_t), + 0, + 0); header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); } diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 743dbba..8977228 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -452,87 +452,6 @@ config_t *chip = dev->chip_info; u16 pmbase = lpc_get_pmbase(); - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe0_blk = pmbase + GPE0_STS; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 8; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 0; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 0; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 0; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x32; @@ -562,6 +481,23 @@ | ACPI_FADT_C2_MP_SUPPORTED); if (chip->docking_supported) fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; + + acpi_fill_fadt_x86_pm(fadt, + pmbase, + 0, + pmbase + PM1_CNT, + 0, + pmbase + PM2_CNT, + pmbase + PM1_TMR, + pmbase + GPE0_STS, + 0, + 4, + 2, + 1, + 4, + 2 * sizeof(uint32_t), + 0, + 0); } static void i82801gx_lpc_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index e3fdde7..ae40a42 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -460,86 +460,6 @@ config_t *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 0; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 0; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 0; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x32; @@ -569,6 +489,23 @@ | ACPI_FADT_C2_MP_SUPPORTED); if (chip->docking_supported) fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; + + acpi_fill_fadt_x86_pm(fadt, + pmbase, + 0, + pmbase + 0x4, + 0, + pmbase + 0x50, + pmbase + 0x8, + pmbase + 0x20, + 0, + 4, + 2, + 1, + 4, + 2 * 2 * sizeof(uint32_t), + 0, + 0); } static void i82801jx_lpc_read_resources(struct device *dev) diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 0062e09..29a263a 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -617,22 +617,6 @@ fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0; - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; fadt->cst_cnt = 0; c2_latency = chip->c2_latency; if (!c2_latency) { @@ -664,70 +648,22 @@ fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED; } - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_fadt_x86_pm(fadt, + pmbase, + 0, + pmbase + 0x4, + 0, + pmbase + 0x50, + pmbase + 0x8, + pmbase + 0x20, + 0, + 4, + 2, + 1, + 4, + 2 * 2 * sizeof(uint32_t), + 0, + 0); } static const char *lpc_acpi_name(const struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 0bfca35..589c4fa 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -767,35 +767,6 @@ fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0; - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - if (pch_is_lp()) - fadt->gpe0_blk = pmbase + LP_GPE0_STS_1; - else - fadt->gpe0_blk = pmbase + GPE0_STS; - fadt->gpe1_blk = 0; - - /* - * Some of the lengths here are doubled. This is because they describe - * blocks containing two registers, where the size of each register - * is found by halving the block length. See Table 5-34 and section - * 4.8.3 of the ACPI specification for details. - */ - fadt->pm1_evt_len = 2 * 2; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - if (pch_is_lp()) - fadt->gpe0_blk_len = 2 * 16; - else - fadt->gpe0_blk_len = 2 * 8; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; @@ -820,76 +791,21 @@ if (cfg->docking_supported) fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; - fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = 2 * 16; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; - fadt->x_pm_tmr_blk.addrh = 0x0; - - /* - * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. - * The bit_width field intentionally overflows here. - * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which - * seems to work fine on Linux 5.0 and Windows 10. - */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_fadt_x86_pm(fadt, + pmbase + PM1_STS, + 0, + pmbase + PM1_CNT, + 0, + pmbase + PM2_CNT, + pmbase + PM1_TMR, + pch_is_lp() ? (pmbase + LP_GPE0_STS_1) : (pmbase + GPE0_STS), + 0, + 4, + 2, + 1, + 4, + pch_is_lp() ? (2 * 4 * sizeof(uint32_t)) : (2 * 2 * sizeof(uint32_t)), + 0); } static const char *lpc_acpi_name(const struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/40036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If58fcf9a1c39c159dfa08339cb931e552d499747 Gerrit-Change-Number: 40036 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: [WIP] soc/amd/common: Use configure_scimap()
by Kyösti Mälkki (Code Review) 15 Apr '21

15 Apr '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43012 ) Change subject: [WIP] soc/amd/common: Use configure_scimap() ...................................................................... [WIP] soc/amd/common: Use configure_scimap() There is little point stashing the SCI trigger register configuration. Remove it to mase SCI and SMI programming more symmetrical. Change-Id: Ie23da79546858282910db65182a6315ade506279 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/gpio_banks/gpio.c 1 file changed, 12 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/43012/1 diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 1bcfc8b..141d04f 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -40,12 +40,6 @@ configure_gevent_smi(gevent_num, SMI_MODE_SMI, level); } -struct sci_trigger_regs { - uint32_t mask; - uint32_t polarity; - uint32_t level; -}; - /* * For each general purpose event, GPE, the choice of edge/level triggered * event is represented as a single bit in SMI_SCI_LEVEL register. @@ -53,37 +47,24 @@ * In a similar fashion, polarity (rising/falling, hi/lo) of each GPE is * represented as a single bit in SMI_SCI_TRIG register. */ -static void fill_sci_trigger(uint32_t flags, int gpe, struct sci_trigger_regs *regs) +static void program_sci(uint32_t flags, int gevent_num) { - uint32_t mask = 1 << gpe; + struct sci_source sci; - regs->mask |= mask; + sci.scimap = gevent_num; + sci.gpe = gevent_num; if (is_gpio_event_level_triggered(flags)) - regs->level |= mask; + sci.level = SMI_SCI_LVL; else - regs->level &= ~mask; + sci.level = SMI_SCI_EDG; if (is_gpio_event_active_high(flags)) - regs->polarity |= mask; + sci.direction = SMI_SCI_LVL_HIGH; else - regs->polarity &= ~mask; -} + sci.direction = SMI_SCI_LVL_LOW; -/* TODO: See configure_scimap() implementations. */ -static void set_sci_trigger(const struct sci_trigger_regs *regs) -{ - uint32_t value; - - value = smi_read32(SMI_SCI_TRIG); - value &= ~regs->mask; - value |= regs->polarity; - smi_write32(SMI_SCI_TRIG, value); - - value = smi_read32(SMI_SCI_LEVEL); - value &= ~regs->mask; - value |= regs->level; - smi_write32(SMI_SCI_LEVEL, value); + configure_scimap(&sci); } uintptr_t gpio_get_address(gpio_t gpio_num) @@ -175,7 +156,7 @@ __weak void soc_gpio_hook(uint8_t gpio, uint8_t mux) {} -static void set_single_gpio(const struct soc_amd_gpio *g, struct sci_trigger_regs *sci_cfg) +static void set_single_gpio(const struct soc_amd_gpio *g) { static const struct soc_amd_event *gev_tbl; static size_t gev_items; @@ -206,14 +187,12 @@ if (g->flags & GPIO_FLAG_SMI) { program_smi(g->flags, gevent_num); } else if (g->flags & GPIO_FLAG_SCI) { - fill_sci_trigger(g->flags, gevent_num, sci_cfg); - soc_route_sci(gevent_num); + program_sci(g->flags, gevent_num); } } void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) { - struct sci_trigger_regs sci_trigger_cfg = { 0 }; size_t i; /* @@ -229,7 +208,7 @@ master_switch_clr(GPIO_MASK_STS_EN | GPIO_INTERRUPT_EN); for (i = 0; i < size; i++) - set_single_gpio(&gpio_list_ptr[i], &sci_trigger_cfg); + set_single_gpio(&gpio_list_ptr[i]); /* * Re-enable interrupt status generation. @@ -239,9 +218,6 @@ * to be missed during boot. */ master_switch_set(GPIO_INTERRUPT_EN); - - /* Set all SCI trigger polarity (high/low) and level (edge/level). */ - set_sci_trigger(&sci_trigger_cfg); } int gpio_interrupt_status(gpio_t gpio) -- To view, visit https://review.coreboot.org/c/coreboot/+/43012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie23da79546858282910db65182a6315ade506279 Gerrit-Change-Number: 43012 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: herobrine : Provide initial mainboard support
by Ravi kumar (Code Review) 15 Apr '21

15 Apr '21

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45206 ) Change subject: herobrine : Provide initial mainboard support ...................................................................... herobrine : Provide initial mainboard support Change-Id: I428cf1a461ee63215f5683abbfed90202d1b2a88 Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> --- M payloads/libpayload/Kconfig A payloads/libpayload/configs/config.herobrine M payloads/libpayload/drivers/Makefile.inc A payloads/libpayload/drivers/serial/sc7280.c A src/mainboard/google/herobrine/Kconfig A src/mainboard/google/herobrine/Kconfig.name A src/mainboard/google/herobrine/Makefile.inc A src/mainboard/google/herobrine/board.h A src/mainboard/google/herobrine/board_info.txt A src/mainboard/google/herobrine/boardid.c A src/mainboard/google/herobrine/bootblock.c A src/mainboard/google/herobrine/chromeos.c A src/mainboard/google/herobrine/chromeos.fmd A src/mainboard/google/herobrine/devicetree.cb A src/mainboard/google/herobrine/mainboard.c A src/mainboard/google/herobrine/reset.c A src/mainboard/google/herobrine/romstage.c 17 files changed, 319 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/45206/1 diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index b5dc9a3..43ba6ab 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -256,6 +256,11 @@ depends on SERIAL_CONSOLE default n +config SC7280_SERIAL_CONSOLE + bool "SC7280 SOC compatible serial port driver" + depends on SERIAL_CONSOLE + default n + config QUALCOMM_QUPV3_SERIAL_CONSOLE bool "Qualcomm QUPV3 serial port driver" depends on SERIAL_CONSOLE diff --git a/payloads/libpayload/configs/config.herobrine b/payloads/libpayload/configs/config.herobrine new file mode 100644 index 0000000..a9d576a --- /dev/null +++ b/payloads/libpayload/configs/config.herobrine @@ -0,0 +1,5 @@ +CONFIG_LP_CHROMEOS=y +CONFIG_LP_ARCH_ARM64=y +CONFIG_LP_TIMER_ARM64_ARCH=y +CONFIG_LP_SERIAL_CONSOLE=y +CONFIG_LP_SC7280_SERIAL_CONSOLE=y diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index c4f7bf6..6c54c49 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -42,6 +42,8 @@ libc-$(CONFIG_LP_PC_MOUSE) += i8042/mouse.c libc-$(CONFIG_LP_PC_I8042) += i8042/i8042.c +libc-$(CONFIG_LP_SC7280_SERIAL_CONSOLE) += serial/sc7280.c serial/serial.c + libc-$(CONFIG_LP_CBMEM_CONSOLE) += cbmem_console.c libc-$(CONFIG_LP_MOUSE_CURSOR) += mouse_cursor.c diff --git a/payloads/libpayload/drivers/serial/sc7280.c b/payloads/libpayload/drivers/serial/sc7280.c new file mode 100644 index 0000000..0d7f5cf --- /dev/null +++ b/payloads/libpayload/drivers/serial/sc7280.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <libpayload.h> + +/* For simplicity sake let's rely on coreboot initalizing the UART. */ +void serial_console_init(void) +{ + +} diff --git a/src/mainboard/google/herobrine/Kconfig b/src/mainboard/google/herobrine/Kconfig new file mode 100644 index 0000000..92f77db --- /dev/null +++ b/src/mainboard/google/herobrine/Kconfig @@ -0,0 +1,55 @@ + +config BOARD_GOOGLE_HEROBRINE_COMMON # Umbrella option to be selected by variants + def_bool n + +if BOARD_GOOGLE_HEROBRINE_COMMON + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select COMMON_CBFS_SPI_WRAPPER + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_RTC + select EC_GOOGLE_CHROMEEC_SPI + select RTC + select SOC_QUALCOMM_SC7280 + select SPI_FLASH + select SPI_FLASH_WINBOND + select MAINBOARD_HAS_CHROMEOS + +config VBOOT + select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_VBNV_FLASH + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select VBOOT_MOCK_SECDATA + +config MAINBOARD_DIR + string + default "google/herobrine" + +config MAINBOARD_VENDOR + string + default "Google" + +config DRIVER_TPM_SPI_BUS + hex + default 0x5 + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0xa + +########################################################## +#### Update below when adding a new derivative board. #### +########################################################## + +config MAINBOARD_PART_NUMBER + string + default "Herobrine" if BOARD_GOOGLE_HEROBRINE + +config GBB_HWID + string + depends on CHROMEOS + default "HEROBRINE TEST 1859" if BOARD_GOOGLE_HEROBRINE + +endif # BOARD_GOOGLE_HEROBRINE_COMMON diff --git a/src/mainboard/google/herobrine/Kconfig.name b/src/mainboard/google/herobrine/Kconfig.name new file mode 100644 index 0000000..13dc56a --- /dev/null +++ b/src/mainboard/google/herobrine/Kconfig.name @@ -0,0 +1,4 @@ + +config BOARD_GOOGLE_HEROBRINE + bool "Herobrine" + select BOARD_GOOGLE_HEROBRINE_COMMON diff --git a/src/mainboard/google/herobrine/Makefile.inc b/src/mainboard/google/herobrine/Makefile.inc new file mode 100644 index 0000000..949d775 --- /dev/null +++ b/src/mainboard/google/herobrine/Makefile.inc @@ -0,0 +1,20 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += boardid.c +bootblock-y += chromeos.c +bootblock-y += bootblock.c +bootblock-y += reset.c + +verstage-y += boardid.c +verstage-y += chromeos.c +verstage-y += reset.c + +romstage-y += boardid.c +romstage-y += chromeos.c +romstage-y += romstage.c +romstage-y += reset.c + +ramstage-y += boardid.c +ramstage-y += chromeos.c +ramstage-y += mainboard.c +ramstage-y += reset.c diff --git a/src/mainboard/google/herobrine/board.h b/src/mainboard/google/herobrine/board.h new file mode 100644 index 0000000..c69d5d2 --- /dev/null +++ b/src/mainboard/google/herobrine/board.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ +#define _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ + +#include <boardid.h> +#include <gpio.h> +#include <soc/gpio.h> + +#define GPIO_EC_IN_RW GPIO(118) +#define GPIO_AP_EC_INT GPIO(94) +#define GPIO_AP_SUSPEND GPIO(20) +#define GPIO_WP_STATE GPIO(42) +#define GPIO_H1_AP_INT (CONFIG(TROGDOR_REV0) ? GPIO(21) : GPIO(42)) +#define GPIO_SD_CD_L GPIO(69) +#define GPIO_AMP_ENABLE GPIO(23) + +/* Display specific GPIOS */ +#define GPIO_BACKLIGHT_ENABLE GPIO(12) +#define GPIO_EDP_BRIDGE_ENABLE (CONFIG(TROGDOR_REV0) ? GPIO(14) : GPIO(104)) +#define GPIO_EN_PP3300_DX_EDP (CONFIG(TROGDOR_REV0) ? GPIO(106) : GPIO(30)) + +void setup_chromeos_gpios(void); + +#endif /* _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ */ diff --git a/src/mainboard/google/herobrine/board_info.txt b/src/mainboard/google/herobrine/board_info.txt new file mode 100644 index 0000000..a670d6e --- /dev/null +++ b/src/mainboard/google/herobrine/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Herobrine Qualcomm sc7280 reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/herobrine/boardid.c b/src/mainboard/google/herobrine/boardid.c new file mode 100644 index 0000000..7ff648e --- /dev/null +++ b/src/mainboard/google/herobrine/boardid.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boardid.h> +#include <gpio.h> + +uint32_t board_id(void) +{ + static uint32_t id = UNDEFINED_STRAPPING_ID; +#if 0 + /* TODO: update gpios for Herobrine */ + const gpio_t pins[] = {[2] = GPIO(31), [1] = GPIO(93), [0] = GPIO(33)}; + + if (id == UNDEFINED_STRAPPING_ID) + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); +#endif + return id; +} + +uint32_t ram_code(void) +{ + static uint32_t id = UNDEFINED_STRAPPING_ID; +#if 0 + /* TODO: update gpios for Herobrine */ + const gpio_t pins[] = {[2] = GPIO(13), [1] = GPIO(19), [0] = GPIO(29)}; + + if (id == UNDEFINED_STRAPPING_ID) + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); +#endif + return id; +} + +uint32_t sku_id(void) +{ + static uint32_t id = UNDEFINED_STRAPPING_ID; +#if 0 + /* TODO: update gpios for Herobrine */ + const gpio_t pins[] = {[2] = GPIO(20), [1] = GPIO(90), [0] = GPIO(105)}; + + if (id == UNDEFINED_STRAPPING_ID) + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); +#endif + return id; +} diff --git a/src/mainboard/google/herobrine/bootblock.c b/src/mainboard/google/herobrine/bootblock.c new file mode 100644 index 0000000..05e53a6 --- /dev/null +++ b/src/mainboard/google/herobrine/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include "board.h" + +void bootblock_mainboard_init(void) +{ + setup_chromeos_gpios(); +} diff --git a/src/mainboard/google/herobrine/chromeos.c b/src/mainboard/google/herobrine/chromeos.c new file mode 100644 index 0000000..dba1c09 --- /dev/null +++ b/src/mainboard/google/herobrine/chromeos.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boot/coreboot_tables.h> +#include <bootmode.h> +#include "board.h" + +int get_write_protect_state(void) +{ +#if 0 + return !gpio_get(GPIO_WP_STATE); +#else + return 0; +#endif +} + +void setup_chromeos_gpios(void) +{ +#if 0 + /* Example of what needs to be done here */ + gpio_input_pullup(GPIO_EC_IN_RW); + gpio_input_pullup(GPIO_AP_EC_INT); + gpio_input_pullup(GPIO_SD_CD_L); + gpio_input_irq(GPIO_H1_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP); + gpio_output(GPIO_AMP_ENABLE, 0); +#endif +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ +#if 0 + /* Example of what needs to be done here */ + struct lb_gpio chromeos_gpios[] = { + {GPIO_EC_IN_RW.addr, ACTIVE_LOW, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, + {GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT), + "EC interrupt"}, + {GPIO_H1_AP_INT.addr, ACTIVE_LOW, gpio_get(GPIO_H1_AP_INT), + "TPM interrupt"}, + {GPIO_SD_CD_L.addr, ACTIVE_LOW, gpio_get(GPIO_SD_CD_L), + "SD card detect"}, + {GPIO_AMP_ENABLE.addr, ACTIVE_HIGH, gpio_get(GPIO_AMP_ENABLE), + "speaker enable"}, + }; + + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +#endif +} diff --git a/src/mainboard/google/herobrine/chromeos.fmd b/src/mainboard/google/herobrine/chromeos.fmd new file mode 100644 index 0000000..a44a638 --- /dev/null +++ b/src/mainboard/google/herobrine/chromeos.fmd @@ -0,0 +1,41 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# TODO: update for Herobrine +FLASH@0x0 8M { + WP_RO 4M { + RO_SECTION 0x3c4000 { + BOOTBLOCK 96K + COREBOOT(CBFS) + FMAP@0x3c0000 0x1000 + GBB 0x2f00 + RO_FRID 0x100 + } + RO_VPD(PRESERVE) 228K + RO_DDR_TRAINING(PRESERVE) 8K + RO_LIMITS_CFG(PRESERVE) 4K + } + + RW_VPD(PRESERVE) 32K + RW_NVRAM(PRESERVE) 16K + RW_DDR_TRAINING(PRESERVE) 8K + RW_LIMITS_CFG(PRESERVE) 4K + RW_ELOG(PRESERVE) 4K + RW_SHARED 4K { + SHARED_DATA + } + + RW_SECTION_A 1280K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 + } + + + RW_SECTION_B 1280K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 + } + + RW_LEGACY(CBFS) +} diff --git a/src/mainboard/google/herobrine/devicetree.cb b/src/mainboard/google/herobrine/devicetree.cb new file mode 100644 index 0000000..e23782f --- /dev/null +++ b/src/mainboard/google/herobrine/devicetree.cb @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/qualcomm/sc7280 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c new file mode 100644 index 0000000..31deb77 --- /dev/null +++ b/src/mainboard/google/herobrine/mainboard.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <bootblock_common.h> +#include <arch/mmio.h> +#include <gpio.h> +#include <timestamp.h> + +static void mainboard_init(struct device *dev) +{ + +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/herobrine/reset.c b/src/mainboard/google/herobrine/reset.c new file mode 100644 index 0000000..9b5810f --- /dev/null +++ b/src/mainboard/google/herobrine/reset.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/google/chromeec/ec.h> +#include <reset.h> + +/* Can't do a "real" reset before the PMIC is initialized in QcLib (romstage), + but this works well enough for our purposes. */ +void do_board_reset(void) +{ + google_chromeec_reboot(0, EC_REBOOT_COLD, 0); +} diff --git a/src/mainboard/google/herobrine/romstage.c b/src/mainboard/google/herobrine/romstage.c new file mode 100644 index 0000000..8844f18 --- /dev/null +++ b/src/mainboard/google/herobrine/romstage.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/stages.h> +#include <soc/qclib_common.h> + +void platform_romstage_main(void) +{ + /* QCLib: DDR init & train */ + qclib_load_and_run(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I428cf1a461ee63215f5683abbfed90202d1b2a88 Gerrit-Change-Number: 45206 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

9 61

Change in coreboot[master]: sc7280: Provide initial SoC support
by Ravi kumar (Code Review) 15 Apr '21

15 Apr '21

Hello mturney mturney, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45205 to review the following change. Change subject: sc7280: Provide initial SoC support ...................................................................... sc7280: Provide initial SoC support Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/include/soc/symbols.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/qclib.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c A src/soc/qualcomm/sc7280/timer.c 16 files changed, 319 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45205/1 diff --git a/Documentation/soc/qualcomm/index.md b/Documentation/soc/qualcomm/index.md index 5cd7981..d177c0e 100644 --- a/Documentation/soc/qualcomm/index.md +++ b/Documentation/soc/qualcomm/index.md @@ -5,3 +5,4 @@ ## Platforms - [SC7180 series](sc7180/index.md) +- [SC7280 series](sc7280/index.md) diff --git a/Documentation/soc/qualcomm/sc7280/index.md b/Documentation/soc/qualcomm/sc7280/index.md new file mode 100644 index 0000000..9dad39c --- /dev/null +++ b/Documentation/soc/qualcomm/sc7280/index.md @@ -0,0 +1,19 @@ +# Qualcomm SC7280 documentation + +## SOC code + +The SOC folder contains functions for: +* MMU +* CLOCK +* GPIO +* QUPv3 FW (provides a bridge to serial interfaces) +* UART +* SPI-NOR +* AOP FW +* USB + +## Notes about the hardware + +The timer is used from the ARMv8 architecture specific code. + + diff --git a/src/soc/qualcomm/sc7280/Kconfig b/src/soc/qualcomm/sc7280/Kconfig new file mode 100644 index 0000000..fc2f34b --- /dev/null +++ b/src/soc/qualcomm/sc7280/Kconfig @@ -0,0 +1,27 @@ + +config SOC_QUALCOMM_SC7280 + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select GENERIC_GPIO_LIB + select GENERIC_UDELAY + select HAVE_MONOTONIC_TIMER + select ARM64_USE_ARCH_TIMER + select SOC_QUALCOMM_COMMON + +if SOC_QUALCOMM_SC7280 + +config MEMLAYOUT_LD_FILE + string + default "src/soc/qualcomm/sc7280/memlayout.ld" + +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + +endif diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc new file mode 100644 index 0000000..2bed326 --- /dev/null +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -0,0 +1,36 @@ + +ifeq ($(CONFIG_SOC_QUALCOMM_SC7280),y) + +################################################################################ +bootblock-y += bootblock.c +bootblock-y += mmu.c +bootblock-y += timer.c +bootblock-y += spi.c + +################################################################################ +verstage-y += timer.c +verstage-y += spi.c + +################################################################################ +romstage-y += cbmem.c +romstage-y += timer.c +romstage-y += ../common/qclib.c +romstage-y += qclib.c +romstage-y += ../common/mmu.c +romstage-y += mmu.c +romstage-y += spi.c + +################################################################################ +ramstage-y += soc.c +ramstage-y += cbmem.c +ramstage-y += timer.c +ramstage-y += spi.c + +################################################################################ + +CPPFLAGS_common += -Isrc/soc/qualcomm/sc7280/include +CPPFLAGS_common += -Isrc/soc/qualcomm/common/include + +################################################################################ + +endif diff --git a/src/soc/qualcomm/sc7280/bootblock.c b/src/soc/qualcomm/sc7280/bootblock.c new file mode 100644 index 0000000..807bb25 --- /dev/null +++ b/src/soc/qualcomm/sc7280/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <soc/mmu.h> + +void bootblock_soc_init(void) +{ + sc7280_mmu_init(); +} diff --git a/src/soc/qualcomm/sc7280/cbmem.c b/src/soc/qualcomm/sc7280/cbmem.c new file mode 100644 index 0000000..4b9eb37 --- /dev/null +++ b/src/soc/qualcomm/sc7280/cbmem.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> + +void *cbmem_top_chipset(void) +{ + return (void *)((uintptr_t)4 * GiB); +} diff --git a/src/soc/qualcomm/sc7280/include/soc/addressmap.h b/src/soc/qualcomm/sc7280/include/soc/addressmap.h new file mode 100644 index 0000000..70d17be --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/addressmap.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_SC7280_ADDRESS_MAP_H_ +#define _SOC_QUALCOMM_SC7280_ADDRESS_MAP_H_ + +#include <stdint.h> + +#endif /* __SOC_QUALCOMM_SC7280_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7280/include/soc/gpio.h b/src/soc/qualcomm/sc7280/include/soc/gpio.h new file mode 100644 index 0000000..82a0c39 --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/gpio.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_SC7280_GPIO_H_ +#define _SOC_QUALCOMM_SC7280_GPIO_H_ + +#include <types.h> + +typedef struct { + u32 addr; +} gpio_t; + +#endif /* _SOC_QUALCOMM_SC7280_GPIO_H_ */ diff --git a/src/soc/qualcomm/sc7280/include/soc/mmu.h b/src/soc/qualcomm/sc7280/include/soc/mmu.h new file mode 100644 index 0000000..5a2984f --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/mmu.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_SC7280_MMU_H_ +#define _SOC_QUALCOMM_SC7280_MMU_H_ + +void sc7280_mmu_init(void); + +#endif /* _SOC_QUALCOMM_SC7280_MMU_H_ */ diff --git a/src/soc/qualcomm/sc7280/include/soc/symbols.h b/src/soc/qualcomm/sc7280/include/soc/symbols.h new file mode 100644 index 0000000..e930638 --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/symbols.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_SC7280_SYMBOLS_H_ +#define _SOC_QUALCOMM_SC7280_SYMBOLS_H_ + +#include <symbols.h> + +DECLARE_REGION(ssram) +DECLARE_REGION(bsram) +DECLARE_REGION(dram_aop) +DECLARE_REGION(dram_soc) +DECLARE_REGION(dcb) +DECLARE_REGION(pmic) +DECLARE_REGION(limits_cfg) +DECLARE_REGION(aop) + +#endif /* _SOC_QUALCOMM_SC7280_SYMBOLS_H_ */ diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld new file mode 100644 index 0000000..94300e8 --- /dev/null +++ b/src/soc/qualcomm/sc7280/memlayout.ld @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <memlayout.h> +#include <arch/header.ld> + +/* SYSTEM_IMEM : 0x14680000 - 0x146AE000 */ +#define SSRAM_START(addr) SYMBOL(ssram, addr) +#define SSRAM_END(addr) SYMBOL(essram, addr) + +/* BOOT_IMEM : 0x14800000 - 0x14980000 */ +#define BSRAM_START(addr) SYMBOL(bsram, addr) +#define BSRAM_END(addr) SYMBOL(ebsram, addr) + +/* AOP : 0x0B000000 - 0x0B100000 */ +#define AOPSRAM_START(addr) SYMBOL(aopsram, addr) +#define AOPSRAM_END(addr) SYMBOL(eaopsram, addr) + +SECTIONS +{ + AOPSRAM_START(0x0B000000) + REGION(aop, 0x0B000000, 0x100000, 4096) + AOPSRAM_END(0x0B100000) + + SSRAM_START(0x14680000) + OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) + REGION(qcsdi, 0x14699000, 52K, 4K) + SSRAM_END(0x146AE000) + + BSRAM_START(0x14800000) + REGION(pbl_timestamps, 0x14800000, 84K, 4K) + BOOTBLOCK(0x14815000, 40K) + PRERAM_CBFS_CACHE(0x1481F000, 70K) + PRERAM_CBMEM_CONSOLE(0x14830800, 32K) + TIMESTAMP(0x14838800, 1K) + TTB(0x14839000, 56K) + STACK(0x14847000, 16K) + VBOOT2_WORK(0x1484B000, 12K) + DMA_COHERENT(0x1484E000, 8K) + REGION(ddr_training, 0x14850000, 8K, 4K) + REGION(qclib_serial_log, 0x14852000, 4K, 4K) + REGION(ddr_information, 0x14853000, 1K, 1K) + FMAP_CACHE(0x14853400, 2K) + REGION(dcb, 0x1485b000, 16K, 4K) + REGION(pmic, 0x1485f000, 44K, 4K) + REGION(limits_cfg, 0x1486a000, 4K, 4K) + REGION(qclib, 0x1486b000, 596K, 4K) + BSRAM_END(0x14900000) + + DRAM_START(0x80000000) + /* Various hardware/software subsystems make use of this area */ + REGION(dram_aop, 0x80800000, 0x040000, 0x1000) + REGION(dram_soc, 0x80900000, 0x200000, 0x1000) + BL31(0x80B00000, 1M) + POSTRAM_CBFS_CACHE(0x9F800000, 16M) + RAMSTAGE(0xA0800000, 16M) +} diff --git a/src/soc/qualcomm/sc7280/mmu.c b/src/soc/qualcomm/sc7280/mmu.c new file mode 100644 index 0000000..9905c29 --- /dev/null +++ b/src/soc/qualcomm/sc7280/mmu.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <symbols.h> +#include <arch/mmu.h> +#include <arch/cache.h> +#include <soc/mmu.h> +#include <soc/mmu_common.h> +#include <soc/symbols.h> + +void sc7280_mmu_init(void) +{ + mmu_init(); + + mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), DEV_MEM); + mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM); + mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM); + mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent), + UNCACHED_RAM); + + mmu_enable(); +} diff --git a/src/soc/qualcomm/sc7280/qclib.c b/src/soc/qualcomm/sc7280/qclib.c new file mode 100644 index 0000000..6affc63 --- /dev/null +++ b/src/soc/qualcomm/sc7280/qclib.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbfs.h> +#include <fmap.h> +#include <console/console.h> +#include <soc/symbols.h> +#include <soc/qclib_common.h> + +int qclib_soc_blob_load(void) +{ + size_t size; + ssize_t ssize; + + /* Attempt to load PMICCFG Blob */ + size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg", + _pmic, REGION_SIZE(pmic), CBFS_TYPE_RAW); + if (!size) + return -1; + qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, size, 0); + + /* Attempt to load DCB Blob */ + size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/dcb", + _dcb, REGION_SIZE(dcb), CBFS_TYPE_RAW); + if (!size) + return -1; + qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, size, 0); + + /* Attempt to load Limits Config Blob */ + ssize = fmap_read_area(QCLIB_FR_LIMITS_CFG_DATA, _limits_cfg, + REGION_SIZE(limits_cfg)); + if (ssize < 0) + return -1; + qclib_add_if_table_entry(QCLIB_TE_LIMITS_CFG_DATA, + _limits_cfg, ssize, 0); + + return 0; +} diff --git a/src/soc/qualcomm/sc7280/soc.c b/src/soc/qualcomm/sc7280/soc.c new file mode 100644 index 0000000..7233d38 --- /dev/null +++ b/src/soc/qualcomm/sc7280/soc.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <symbols.h> +#include <device/device.h> +#include <soc/mmu.h> +#include <soc/mmu_common.h> +#include <soc/symbols.h> + +static void soc_read_resources(struct device *dev) +{ + ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB, + ddr_region->size / KiB); + reserved_ram_resource(dev, 1, (uintptr_t)_dram_soc / KiB, + REGION_SIZE(dram_soc) / KiB); +} + +static void soc_init(struct device *dev) +{ +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(struct device *dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_qualcomm_sc7280_ops = { + CHIP_NAME("SOC Qualcomm SC7280") + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/qualcomm/sc7280/spi.c b/src/soc/qualcomm/sc7280/spi.c new file mode 100644 index 0000000..50aa395 --- /dev/null +++ b/src/soc/qualcomm/sc7280/spi.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <spi-generic.h> +#include <spi_flash.h> + +static const struct spi_ctrlr spi_ctrlr; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/qualcomm/sc7280/timer.c b/src/soc/qualcomm/sc7280/timer.c new file mode 100644 index 0000000..19e466a --- /dev/null +++ b/src/soc/qualcomm/sc7280/timer.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> +#include <arch/lib_helpers.h> +#include <commonlib/helpers.h> + +void init_timer(void) +{ + raw_write_cntfrq_el0(19200*KHz); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Gerrit-Change-Number: 45205 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c/tas5825m: Add driver for TI TAS5825M amplifier
by Jeremy Soller (Code Review) 15 Apr '21

15 Apr '21

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43614 ) Change subject: drivers/i2c/tas5825m: Add driver for TI TAS5825M amplifier ...................................................................... drivers/i2c/tas5825m: Add driver for TI TAS5825M amplifier This adds a driver for the TI TAS5825M, documentation can be found here: https://www.ti.com/product/TAS5825M This driver expects the mainboard using it to define tas5825m_setup, which uses the tas5825m_* functions to set configuration data. Each mainboard may have very different configuration data, depending on its audio hardware. Tested on system76/addw2 and system76/oryp6, which will be added in a future patch. Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Change-Id: I896e8f272f18e64bfc90f406e7d4163010800aaf --- A src/drivers/i2c/tas5825m/Kconfig A src/drivers/i2c/tas5825m/Makefile.inc A src/drivers/i2c/tas5825m/tas5825m.c A src/drivers/i2c/tas5825m/tas5825m.h 4 files changed, 81 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/43614/1 diff --git a/src/drivers/i2c/tas5825m/Kconfig b/src/drivers/i2c/tas5825m/Kconfig new file mode 100644 index 0000000..0deca17 --- /dev/null +++ b/src/drivers/i2c/tas5825m/Kconfig @@ -0,0 +1,5 @@ +config DRIVERS_I2C_TAS5825M + bool + default n + help + Enable support for TI TAS5825M Amplifier. diff --git a/src/drivers/i2c/tas5825m/Makefile.inc b/src/drivers/i2c/tas5825m/Makefile.inc new file mode 100644 index 0000000..909ffdb --- /dev/null +++ b/src/drivers/i2c/tas5825m/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += tas5825m.c diff --git a/src/drivers/i2c/tas5825m/tas5825m.c b/src/drivers/i2c/tas5825m/tas5825m.c new file mode 100644 index 0000000..2970a8ee --- /dev/null +++ b/src/drivers/i2c/tas5825m/tas5825m.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/smbus.h> +#include <device/pci.h> +#include "tas5825m.h" + +int tas5825m_write_at(struct device *dev, uint8_t addr, uint8_t value) { + return smbus_write_byte(dev, addr, value); +} + +//TODO: use I2C block write for better performance +int tas5825m_write_block_at(struct device *dev, uint8_t addr, const uint8_t * values, uint8_t length) { + int res = 0; + for (uint8_t i = 0; i < length; i++) { + res = smbus_write_byte(dev, addr + i, values[i]); + if (res < 0) return res; + } + return (int)length; +} + +int tas5825m_set_page(struct device *dev, uint8_t page) { + return tas5825m_write_at(dev, 0x00, page); +} + +int tas5825m_set_book(struct device *dev, uint8_t book) { + int res = tas5825m_set_page(dev, 0x00); + if (res < 0) return res; + return tas5825m_write_at(dev, 0x7F, book); +} + +__weak int tas5825m_setup(struct device *dev) { + printk(BIOS_ERR, "tas5825m: setup not implemented\n"); + return -1; +} + +static void tas5825m_init(struct device *dev) { + if (dev->enabled && dev->path.type == DEVICE_PATH_I2C && + ops_smbus_bus(get_pbus_smbus(dev))) { + printk(BIOS_DEBUG, "tas5825m at %s\n", dev_path(dev)); + int res = tas5825m_setup(dev); + if (res) { + printk(BIOS_ERR, "tas5825m init failed: %d\n", res); + } else { + printk(BIOS_DEBUG, "tas5825m init successful\n"); + } + } +} + +static struct device_operations tas5825m_operations = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .init = tas5825m_init, +}; + +static void tas5825m_enable_dev(struct device *dev) { + dev->ops = &tas5825m_operations; +} + +struct chip_operations drivers_i2c_tas5825m_ops = { + CHIP_NAME("TI TAS5825M Amplifier") + .enable_dev = tas5825m_enable_dev, +}; diff --git a/src/drivers/i2c/tas5825m/tas5825m.h b/src/drivers/i2c/tas5825m/tas5825m.h new file mode 100644 index 0000000..c58f86a --- /dev/null +++ b/src/drivers/i2c/tas5825m/tas5825m.h @@ -0,0 +1,12 @@ +#ifndef TAS5825M_H +#define TAS5825M_H + +#include <device/device.h> + +int tas5825m_write_at(struct device *dev, uint8_t addr, uint8_t value); +int tas5825m_write_block_at(struct device *dev, uint8_t addr, const uint8_t * values, uint8_t length); +int tas5825m_set_page(struct device *dev, uint8_t page); +int tas5825m_set_book(struct device *dev, uint8_t book); +int tas5825m_setup(struct device *dev); + +#endif // TAS5825M_H -- To view, visit https://review.coreboot.org/c/coreboot/+/43614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896e8f272f18e64bfc90f406e7d4163010800aaf Gerrit-Change-Number: 43614 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

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