coreboot-gerrit October 2020

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Change in coreboot[master]: mb/lenovo/x220/devicetree: Use subsystemid inheritance
by Peter Lemenkov (Code Review) 09 Jun '21

09 Jun '21

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37297 ) Change subject: mb/lenovo/x220/devicetree: Use subsystemid inheritance ...................................................................... mb/lenovo/x220/devicetree: Use subsystemid inheritance Change-Id: Ia9367d03b6f97f1eb8c35045fd7bb79e5f45b535 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/x220/devicetree.cb 1 file changed, 15 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/37297/1 diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 26fa1a4..5ae1427 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -37,13 +37,11 @@ register "pci_mmio_size" = "1024" device domain 0 on - device pci 00.0 on - subsystemid 0x17aa 0x21db - end # host bridge + subsystemid 0x17aa 0x21db inherit + + device pci 00.0 on end # host bridge device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on - subsystemid 0x17aa 0x21db - end # vga controller + device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -80,49 +78,29 @@ device pci 19.0 on subsystemid 0x17aa 0x21ce end # Intel Gigabit Ethernet - device pci 1a.0 on - subsystemid 0x17aa 0x21db - end # USB2 EHCI #2 - device pci 1b.0 on - subsystemid 0x17aa 0x21db - end # High Definition Audio - device pci 1c.0 on - subsystemid 0x17aa 0x21db - end # PCIe Port #1 - device pci 1c.1 on - subsystemid 0x17aa 0x21db - end # PCIe Port #2 (wlan) - device pci 1c.2 on - subsystemid 0x17aa 0x21db - end # PCIe Port #3 + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 (wlan) + device pci 1c.2 on end # PCIe Port #3 device pci 1c.3 on - subsystemid 0x17aa 0x21db smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 device pci 1c.4 on - subsystemid 0x17aa 0x21db chip drivers/ricoh/rce822 register "sdwppol" = "1" register "disable_mask" = "0x87" - device pci 00.0 on - subsystemid 0x17aa 0x21fa - end + device pci 00.0 on end end end # PCIe Port #5 (SD) device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on - subsystemid 0x17aa 0x21db - end # PCIe Port #7 + device pci 1c.6 on end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on - subsystemid 0x17aa 0x21db - end # USB2 EHCI #1 + device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on #LPC bridge - subsystemid 0x17aa 0x21db chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end @@ -172,11 +150,8 @@ register "wwan_gpio_lvl" = "0" end end # LPC bridge - device pci 1f.2 on - subsystemid 0x17aa 0x21db - end # SATA Controller 1 + device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on - subsystemid 0x17aa 0x21db # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -190,9 +165,7 @@ end end # SMBus device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on - subsystemid 0x17aa 0x21db - end # Thermal + device pci 1f.6 on end # Thermal end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/37297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9367d03b6f97f1eb8c35045fd7bb79e5f45b535 Gerrit-Change-Number: 37297 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: sb/intel/bd82x6x: Add missing ID for PCI bridge
by James (Code Review) 07 Jun '21

07 Jun '21

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41015 ) Change subject: sb/intel/bd82x6x: Add missing ID for PCI bridge ...................................................................... sb/intel/bd82x6x: Add missing ID for PCI bridge The PCI device ID 0x244e for the "Intel Corporation 82801 PCI Bridge" was missing. Change-Id: I22cdbcf518d86af7b93de7731d175088a81bbc1f Signed-off-by: James Ye <jye836(a)gmail.com> --- M src/southbridge/intel/bd82x6x/pci.c 1 file changed, 9 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/41015/1 diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index 459ed46..757bdeb 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -58,8 +58,14 @@ .ops_pci = &pci_ops, }; +static const unsigned short pci_device_ids[] = { + 0x244e, /* Desktop */ + 0x2448, /* Mobile */ + 0 +}; + static const struct pci_driver pch_pci __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x2448, + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/41015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22cdbcf518d86af7b93de7731d175088a81bbc1f Gerrit-Change-Number: 41015 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: soc/intel/xeon_sp/cpx/acpi: Align MADT IO APIC ID's with DMAR
by Arthur Heymans (Code Review) 07 Jun '21

07 Jun '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46503 ) Change subject: soc/intel/xeon_sp/cpx/acpi: Align MADT IO APIC ID's with DMAR ...................................................................... soc/intel/xeon_sp/cpx/acpi: Align MADT IO APIC ID's with DMAR In MADT loop over each stack and compare it against the same IO APIC ID table as during the DMAR table generation. This fixes Linux (5.8) warning: "DMAR-IR: [Firmware Bug]: ioapic 12 has no mapping iommu, interrupt remapping will be disabled" Change-Id: I32caf9036f0d548520b30b82324265cd4d0c3b8f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/cpx/acpi.c 1 file changed, 42 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/46503/1 diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index a1ebc4a..c7172b2 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -78,49 +78,56 @@ unsigned long acpi_fill_madt(unsigned long current) { - int cur_index; - struct iiostack_resource stack_info = {0}; + int cur_index = 0; + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); /* With CPX-SP FSP, PCH IOAPIC is allocated with first 120 GSIs. */ - int gsi_bases[] = { 0, 0x78, 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 }; - int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 }; + const int gsi_bases[] = { 0, 0x78, 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 }; + const int IoApicID[] = { + // socket 0 + PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID, + PC04_IOAPIC_ID, PC05_IOAPIC_ID, + // socket 1 + PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID, + PC10_IOAPIC_ID, PC11_IOAPIC_ID, + }; + + assert(hob != NULL && hob_size != 0); /* Local APICs */ current = xeonsp_acpi_create_madt_lapics(current); - cur_index = 0; - get_iiostack_info(&stack_info); + /* + * Stack 0 has non-PCH IOAPIC and PCH IOAPIC. + * Add entry for PCH IOAPIC. + */ + { + const STACK_RES *ri = &hob->PlatformData.IIO_resource[0].StackRes[0]; + const int gsi_base = gsi_bases[cur_index]; + printk(BIOS_DEBUG, "Adding MADT IOAPIC for PCH: ioapic_id: 0x%x, " + "ioapic_base: 0x%x, gsi_base: 0x%x\n", + PCH_IOAPIC_ID, ri->IoApicBase, gsi_base); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, PCH_IOAPIC_ID, + ri->IoApicBase, gsi_base); + cur_index++; + } - for (int stack = 0; stack < stack_info.no_of_stacks; ++stack) { - const STACK_RES *ri = &stack_info.res[stack]; - assert(cur_index < ARRAY_SIZE(ioapic_ids)); - assert(cur_index < ARRAY_SIZE(gsi_bases)); - int ioapic_id = ioapic_ids[cur_index]; - int gsi_base = gsi_bases[cur_index]; - printk(BIOS_DEBUG, "Adding MADT IOAPIC for stack: %d, ioapic_id: 0x%x, " - "ioapic_base: 0x%x, gsi_base: 0x%x\n", - stack, ioapic_id, ri->IoApicBase, gsi_base); - current += acpi_create_madt_ioapic( - (acpi_madt_ioapic_t *)current, - ioapic_id, ri->IoApicBase, gsi_base); - ++cur_index; - /* - * Stack 0 has non-PCH IOAPIC and PCH IOAPIC. - * Add entry for PCH IOAPIC. - */ - if (stack == 0) { /* PCH IOAPIC */ - assert(cur_index < ARRAY_SIZE(ioapic_ids)); - assert(cur_index < ARRAY_SIZE(gsi_bases)); - ioapic_id = ioapic_ids[cur_index]; - gsi_base = gsi_bases[cur_index]; - printk(BIOS_DEBUG, "Adding MADT IOAPIC for stack: %d, ioapic_id: 0x%x, " - "ioapic_base: 0x%x, gsi_base: 0x%x\n", - stack, ioapic_id, - ri->IoApicBase + 0x1000, gsi_base); - current += acpi_create_madt_ioapic( - (acpi_madt_ioapic_t *)current, - ioapic_id, ri->IoApicBase + 0x1000, gsi_base); + // DRHD + for (int iio = 0; iio < hob->PlatformData.numofIIO; ++iio) { + for (int stack = 0; stack < MAX_IIO_STACK; stack++) { + const STACK_RES *ri = &hob->PlatformData.IIO_resource[iio].StackRes[stack]; + if (ri->Personality != TYPE_UBOX_IIO) + continue; + const int ioapic_id = IoApicID[(iio * MAX_IIO_STACK) + stack]; + const int gsi_base = gsi_bases[cur_index]; + uint32_t apic_base = ri->IoApicBase; + if (iio == 0 && stack == 0) + apic_base += 0x1000; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, + ioapic_id, apic_base, gsi_base); ++cur_index; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32caf9036f0d548520b30b82324265cd4d0c3b8f Gerrit-Change-Number: 46503 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: [TEST] Enable link time optimization
by Jacob Garber (Code Review) 05 Jun '21

05 Jun '21

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40815 ) Change subject: [TEST] Enable link time optimization ...................................................................... [TEST] Enable link time optimization Enable LTO to shake out the bugs. Current problems: - GCC does not track symbol origins when using LTO, so it must be disabled for AGESA so it can be excluded from the illegal_globals check. - GCC segfaults when compiling ARMV7 - Most of the Google boards do not compile because of a missing reference to _watchdog_tombstone Change-Id: I37474d4adbf653729bb2e631a1ff812b4319c17a Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M src/Kconfig M src/vendorcode/amd/agesa/Makefile.inc 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/40815/1 diff --git a/src/Kconfig b/src/Kconfig index e4821e8..375bca2 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -116,7 +116,7 @@ config LTO bool "Use link time optimization (LTO)" - default n + default y depends on COMPILER_GCC help Compile with link time optimization. This can often decrease the diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc index b96af84..3e4a53c 100644 --- a/src/vendorcode/amd/agesa/Makefile.inc +++ b/src/vendorcode/amd/agesa/Makefile.inc @@ -14,6 +14,12 @@ AGESA_CFLAGS := -march=k8-sse3 -mtune=k8-sse3 -fno-strict-aliasing +# GCC currently does not track symbol origins when using LTO, so +# AGESA gets caught in the illegal_globals check. Disable for now. +ifeq ($(CONFIG_LTO),y) +AGESA_CFLAGS += -fno-lto +endif + CFLAGS_x86_32 += $(AGESA_CFLAGS) CFLAGS_x86_64 += $(AGESA_CFLAGS) -- To view, visit https://review.coreboot.org/c/coreboot/+/40815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37474d4adbf653729bb2e631a1ff812b4319c17a Gerrit-Change-Number: 40815 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE
by Subrata Banik (Code Review) 04 Jun '21

04 Jun '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44014 ) Change subject: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE ...................................................................... src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE This patch ensures that the TSEG region is only mapped as cacheable so that one can perform SMRAM relocation faster. Ideally don't need to mark the entire TOP_OF_RAM till BGSM range (used for ME stolen memory, PTT, DPR, PRMRR, TSEG etc) as cacheable as no executable code exist there except TSEG region. Hence only mark TSEG range as cacheable (+ reserved) and other ranges as reserve alone. TEST=Able to build and boot ICL, TGL RVP. Without this CL: PCI: 00:00.0 resource base 77000000 size 4800000 align 0 gran 0 limit 0 flags f0004200 index 9 PCI: 00:00.0 resource base 7b800000 size 4400000 align 0 gran 0 limit 0 flags f0000200 index a With this CL: PCI: 00:00.0 resource base 77000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 9 PCI: 00:00.0 resource base 7b000000 size 800000 align 0 gran 0 limit 0 flags f0004200 index a PCI: 00:00.0 resource base 7b800000 size 4400000 align 0 gran 0 limit 0 flags f0000200 index b Change-Id: I64c14b14caf0a53219fdc02ec6bbd375955a0c8e Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/systemagent/systemagent.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/44014/1 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index e12e07c..b15ca01 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -173,8 +173,13 @@ sa_get_mem_map(dev, &sa_map_values[0]); - /* top_of_ram -> BGSM */ + /* top_of_ram -> TSEG */ base_k = top_of_ram; + size_k = sa_map_values[SA_TSEG_REG] - base_k; + mmio_resource(dev, index++, base_k / KiB, size_k / KiB); + + /* TSEG -> BGSM */ + base_k = sa_map_values[SA_TSEG_REG]; size_k = sa_map_values[SA_BGSM_REG] - base_k; reserved_ram_resource(dev, index++, base_k / KiB, size_k / KiB); -- To view, visit https://review.coreboot.org/c/coreboot/+/44014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64c14b14caf0a53219fdc02ec6bbd375955a0c8e Gerrit-Change-Number: 44014 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Add KASAN stubs to coreboot.
by Abdullah Zafar (Code Review) 03 Jun '21

03 Jun '21

Abdullah Zafar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32231 Change subject: Add KASAN stubs to coreboot. ...................................................................... Add KASAN stubs to coreboot. Add option in Kconfig to compile with KASAN. Modify src/lib/Makefile.inc to enable gcc KASAN. Remove lint errors and warnings from kasan.c. Signed-off-by: 11abdullah11 <abdullahzafar4876(a)yahoo.com> Changes to be committed: modified: src/Kconfig modified: src/lib/Makefile.inc new file: src/lib/kasan.c Change-Id: Id13970514e37dfffb751391fb3e7e6b53ccc7577 --- M src/Kconfig M src/lib/Makefile.inc A src/lib/kasan.c 3 files changed, 45 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32231/1 diff --git a/src/Kconfig b/src/Kconfig index 62b3818..96e746e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -219,6 +219,15 @@ coverage information in CBMEM for extraction from user space. If unsure, say N. +config KASAN + bool "Kernel Address sanitizer support" + default y + help + Instrument the code with checks for UAF and OOB erros. If unsure, + say N because it adds a small performance penalty and may abort + on code that happens to work in spite of the UB. + + config UBSAN bool "Undefined behavior sanitizer support" default n diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1350152..88afaaa 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -19,6 +19,12 @@ CFLAGS_ramstage += -fsanitize=undefined endif +ifeq ($(CONFIG_KASAN),y) +ramstage-y += kasan.c +CFLAGS_ramstage += -fsanitize=kernel-address +endif + + decompressor-y += decompressor.c $(call src-to-obj,decompressor,$(dir)/decompressor.c): $(objcbfs)/bootblock.lz4 $(call src-to-obj,decompressor,$(dir)/decompressor.c): CCACHE_EXTRAFILES=$(objcbfs)/bootblock.lz4 @@ -83,7 +89,7 @@ romstage-y += memrange.c romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c -romstage-y += ramtest.c +romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c ramstage-y += region_file.c romstage-y += region_file.c diff --git a/src/lib/kasan.c b/src/lib/kasan.c new file mode 100644 index 0000000..3f482e9 --- /dev/null +++ b/src/lib/kasan.c @@ -0,0 +1,29 @@ +#include <stddef.h> + +/* + *Empty stubs for required by gcc to add compiler code + */ +void __asan_handle_no_return(void); +void __asan_load1_noabort(unsigned long addr); +void __asan_store1_noabort(unsigned long addr); +void __asan_load2_noabort(unsigned long addr); +void __asan_store2_noabort(unsigned long addr); +void __asan_load4_noabort(unsigned long addr); +void __asan_store4_noabort(unsigned long addr); +void __asan_load8_noabort(unsigned long addr); +void __asan_store8_noabort(unsigned long addr); +void __asan_loadN_noabort(unsigned long addr, size_t x); +void __asan_storeN_noabort(unsigned long addr, size_t x); + + +void __asan_handle_no_return(void) { } +void __asan_load1_noabort(unsigned long addr) { } +void __asan_store1_noabort(unsigned long addr) { } +void __asan_load2_noabort(unsigned long addr) { } +void __asan_store2_noabort(unsigned long addr) { } +void __asan_load4_noabort(unsigned long addr) { } +void __asan_store4_noabort(unsigned long addr) { } +void __asan_store8_noabort(unsigned long addr) { } +void __asan_load8_noabort(unsigned long addr) { } +void __asan_loadN_noabort(unsigned long addr, size_t i) { } +void __asan_storeN_noabort(unsigned long addr, size_t i) { } -- To view, visit https://review.coreboot.org/c/coreboot/+/32231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id13970514e37dfffb751391fb3e7e6b53ccc7577 Gerrit-Change-Number: 32231 Gerrit-PatchSet: 1 Gerrit-Owner: Abdullah Zafar <abdullahzafar4876(a)yahoo.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TEST]3rdparty/vboot: Vboot version update
by Wonkyu Kim (Code Review) 02 Jun '21

02 Jun '21

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39447 ) Change subject: [TEST]3rdparty/vboot: Vboot version update ...................................................................... [TEST]3rdparty/vboot: Vboot version update Update Vboot version to bb6c23472a0f to fix depthcharge build Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: Ibe5d13fff9730229818cd2201c55b794ba69c5ea --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/39447/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index 5059062..bb6c234 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 5059062dd352e3864fb68f8a061e87bd7055d12a +Subproject commit bb6c23472a0fd0565b3991331b63a4ed319d7872 -- To view, visit https://review.coreboot.org/c/coreboot/+/39447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe5d13fff9730229818cd2201c55b794ba69c5ea Gerrit-Change-Number: 39447 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vboot: Fix wrong algorithm in TCPA log for BOOT_MODE
by Werner Zeh (Code Review) 31 May '21

31 May '21

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35645 ) Change subject: vboot: Fix wrong algorithm in TCPA log for BOOT_MODE ...................................................................... vboot: Fix wrong algorithm in TCPA log for BOOT_MODE The hash algorithm for VBOOTs BOOT_MODE is fixed to sha1 but TCPA log uses sha256 as the name for the algorithm. This leads to an log entry with 20 bytes (sha1) while the algorithm is set to sha256 (which needs 32 bytes of hash). Fix it by using the matching algorithm name for BOOT_MODE. Change-Id: Ia25938ac5f6c29f60a4819023b99f7796849f574 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/security/vboot/tpm_common.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/35645/1 diff --git a/src/security/vboot/tpm_common.c b/src/security/vboot/tpm_common.c index 0a211c5..1db7189 100644 --- a/src/security/vboot/tpm_common.c +++ b/src/security/vboot/tpm_common.c @@ -46,7 +46,7 @@ switch (which_digest) { /* SHA1 of (devmode|recmode|keyblock) bits */ case BOOT_MODE_PCR: - return tpm_extend_pcr(pcr, VB2_HASH_SHA256, buffer, size, + return tpm_extend_pcr(pcr, VB2_HASH_SHA1, buffer, size, TPM_PCR_BOOT_MODE); /* SHA256 of HWID */ case HWID_DIGEST_PCR: -- To view, visit https://review.coreboot.org/c/coreboot/+/35645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia25938ac5f6c29f60a4819023b99f7796849f574 Gerrit-Change-Number: 35645 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: sb/intel/lynxpoint: Relocate SATA clock gating write
by Angel Pons (Code Review) 20 May '21

20 May '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47034 ) Change subject: sb/intel/lynxpoint: Relocate SATA clock gating write ...................................................................... sb/intel/lynxpoint: Relocate SATA clock gating write Do it in the same place as Broadwell. Change-Id: I50bd951af52d03ad986dbf4bf70bdae348fa994b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/sata.c 2 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/47034/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 4286e6ca..6b47b8a 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -467,8 +467,6 @@ RCBA32_OR(0x3434, 0x7); // LP LPC - RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); // SATA - RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic pch_iobp_update(0xCF000000, ~0, 0x00007001); diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index ef7ebcf..167f4df 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -215,6 +215,7 @@ if (pch_is_lp()) { sir_write(dev, 0x54, 0xcf000f0f); sir_write(dev, 0x58, 0x00190000); + RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); } reg32 = pci_read_config32(dev, 0x300); -- To view, visit https://review.coreboot.org/c/coreboot/+/47034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50bd951af52d03ad986dbf4bf70bdae348fa994b Gerrit-Change-Number: 47034 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: [RFC]cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y
by Arthur Heymans (Code Review) 18 May '21

18 May '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46380 ) Change subject: [RFC]cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y ...................................................................... [RFC]cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y If this builds, it removes the need to include this code separately on each platform. Change-Id: I3d848b1adca4921d7ffa2203348073f0a11d090e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/agesa/family14/Makefile.inc M src/cpu/amd/agesa/family15tn/Makefile.inc M src/cpu/amd/agesa/family16kb/Makefile.inc M src/cpu/amd/pi/00630F01/Makefile.inc M src/cpu/amd/pi/00660F01/Makefile.inc M src/cpu/amd/pi/00730F01/Makefile.inc M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/slot_1/Makefile.inc M src/cpu/intel/socket_441/Makefile.inc M src/cpu/intel/socket_BGA956/Makefile.inc M src/cpu/intel/socket_FCBGA559/Makefile.inc M src/cpu/intel/socket_LGA775/Makefile.inc M src/cpu/intel/socket_m/Makefile.inc M src/cpu/intel/socket_mPGA604/Makefile.inc M src/cpu/intel/socket_p/Makefile.inc M src/cpu/qemu-x86/Makefile.inc M src/cpu/x86/Makefile.inc M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Makefile.inc M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/braswell/Makefile.inc M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/denverton_ns/Makefile.inc M src/soc/intel/elkhartlake/Makefile.inc M src/soc/intel/icelake/Makefile.inc M src/soc/intel/jasperlake/Makefile.inc M src/soc/intel/skylake/Makefile.inc M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/xeon_sp/skx/Makefile.inc 34 files changed, 1 insertion(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/46380/1 diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index c940232..e73e8dd 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -12,4 +12,3 @@ subdirs-y += ../../../x86/cache subdirs-y += ../../../x86/mtrr subdirs-y += ../../../x86/pae -subdirs-y += ../../../x86/smm diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index bc04cfd..b2225b8 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -15,4 +15,3 @@ subdirs-y += ../../../x86/cache subdirs-y += ../../../x86/mtrr subdirs-y += ../../../x86/pae -subdirs-y += ../../../x86/smm diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc index c097b2c..6f5d439 100644 --- a/src/cpu/amd/agesa/family16kb/Makefile.inc +++ b/src/cpu/amd/agesa/family16kb/Makefile.inc @@ -12,4 +12,3 @@ subdirs-y += ../../../x86/cache subdirs-y += ../../../x86/mtrr subdirs-y += ../../../x86/pae -subdirs-y += ../../../x86/smm diff --git a/src/cpu/amd/pi/00630F01/Makefile.inc b/src/cpu/amd/pi/00630F01/Makefile.inc index bc04cfd..b2225b8 100644 --- a/src/cpu/amd/pi/00630F01/Makefile.inc +++ b/src/cpu/amd/pi/00630F01/Makefile.inc @@ -15,4 +15,3 @@ subdirs-y += ../../../x86/cache subdirs-y += ../../../x86/mtrr subdirs-y += ../../../x86/pae -subdirs-y += ../../../x86/smm diff --git a/src/cpu/amd/pi/00660F01/Makefile.inc b/src/cpu/amd/pi/00660F01/Makefile.inc index 69635fc..9c38443 100644 --- a/src/cpu/amd/pi/00660F01/Makefile.inc +++ b/src/cpu/amd/pi/00660F01/Makefile.inc @@ -11,4 +11,3 @@ subdirs-y += ../../../x86/cache subdirs-y += ../../../x86/mtrr subdirs-y += ../../../x86/pae -subdirs-y += ../../../x86/smm diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc index 406fafb9..ae2db0f 100644 --- a/src/cpu/amd/pi/00730F01/Makefile.inc +++ b/src/cpu/amd/pi/00730F01/Makefile.inc @@ -13,4 +13,3 @@ subdirs-y += ../../../x86/cache subdirs-y += ../../../x86/mtrr subdirs-y += ../../../x86/pae -subdirs-y += ../../../x86/smm diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index b93b911..c39ca64 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -17,7 +17,6 @@ subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../turbo diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index 1428421..817e0b7 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -6,7 +6,6 @@ subdirs-y += ../../x86/tsc subdirs-y += ../../intel/turbo subdirs-y += ../../intel/microcode -subdirs-y += ../../x86/smm subdirs-y += ../smm/gen1 ramstage-y += acpi.c diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index d824da1..5f39495 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -6,7 +6,6 @@ subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../turbo diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc index 03026cc..9044de8 100644 --- a/src/cpu/intel/slot_1/Makefile.inc +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -11,7 +11,6 @@ subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm subdirs-y += ../microcode bootblock-y += ../car/p3/cache_as_ram.S diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc index e21bf03..46312ce 100644 --- a/src/cpu/intel/socket_441/Makefile.inc +++ b/src/cpu/intel/socket_441/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc index 7656416..2af44bd 100644 --- a/src/cpu/intel/socket_BGA956/Makefile.inc +++ b/src/cpu/intel/socket_BGA956/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index c95e135..fd2c9d8 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index 2f1c6b4..8cc9a94 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -8,7 +8,6 @@ subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep diff --git a/src/cpu/intel/socket_m/Makefile.inc b/src/cpu/intel/socket_m/Makefile.inc index 61e4e58..84fc7a2 100644 --- a/src/cpu/intel/socket_m/Makefile.inc +++ b/src/cpu/intel/socket_m/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc index 9e3b8d7..9fc9d15 100644 --- a/src/cpu/intel/socket_mPGA604/Makefile.inc +++ b/src/cpu/intel/socket_mPGA604/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading diff --git a/src/cpu/intel/socket_p/Makefile.inc b/src/cpu/intel/socket_p/Makefile.inc index 76c4127..8e3cb2c 100644 --- a/src/cpu/intel/socket_p/Makefile.inc +++ b/src/cpu/intel/socket_p/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc index fb560d6..a286db9 100644 --- a/src/cpu/qemu-x86/Makefile.inc +++ b/src/cpu/qemu-x86/Makefile.inc @@ -9,5 +9,4 @@ subdirs-y += ../x86/mtrr subdirs-y += ../x86/lapic -subdirs-y += ../x86/smm subdirs-y += ../x86/tsc diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 2f789f7..3a24e7b 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -1,4 +1,5 @@ subdirs-y += pae +subdirs-$(CONFIG_HAVE_SMI_HANDLER) += smm subdirs-$(CONFIG_PARALLEL_MP) += name ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c ramstage-y += backup_default_smm.c diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 9757160..99bd212 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -8,7 +8,6 @@ subdirs-y += ../../../cpu/x86/cache subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/pae -subdirs-y += ../../../cpu/x86/smm subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage bootblock-y += bootblock/pre_c.S diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 16597e1..f41a644 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -8,7 +8,6 @@ subdirs-y += ../../../cpu/x86/cache subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/pae -subdirs-y += ../../../cpu/x86/smm bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c bootblock-y += BiosCallOuts.c diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index d962b75..4f99f48 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc # all (bootblock, verstage, romstage, postcar, ramstage) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 79fab1a..56079c1 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -5,7 +5,6 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index bfa1846..f49aac4 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index fcdb4a6..dade9a2 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 28b7c29..65f33f0 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 96f1f97..67b38c4 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -5,7 +5,6 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/common diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index 105f866..7ad5ecb 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -6,7 +6,6 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache diff --git a/src/soc/intel/elkhartlake/Makefile.inc b/src/soc/intel/elkhartlake/Makefile.inc index 5c46f86..5ba7b6d 100644 --- a/src/soc/intel/elkhartlake/Makefile.inc +++ b/src/soc/intel/elkhartlake/Makefile.inc @@ -5,7 +5,6 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc # all (bootblock, verstage, romstage, postcar, ramstage) diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 05f4846..3ce3600 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -5,7 +5,6 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc # all (bootblock, verstage, romstage, postcar, ramstage) diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 1cba218..8408b46 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -5,7 +5,6 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc # all (bootblock, verstage, romstage, postcar, ramstage) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index de516c1..3d2cabf 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -7,7 +7,6 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock.c diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index c4f71c7..4f9ae86 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -5,7 +5,6 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc # all (bootblock, verstage, romstage, postcar, ramstage) diff --git a/src/soc/intel/xeon_sp/skx/Makefile.inc b/src/soc/intel/xeon_sp/skx/Makefile.inc index 1a7e3dd..29e0dc9 100644 --- a/src/soc/intel/xeon_sp/skx/Makefile.inc +++ b/src/soc/intel/xeon_sp/skx/Makefile.inc @@ -8,7 +8,6 @@ subdirs-y += ../../../../cpu/x86/mtrr subdirs-y += ../../../../cpu/x86/tsc subdirs-y += ../../../../cpu/x86/cache -subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm postcar-y += soc_util.c -- To view, visit https://review.coreboot.org/c/coreboot/+/46380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d848b1adca4921d7ffa2203348073f0a11d090e Gerrit-Change-Number: 46380 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020