Change in coreboot[master]: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE

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coreboot-gerrit@coreboot.org

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  • Aaron Durbin (Code Review)
  • Angel Pons (Code Review)
  • Arthur Heymans (Code Review)
  • Furquan Shaikh (Code Review)
  • Maulik V Vaghela (Code Review)
  • Nico Huber (Code Review)
  • Subrata Banik (Code Review)
  • V Sowmya (Code Review)