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Change in coreboot[master]: mb/google/kukui: add support different ram table for Willow
by Lucas Chen (Code Review) 28 Jul '21

28 Jul '21

Lucas Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45289 ) Change subject: mb/google/kukui: add support different ram table for Willow ...................................................................... mb/google/kukui: add support different ram table for Willow Add support different ram id table base on board_id. BUG=b:160288021 BRANCH=kukui TEST=emerge-jacuzzi coreboot Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Change-Id: Icee922c647774f755d41bc3c37f6a0d5ffc35df1 --- M src/mainboard/google/kukui/boardid.c 1 file changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/45289/1 diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c old mode 100644 new mode 100755 index 548f36b..546247e --- a/src/mainboard/google/kukui/boardid.c +++ b/src/mainboard/google/kukui/boardid.c @@ -112,8 +112,17 @@ if (cached_ram_code == BOARD_ID_INIT) { cached_ram_code = get_adc_index(RAM_ID_CHANNEL); - /* Model-specific offset - see sdram_configs.c for details. */ - cached_ram_code += CONFIG_BOARD_SDRAM_TABLE_OFFSET; + /* Quirk for Willow: All Rev greater then 5 set SDRAM TABLE OFFSET=0x10. */ + if (CONFIG(BOARD_GOOGLE_WILLOW)) { + if (board_id() >= 6) { + cached_ram_code += 0x10; + } + else + cached_ram_code += CONFIG_BOARD_SDRAM_TABLE_OFFSET; + } + else + /* Model-specific offset - see sdram_configs.c for details. */ + cached_ram_code += CONFIG_BOARD_SDRAM_TABLE_OFFSET; } return cached_ram_code; } -- To view, visit https://review.coreboot.org/c/coreboot/+/45289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icee922c647774f755d41bc3c37f6a0d5ffc35df1 Gerrit-Change-Number: 45289 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: crossgcc: Update to GCC 8.4.0
by Iru Cai (vimacs) (Code Review) 19 Jul '21

19 Jul '21

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42159 to review the following change. Change subject: crossgcc: Update to GCC 8.4.0 ...................................................................... crossgcc: Update to GCC 8.4.0 - Remove gnat-bad_constant.patch which is already in GCC 8.4.0 - Backport GNAT exception handler v1 Change-Id: Icfc8430764404a6c272deb490fee23c963bd7ee5 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/crossgcc/buildgcc D util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch R util/crossgcc/patches/gcc-8.4.0_ada-musl_workaround.patch R util/crossgcc/patches/gcc-8.4.0_gnat.patch A util/crossgcc/patches/gcc-8.4.0_gnat_eh.patch R util/crossgcc/patches/gcc-8.4.0_libgcc.patch R util/crossgcc/patches/gcc-8.4.0_nds32_ite.patch D util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum A util/crossgcc/sum/gcc-8.4.0.tar.xz.cksum 9 files changed, 272 insertions(+), 152 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/42159/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 8770e02..e0827e0 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -36,7 +36,7 @@ GMP_VERSION=6.1.2 MPFR_VERSION=4.0.2 MPC_VERSION=1.1.0 -GCC_VERSION=8.3.0 +GCC_VERSION=8.4.0 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.33.1 GDB_VERSION=8.3.1 diff --git a/util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch b/util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch deleted file mode 100644 index e98f933..0000000 --- a/util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch +++ /dev/null @@ -1,150 +0,0 @@ -commit b6f742f96c62bab0582021455328ae3be58e16d3 -Author: pmderodat <pmderodat@138bc75d-0d04-0410-961f-82ee72b054a4> -Date: Fri May 25 09:05:10 2018 +0000 - - [Ada] Remove "constant" attribute on Osint.Unknown_Attributes - - 2018-05-25 Arnaud Charlet <charlet(a)adacore.com> - - gcc/ada/ - - * exp_aggr.adb (Convert_To_Positional): Bump default for - Max_Others_Replicate to 32. Update comments. - * osint.ads (Unknown_Attributes): No longer pretend this is a constant. - (No_File_Info_Cache): Initialize separately. - * osint.adb (No_File_Info_Cache): Update initializer. - - git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@260739 138bc75d-0d04-0410-961f-82ee72b054a4 - -diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog -index e4127e472aa..d56240b7b82 100644 ---- a/gcc/ada/ChangeLog -+++ b/gcc/ada/ChangeLog -@@ -188,6 +188,14 @@ - an allocator if the type is an unconstrained record type with default - discriminant. - -+2018-05-25 Arnaud Charlet <charlet(a)adacore.com> -+ -+ * exp_aggr.adb (Convert_To_Positional): Bump default for -+ Max_Others_Replicate to 32. Update comments. -+ * osint.ads (Unknown_Attributes): No longer pretend this is a constant. -+ (No_File_Info_Cache): Initialize separately. -+ * osint.adb (No_File_Info_Cache): Update initializer. -+ - 2018-05-04 John Marino <gnugcc(a)marino.st> - - PR ada/85635 -diff --git a/gcc/ada/exp_aggr.adb b/gcc/ada/exp_aggr.adb -index f723c1b4d99..ff5210eb4e4 100644 ---- a/gcc/ada/exp_aggr.adb -+++ b/gcc/ada/exp_aggr.adb -@@ -284,14 +284,14 @@ package body Exp_Aggr is - - procedure Convert_To_Positional - (N : Node_Id; -- Max_Others_Replicate : Nat := 5; -+ Max_Others_Replicate : Nat := 32; - Handle_Bit_Packed : Boolean := False); - -- If possible, convert named notation to positional notation. This - -- conversion is possible only in some static cases. If the conversion is - -- possible, then N is rewritten with the analyzed converted aggregate. - -- The parameter Max_Others_Replicate controls the maximum number of - -- values corresponding to an others choice that will be converted to -- -- positional notation (the default of 5 is the normal limit, and reflects -+ -- positional notation (the default of 32 is the normal limit, and reflects - -- the fact that normally the loop is better than a lot of separate - -- assignments). Note that this limit gets overridden in any case if - -- either of the restrictions No_Elaboration_Code or No_Implicit_Loops is -@@ -301,11 +301,6 @@ package body Exp_Aggr is - -- Packed_Array_Aggregate_Handled, we set this parameter to True, since - -- these are cases we handle in there. - -- -- It would seem useful to have a higher default for Max_Others_Replicate, -- -- but aggregates in the compiler make this impossible: the compiler -- -- bootstrap fails if Max_Others_Replicate is greater than 25. This -- -- is unexpected ??? -- - procedure Expand_Array_Aggregate (N : Node_Id); - -- This is the top-level routine to perform array aggregate expansion. - -- N is the N_Aggregate node to be expanded. -@@ -4292,7 +4287,7 @@ package body Exp_Aggr is - - procedure Convert_To_Positional - (N : Node_Id; -- Max_Others_Replicate : Nat := 5; -+ Max_Others_Replicate : Nat := 32; - Handle_Bit_Packed : Boolean := False) - is - Typ : constant Entity_Id := Etype (N); -diff --git a/gcc/ada/osint.adb b/gcc/ada/osint.adb -index 0c23761b6dc..896fbc7ee37 100644 ---- a/gcc/ada/osint.adb -+++ b/gcc/ada/osint.adb -@@ -250,8 +250,7 @@ package body Osint is - Attr : aliased File_Attributes; - end record; - -- No_File_Info_Cache : constant File_Info_Cache := -- (No_File, Unknown_Attributes); -+ No_File_Info_Cache : constant File_Info_Cache := (No_File, (others => 0)); - - package File_Name_Hash_Table is new GNAT.HTable.Simple_HTable ( - Header_Num => File_Hash_Num, -diff --git a/gcc/ada/osint.ads b/gcc/ada/osint.ads -index 65a87fe4ce3..6c75b521456 100644 ---- a/gcc/ada/osint.ads -+++ b/gcc/ada/osint.ads -@@ -255,10 +255,26 @@ package Osint is - -- from the disk and then cached in the File_Attributes parameter (possibly - -- along with other values). - -- type File_Attributes is private; -- Unknown_Attributes : constant File_Attributes; -+ File_Attributes_Size : constant Natural := 32; -+ -- This should be big enough to fit a "struct file_attributes" on any -+ -- system. It doesn't cause any malfunction if it is too big (which avoids -+ -- the need for either mapping the struct exactly or importing the sizeof -+ -- from C, which would result in dynamic code). However, it does waste -+ -- space (e.g. when a component of this type appears in a record, if it is -+ -- unnecessarily large). Note: for runtime units, use System.OS_Constants. -+ -- SIZEOF_struct_file_attributes instead, which has the exact value. -+ -+ type File_Attributes is -+ array (1 .. File_Attributes_Size) -+ of System.Storage_Elements.Storage_Element; -+ for File_Attributes'Alignment use Standard'Maximum_Alignment; -+ -+ Unknown_Attributes : File_Attributes; - -- A cache for various attributes for a file (length, accessibility,...) -- -- This must be initialized to Unknown_Attributes prior to the first call. -+ -- Will be initialized properly at elaboration (for efficiency later on, -+ -- avoid function calls every time we want to reset the attributes) prior -+ -- to the first usage. We cannot make it constant since the compiler may -+ -- put it in a read-only section. - - function Is_Directory - (Name : C_File_Name; -@@ -754,22 +770,4 @@ private - -- detected, the file being written is deleted, and a fatal error is - -- signalled. - -- File_Attributes_Size : constant Natural := 32; -- -- This should be big enough to fit a "struct file_attributes" on any -- -- system. It doesn't cause any malfunction if it is too big (which avoids -- -- the need for either mapping the struct exactly or importing the sizeof -- -- from C, which would result in dynamic code). However, it does waste -- -- space (e.g. when a component of this type appears in a record, if it is -- -- unnecessarily large). Note: for runtime units, use System.OS_Constants. -- -- SIZEOF_struct_file_attributes instead, which has the exact value. -- -- type File_Attributes is -- array (1 .. File_Attributes_Size) -- of System.Storage_Elements.Storage_Element; -- for File_Attributes'Alignment use Standard'Maximum_Alignment; -- -- Unknown_Attributes : constant File_Attributes := (others => 0); -- -- Will be initialized properly at elaboration (for efficiency later on, -- -- avoid function calls every time we want to reset the attributes). -- - end Osint; diff --git a/util/crossgcc/patches/gcc-8.3.0_ada-musl_workaround.patch b/util/crossgcc/patches/gcc-8.4.0_ada-musl_workaround.patch similarity index 100% rename from util/crossgcc/patches/gcc-8.3.0_ada-musl_workaround.patch rename to util/crossgcc/patches/gcc-8.4.0_ada-musl_workaround.patch diff --git a/util/crossgcc/patches/gcc-8.3.0_gnat.patch b/util/crossgcc/patches/gcc-8.4.0_gnat.patch similarity index 100% rename from util/crossgcc/patches/gcc-8.3.0_gnat.patch rename to util/crossgcc/patches/gcc-8.4.0_gnat.patch diff --git a/util/crossgcc/patches/gcc-8.4.0_gnat_eh.patch b/util/crossgcc/patches/gcc-8.4.0_gnat_eh.patch new file mode 100644 index 0000000..151a3e6 --- /dev/null +++ b/util/crossgcc/patches/gcc-8.4.0_gnat_eh.patch @@ -0,0 +1,270 @@ +commit 5d733372faa97c1c3943a20a252d000db37c738b +Author: Alexandre Oliva <oliva(a)adacore.com> +Date: Fri Aug 2 18:46:51 2019 +0000 + + rework Ada EH Machine_Occurrence deallocation + + Introduce exception handler ABI #1 to ensure single release, no access + after release of reraised Machine_Occurrences, and no failure to + re-reraise a Machine_Occurrence. + + Unlike Ada exceptions, foreign exceptions do not get a new + Machine_Occurrence upon reraise, but each handler would delete the + exception upon completion, normal or exceptional, save for the case of + a 'raise;' statement within the handler, that avoided the delete by + clearing the exception pointer that the cleanup would use to release + it. The cleared exception pointer might then be used by a subsequent + reraise within the same handler. Get_Current_Excep.all would also + expose the Machine_Occurrence to reuse by Reraise_Occurrence, even for + native exceptions. + + Under ABI #1, Begin_Handler_v1 claims responsibility for releasing an + exception by saving its cleanup and setting it to Claimed_Cleanup. + End_Handler_v1 restores the cleanup and runs it, as long as it isn't + still Claimed_Cleanup (which indicates an enclosing handler has + already claimed responsibility for releasing it), and as long as the + same exception is not being propagated up (the next handler of the + propagating exception will then claim responsibility for releasing + it), so reraise no longer needs to clear the exception pointer, and it + can just propagate the exception, just like Reraise_Occurrence. + + ABI #1 is fully interoperable with ABI #0, i.e., exception handlers + that call the #0 primitives can be linked together with ones that call + the #1 primitives, and they will not misbehave. When a #1 handler + claims responsibility for releasing an exception, even #0 reraises + dynamically nested within it will refrain from releasing it. However, + when a #0 handler is a handler of a foreign exception that would have + been responsible for releasing it with #1, a Reraise_Occurrence of + that foreign or other Machine_Occurrence-carrying exception may still + cause the exception to be released multiple times, and to be used + after it is first released, even if other handlers of the foreign + exception use #1. + + + for gcc/ada/ChangeLog + + * libgnat/a-exexpr.adb (Begin_Handler_v1, End_Handler_v1): New. + (Claimed_Cleanup): New. + (Begin_Handler, End_Handler): Document. + * gcc-interface/trans.c (gigi): Switch to exception handler + ABI #1. + (Exception_Handler_to_gnu_gcc): Save the original cleanup + returned by begin handler, pass it to end handler, and use + EH_ELSE_EXPR to pass a propagating exception to end handler. + (gnat_to_gnu): Leave the exception pointer alone for reraise. + (add_cleanup): Handle EH_ELSE_EXPR, require it by itself. + + From-SVN: r274029 + +diff --git a/gcc/ada/libgnat/a-exexpr.adb b/gcc/ada/libgnat/a-exexpr.adb +index b1aa1c6e6ba..5e72fd6e3f2 100644 +--- a/gcc/ada/libgnat/a-exexpr.adb ++++ b/gcc/ada/libgnat/a-exexpr.adb +@@ -197,15 +197,75 @@ package body Exception_Propagation is + -- whose machine occurrence is Mo. The message is empty, the backtrace + -- is empty too and the exception identity is Foreign_Exception. + +- -- Hooks called when entering/leaving an exception handler for a given +- -- occurrence, aimed at handling the stack of active occurrences. The +- -- calls are generated by gigi in tree_transform/N_Exception_Handler. ++ -- Hooks called when entering/leaving an exception handler for a ++ -- given occurrence. The calls are generated by gigi in ++ -- Exception_Handler_to_gnu_gcc. ++ ++ -- Begin_Handler_v1, called when entering an exception handler, ++ -- claims responsibility for the handler to release the ++ -- GCC_Exception occurrence. End_Handler_v1, called when ++ -- leaving the handler, releases the occurrence, unless the ++ -- occurrence is propagating further up, or the handler is ++ -- dynamically nested in the context of another handler that ++ -- claimed responsibility for releasing that occurrence. ++ ++ -- Responsibility is claimed by changing the Cleanup field to ++ -- Claimed_Cleanup, which enables claimed exceptions to be ++ -- recognized, and avoids accidental releases even by foreign ++ -- handlers. ++ ++ function Begin_Handler_v1 ++ (GCC_Exception : not null GCC_Exception_Access) ++ return System.Address; ++ pragma Export (C, Begin_Handler_v1, "__gnat_begin_handler_v1"); ++ -- Called when entering an exception handler. Claim ++ -- responsibility for releasing GCC_Exception, by setting the ++ -- cleanup/release function to Claimed_Cleanup, and return the ++ -- address of the previous cleanup/release function. ++ ++ procedure End_Handler_v1 ++ (GCC_Exception : not null GCC_Exception_Access; ++ Saved_Cleanup : System.Address; ++ Propagating_Exception : GCC_Exception_Access); ++ pragma Export (C, End_Handler_v1, "__gnat_end_handler_v1"); ++ -- Called when leaving an exception handler. Restore the ++ -- Saved_Cleanup in the GCC_Exception occurrence, and then release ++ -- it, unless it remains claimed by an enclosing handler, or ++ -- GCC_Exception and Propagating_Exception are the same ++ -- occurrence. Propagating_Exception could be either an ++ -- occurrence (re)raised within the handler of GCC_Exception, when ++ -- we're executing as an exceptional cleanup, or null, if we're ++ -- completing the handler of GCC_Exception normally. ++ ++ procedure Claimed_Cleanup ++ (Reason : Unwind_Reason_Code; ++ GCC_Exception : not null GCC_Exception_Access); ++ pragma Export (C, Claimed_Cleanup, "__gnat_claimed_cleanup"); ++ -- A do-nothing placeholder installed as GCC_Exception.Cleanup ++ -- while handling GCC_Exception, to claim responsibility for ++ -- releasing it, and to stop it from being accidentally released. ++ ++ -- The following are version 0 implementations of the version 1 ++ -- hooks above. They remain in place for compatibility with the ++ -- output of compilers that still use version 0, such as those ++ -- used during bootstrap. They are interoperable with the v1 ++ -- hooks, except that the older versions may malfunction when ++ -- handling foreign exceptions passed to Reraise_Occurrence. + + procedure Begin_Handler (GCC_Exception : not null GCC_Exception_Access); + pragma Export (C, Begin_Handler, "__gnat_begin_handler"); ++ -- Called when entering an exception handler translated by an old ++ -- compiler. It does nothing. + + procedure End_Handler (GCC_Exception : GCC_Exception_Access); + pragma Export (C, End_Handler, "__gnat_end_handler"); ++ -- Called when leaving an exception handler translated by an old ++ -- compiler. It releases GCC_Exception, unless it is null. It is ++ -- only ever null when the handler has a 'raise;' translated by a ++ -- v0-using compiler. The artificial handler variable passed to ++ -- End_Handler was set to null to tell End_Handler to refrain from ++ -- releasing the reraised exception. In v1 safer ways are used to ++ -- accomplish that. + + -------------------------------------------------------------------- + -- Accessors to Basic Components of a GNAT Exception Data Pointer -- +@@ -352,6 +412,128 @@ package body Exception_Propagation is + end if; + end Setup_Current_Excep; + ++ ---------------------- ++ -- Begin_Handler_v1 -- ++ ---------------------- ++ ++ function Begin_Handler_v1 ++ (GCC_Exception : not null GCC_Exception_Access) ++ return System.Address is ++ Saved_Cleanup : constant System.Address := GCC_Exception.Cleanup; ++ begin ++ -- Claim responsibility for releasing this exception, and stop ++ -- others from releasing it. ++ GCC_Exception.Cleanup := Claimed_Cleanup'Address; ++ return Saved_Cleanup; ++ end Begin_Handler_v1; ++ ++ -------------------- ++ -- End_Handler_v1 -- ++ -------------------- ++ ++ procedure End_Handler_v1 ++ (GCC_Exception : not null GCC_Exception_Access; ++ Saved_Cleanup : System.Address; ++ Propagating_Exception : GCC_Exception_Access) is ++ begin ++ GCC_Exception.Cleanup := Saved_Cleanup; ++ -- Restore the Saved_Cleanup, so that it is either used to ++ -- release GCC_Exception below, or transferred to the next ++ -- handler of the Propagating_Exception occurrence. The ++ -- following test ensures that an occurrence is only released ++ -- once, even after reraises. ++ -- ++ -- The idea is that the GCC_Exception is not to be released ++ -- unless it had an unclaimed Cleanup when the handler started ++ -- (see Begin_Handler_v1 above), but if we propagate across its ++ -- handler a reraise of the same exception, we transfer to the ++ -- Propagating_Exception the responsibility for running the ++ -- Saved_Cleanup when its handler completes. ++ -- ++ -- This ownership transfer mechanism ensures safety, as in ++ -- single release and no dangling pointers, because there is no ++ -- way to hold on to the Machine_Occurrence of an ++ -- Exception_Occurrence: the only situations in which another ++ -- Exception_Occurrence gets the same Machine_Occurrence are ++ -- through Reraise_Occurrence, and plain reraise, and so we ++ -- have the following possibilities: ++ -- ++ -- - Reraise_Occurrence is handled within the running handler, ++ -- and so when completing the dynamically nested handler, we ++ -- must NOT release the exception. A Claimed_Cleanup upon ++ -- entry of the nested handler, installed when entering the ++ -- enclosing handler, ensures the exception will not be ++ -- released by the nested handler, but rather by the enclosing ++ -- handler. ++ -- ++ -- - Reraise_Occurrence/reraise escapes the running handler, ++ -- and we run as an exceptional cleanup for GCC_Exception. The ++ -- Saved_Cleanup was reinstalled, but since we're propagating ++ -- the same machine occurrence, we do not release it. Instead, ++ -- we transfer responsibility for releasing it to the eventual ++ -- handler of the propagating exception. ++ -- ++ -- - An unrelated exception propagates through the running ++ -- handler. We restored GCC_Exception.Saved_Cleanup above. ++ -- Since we're propagating a different exception, we proceed to ++ -- release GCC_Exception, unless Saved_Cleanup was ++ -- Claimed_Cleanup, because then we know we're not in the ++ -- outermost handler for GCC_Exception. ++ -- ++ -- - The handler completes normally, so it reinstalls the ++ -- Saved_Cleanup and runs it, unless it was Claimed_Cleanup. ++ -- If Saved_Cleanup is null, Unwind_DeleteException (currently) ++ -- has no effect, so we could skip it, but if it is ever ++ -- changed to do more in this case, we're ready for that, ++ -- calling it exactly once. ++ if Saved_Cleanup /= Claimed_Cleanup'Address ++ and then ++ Propagating_Exception /= GCC_Exception ++ then ++ declare ++ Current : constant EOA := Get_Current_Excep.all; ++ Cur_Occ : constant GCC_Exception_Access ++ := To_GCC_Exception (Current.Machine_Occurrence); ++ begin ++ -- If we are releasing the Machine_Occurrence of the current ++ -- exception, reset the access to it, so that it is no ++ -- longer accessible. ++ if Cur_Occ = GCC_Exception then ++ Current.Machine_Occurrence := System.Null_Address; ++ end if; ++ end; ++ Unwind_DeleteException (GCC_Exception); ++ end if; ++ end End_Handler_v1; ++ ++ --------------------- ++ -- Claimed_Cleanup -- ++ --------------------- ++ ++ procedure Claimed_Cleanup ++ (Reason : Unwind_Reason_Code; ++ GCC_Exception : not null GCC_Exception_Access) is ++ pragma Unreferenced (Reason); ++ pragma Unreferenced (GCC_Exception); ++ begin ++ -- This procedure should never run. If it does, it's either a ++ -- version 0 handler or a foreign handler, attempting to ++ -- release an exception while a version 1 handler that claimed ++ -- responsibility for releasing the exception remains still ++ -- active. This placeholder stops GCC_Exception from being ++ -- released by them. ++ ++ -- We could get away with just Null_Address instead, with ++ -- nearly the same effect, but with this placeholder we can ++ -- detect and report unexpected releases, and we can tell apart ++ -- a GCC_Exception without a Cleanup, from one with another ++ -- active handler, so as to still call Unwind_DeleteException ++ -- exactly once: currently, Unwind_DeleteException does nothing ++ -- when the Cleanup is null, but should it ever be changed to ++ -- do more, we'll still be safe. ++ null; ++ end Claimed_Cleanup; ++ + ------------------- + -- Begin_Handler -- + ------------------- diff --git a/util/crossgcc/patches/gcc-8.3.0_libgcc.patch b/util/crossgcc/patches/gcc-8.4.0_libgcc.patch similarity index 100% rename from util/crossgcc/patches/gcc-8.3.0_libgcc.patch rename to util/crossgcc/patches/gcc-8.4.0_libgcc.patch diff --git a/util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch b/util/crossgcc/patches/gcc-8.4.0_nds32_ite.patch similarity index 100% rename from util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch rename to util/crossgcc/patches/gcc-8.4.0_nds32_ite.patch diff --git a/util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum b/util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum deleted file mode 100644 index b46ef8c..0000000 --- a/util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -c27f4499dd263fe4fb01bcc5565917f3698583b2 tarballs/gcc-8.3.0.tar.xz diff --git a/util/crossgcc/sum/gcc-8.4.0.tar.xz.cksum b/util/crossgcc/sum/gcc-8.4.0.tar.xz.cksum new file mode 100644 index 0000000..441f096 --- /dev/null +++ b/util/crossgcc/sum/gcc-8.4.0.tar.xz.cksum @@ -0,0 +1 @@ +00ddb177b04caffd40f7af0175d5b3c8e5442545 tarballs/gcc-8.4.0.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/42159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfc8430764404a6c272deb490fee23c963bd7ee5 Gerrit-Change-Number: 42159 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [DONOTSUBMIT] build system: temporarily disable adding config to cbfs
by Patrick Georgi (Code Review) 14 Jul '21

14 Jul '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42820 ) Change subject: [DONOTSUBMIT] build system: temporarily disable adding config to cbfs ...................................................................... [DONOTSUBMIT] build system: temporarily disable adding config to cbfs Makes comparisons between kconfig versions easier Change-Id: I30e4988b70785b3500a5b5284d760ea209c64ec4 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Makefile.inc 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/42820/1 diff --git a/Makefile.inc b/Makefile.inc index 7f61a5e..a204908 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1209,9 +1209,9 @@ vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE) vgaroms/seavgabios.bin-type := raw -cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += config -config-file := $(DOTCONFIG):defconfig -config-type := raw +# cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += config +# config-file := $(DOTCONFIG):defconfig +# config-type := raw cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += revision revision-file := $(obj)/build.h -- To view, visit https://review.coreboot.org/c/coreboot/+/42820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30e4988b70785b3500a5b5284d760ea209c64ec4 Gerrit-Change-Number: 42820 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: util/kconfig: Uprev to Linux 5.3's kconfig
by Patrick Georgi (Code Review) 13 Jul '21

13 Jul '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37152 ) Change subject: util/kconfig: Uprev to Linux 5.3's kconfig ...................................................................... util/kconfig: Uprev to Linux 5.3's kconfig This was originally several commits that had to be squashed into one because the intermediate states weren't able to build coreboot: - one to remove everything that wasn't our own code, leaving only regex.[ch], toada.c, description.md and Makefile.inc - one to copy in Linux 5.3's scripts/kconfig and adapt Makefile.inc to make the original Makefile work again. TODO: - more commits that bring back our modifications, both directly in the code and as a diff in a patches/ subdirectory. Change-Id: Ia0e8fe4e9022b278f34ab113a433ef4d45e5c355 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/kconfig/Makefile M util/kconfig/Makefile.inc D util/kconfig/POTFILES.in D util/kconfig/check.sh M util/kconfig/conf.c M util/kconfig/confdata.c M util/kconfig/expr.c M util/kconfig/expr.h A util/kconfig/gconf-cfg.sh M util/kconfig/gconf.c M util/kconfig/images.c A util/kconfig/images.h D util/kconfig/kxgettext.c A util/kconfig/lexer.l M util/kconfig/list.h M util/kconfig/lkc.h M util/kconfig/lkc_proto.h D util/kconfig/lxdialog/.gitignore M util/kconfig/lxdialog/BIG.FAT.WARNING D util/kconfig/lxdialog/check-lxdialog.sh M util/kconfig/lxdialog/checklist.c M util/kconfig/lxdialog/dialog.h M util/kconfig/lxdialog/inputbox.c M util/kconfig/lxdialog/menubox.c M util/kconfig/lxdialog/textbox.c M util/kconfig/lxdialog/util.c M util/kconfig/lxdialog/yesno.c A util/kconfig/mconf-cfg.sh M util/kconfig/mconf.c M util/kconfig/menu.c A util/kconfig/merge_config.sh A util/kconfig/nconf-cfg.sh M util/kconfig/nconf.c M util/kconfig/nconf.gui.c M util/kconfig/nconf.h R util/kconfig/parser.y A util/kconfig/preprocess.c A util/kconfig/qconf-cfg.sh M util/kconfig/qconf.cc M util/kconfig/qconf.h A util/kconfig/streamline_config.pl M util/kconfig/symbol.c M util/kconfig/util.c D util/kconfig/zconf.gperf D util/kconfig/zconf.hash.c_shipped D util/kconfig/zconf.l D util/kconfig/zconf.lex.c_shipped D util/kconfig/zconf.tab.c_shipped 48 files changed, 4,250 insertions(+), 8,203 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/37152/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/37152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0e8fe4e9022b278f34ab113a433ef4d45e5c355 Gerrit-Change-Number: 37152 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

6 46

Change in coreboot[master]: cpu/intel/car/core2/cache_as_ram: Add x86_64 support
by Patrick Rudolph (Code Review) 06 Jul '21

06 Jul '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45823 ) Change subject: cpu/intel/car/core2/cache_as_ram: Add x86_64 support ...................................................................... cpu/intel/car/core2/cache_as_ram: Add x86_64 support Change-Id: I27cdec5f112588b219f51112279b2dfbb05b6c97 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/car/cache_as_ram_symbols.inc M src/cpu/intel/car/core2/cache_as_ram.S 2 files changed, 26 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/45823/1 diff --git a/src/cpu/intel/car/cache_as_ram_symbols.inc b/src/cpu/intel/car/cache_as_ram_symbols.inc index 857e039..c75b1e44 100644 --- a/src/cpu/intel/car/cache_as_ram_symbols.inc +++ b/src/cpu/intel/car/cache_as_ram_symbols.inc @@ -16,5 +16,13 @@ car_mtrr_mask: .uintptr_t _car_mtrr_mask +car_mtrr_size: +.uintptr_t _car_mtrr_size + car_mtrr_start: .uintptr_t _car_mtrr_start + +#if !CONFIG(NO_XIP_EARLY_STAGES) +xip_mtrr_mask: +.uintptr_t _xip_mtrr_mask +#endif diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 837394c..5d6994f 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -6,6 +6,8 @@ .global bootblock_pre_c_entry +#include <cpu/intel/car/cache_as_ram_symbols.inc> + .code32 _cache_as_ram_setup: @@ -91,7 +93,7 @@ /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr - movl $_car_mtrr_mask, %eax + movl car_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr @@ -118,8 +120,8 @@ /* Clear the cache memory region. This will also fill up the cache. */ cld xorl %eax, %eax - movl $_car_mtrr_start, %edi - movl $_car_mtrr_size, %ecx + movl car_mtrr_start, %edi + movl car_mtrr_size, %ecx shr $2, %ecx rep stosl @@ -133,12 +135,12 @@ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx movl $_program, %eax - andl $_xip_mtrr_mask, %eax + andl xip_mtrr_mask, %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $_xip_mtrr_mask, %eax + movl xip_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr @@ -156,6 +158,16 @@ andl $0xfffffff0, %esp subl $4, %esp +#if ENV_X86_64 + + #include <cpu/x86/64bit/entry64.inc> + + movd %mm2, %rdi + shlq $32, %rdi + movd %mm1, %rsi + or %rsi, %rdi + movd %mm0, %rsi +#else /* push TSC and BIST to stack */ movd %mm0, %eax pushl %eax /* BIST */ @@ -163,6 +175,7 @@ pushl %eax /* tsc[63:32] */ movd %mm1, %eax pushl %eax /* tsc[31:0] */ +#endif before_c_entry: post_code(0x29) -- To view, visit https://review.coreboot.org/c/coreboot/+/45823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27cdec5f112588b219f51112279b2dfbb05b6c97 Gerrit-Change-Number: 45823 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: ironlake: Add support for x86_64
by Patrick Rudolph (Code Review) 06 Jul '21

06 Jul '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45699 ) Change subject: ironlake: Add support for x86_64 ...................................................................... ironlake: Add support for x86_64 Allow to compile the experimental x86_64 code. Tested on Lenovo Thinkpad T410. Works without issues. Change-Id: I60f2fccba357cb5fb5d85feb4ee8d02abfe6bc7e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/microcode/microcode_asm.S M src/cpu/intel/model_2065x/Kconfig M src/cpu/x86/early_reset.S 3 files changed, 14 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/45699/1 diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S index f02351a..5a8b907 100644 --- a/src/cpu/intel/microcode/microcode_asm.S +++ b/src/cpu/intel/microcode/microcode_asm.S @@ -45,6 +45,7 @@ .section .text .global update_bsp_microcode +.code32 update_bsp_microcode: /* Keep return address */ diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 78cac30..19eeab0 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -3,12 +3,20 @@ if CPU_INTEL_MODEL_2065X +config ARCH_EXP_X86_64 + bool "Experimental 64bit support" + default n + config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64 select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/x86/early_reset.S b/src/cpu/x86/early_reset.S index 6ce9d52..c6d0703 100644 --- a/src/cpu/x86/early_reset.S +++ b/src/cpu/x86/early_reset.S @@ -9,6 +9,7 @@ .section .text .global check_mtrr +.code32 check_mtrr: /* Use the MTRR default type MSR as a proxy for detecting INIT#. -- To view, visit https://review.coreboot.org/c/coreboot/+/45699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60f2fccba357cb5fb5d85feb4ee8d02abfe6bc7e Gerrit-Change-Number: 45699 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: arch/x86: Use ENV_X86_64 instead of _x86_64_
by Patrick Rudolph (Code Review) 05 Jul '21

05 Jul '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44867 ) Change subject: arch/x86: Use ENV_X86_64 instead of _x86_64_ ...................................................................... arch/x86: Use ENV_X86_64 instead of _x86_64_ Untested. Change-Id: I152483d24af0512c0ee4fbbe8931b7312e487ac6 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/assembly_entry.S M src/arch/x86/boot.c M src/arch/x86/c_exit.S M src/arch/x86/c_start.S M src/arch/x86/cpu.c M src/arch/x86/cpu_common.c M src/arch/x86/exception.c M src/arch/x86/exit_car.S M src/arch/x86/gdt_init.S M src/arch/x86/idt.S M src/arch/x86/include/arch/cpu.h M src/arch/x86/include/arch/registers.h M src/arch/x86/memcpy.c M src/arch/x86/wakeup.S M src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/cpu/x86/64bit/entry64.inc M src/cpu/x86/lapic/lapic_cpu_init.c M src/cpu/x86/smm/smm_stub.S M src/cpu/x86/smm/smmhandler.S M src/include/assert.h M src/include/cpu/x86/cr.h M src/soc/intel/denverton_ns/soc_util.c 22 files changed, 42 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/44867/1 diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 31670c2..6e73027 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -15,7 +15,7 @@ #define _STACK_TOP _ecar_stack #endif -#ifdef __x86_64__ +#if ENV_X86_64 .code64 #else .code32 @@ -26,7 +26,7 @@ _start: /* Migrate GDT to this text segment */ -#ifdef __x86_64__ +#if ENV_X86_64 call gdt_init64 #else call gdt_init diff --git a/src/arch/x86/boot.c b/src/arch/x86/boot.c index 777a0b7..31e7cee 100644 --- a/src/arch/x86/boot.c +++ b/src/arch/x86/boot.c @@ -21,14 +21,14 @@ void arch_prog_run(struct prog *prog) { -#if ENV_RAMSTAGE && defined(__x86_64__) +#if ENV_RAMSTAGE && ENV_X86_64 const uint32_t arg = pointer_to_uint32_safe(prog_entry_arg(prog)); const uint32_t entry = pointer_to_uint32_safe(prog_entry(prog)); /* On x86 coreboot payloads expect to be called in protected mode */ protected_mode_jump(entry, arg); #else -#ifdef __x86_64__ +#if ENV_X86_64 void (*doit)(void *arg); #else /* Ensure the argument is pushed on the stack. */ diff --git a/src/arch/x86/c_exit.S b/src/arch/x86/c_exit.S index e5b9bf8..bb1df28 100644 --- a/src/arch/x86/c_exit.S +++ b/src/arch/x86/c_exit.S @@ -5,7 +5,7 @@ #include <cpu/x86/cr.h> -#ifdef __x86_64__ +#if ENV_X86_64 /* * Functions to handle mode switches from long mode to protected diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index c46a45c..47d6597 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -22,7 +22,7 @@ #endif .section ".text._start", "ax", @progbits -#ifdef __x86_64__ +#if ENV_X86_64 .code64 #else .code32 @@ -31,7 +31,7 @@ _start: cli lgdt %cs:gdtaddr -#ifndef __x86_64__ +#if ENV_X86_32 ljmp $RAM_CODE_SEG, $1f #endif 1: movl $RAM_DATA_SEG, %eax @@ -40,7 +40,7 @@ movl %eax, %ss movl %eax, %fs movl %eax, %gs -#ifdef __x86_64__ +#if ENV_X86_64 mov $RAM_CODE_SEG64, %ecx call SetCodeSelector #endif @@ -49,7 +49,7 @@ cld -#ifdef __x86_64__ +#if ENV_X86_64 mov %rdi, _cbmem_top_ptr #else /* The return argument is at 0(%esp), the calling argument at 4(%esp) */ @@ -110,7 +110,7 @@ .globl gdb_stub_breakpoint gdb_stub_breakpoint: -#ifdef __x86_64__ +#if ENV_X86_64 pop %rax /* Return address */ pushfl push %cs @@ -132,7 +132,7 @@ gdtaddr: .word gdt_end - gdt - 1 -#ifdef __x86_64__ +#if ENV_X86_64 .quad gdt #else .long gdt /* we know the offset */ @@ -169,7 +169,7 @@ /* selgdt 0x18, flat data segment */ .word 0xffff, 0x0000 -#ifdef __x86_64__ +#if ENV_X86_64 .byte 0x00, 0x92, 0xcf, 0x00 #else .byte 0x00, 0x93, 0xcf, 0x00 @@ -203,7 +203,7 @@ * limit */ -#ifdef __x86_64__ +#if ENV_X86_64 /* selgdt 0x48, flat x64 code segment */ .word 0xffff, 0x0000 .byte 0x00, 0x9b, 0xaf, 0x00 @@ -211,7 +211,7 @@ gdt_end: .section ".text._start", "ax", @progbits -#ifdef __x86_64__ +#if ENV_X86_64 SetCodeSelector: # save rsp because iret will align it to a 16 byte boundary mov %rsp, %rdx diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index d054cfe..d44bd2f 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -14,7 +14,7 @@ #include <device/device.h> #include <smp/spinlock.h> -#ifndef __x86_64__ +#if ENV_X86_32 /* Standard macro to see if a specific flag is changeable */ static inline int flag_is_changeable_p(uint32_t flag) { @@ -137,7 +137,7 @@ vendor_name[0] = '\0'; /* Unset */ -#ifndef __x86_64__ +#if ENV_X86_32 /* Find the id and vendor_name */ if (!cpu_have_cpuid()) { /* Its a 486 if we can modify the AC flag */ diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c index 07de155..77d08c41 100644 --- a/src/arch/x86/cpu_common.c +++ b/src/arch/x86/cpu_common.c @@ -2,7 +2,7 @@ #include <cpu/cpu.h> -#ifndef __x86_64__ +#if ENV_X86_32 /* Standard macro to see if a specific flag is changeable */ static inline int flag_is_changeable_p(uint32_t flag) { diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index f10c7bf..6c519c3 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -491,7 +491,7 @@ logical_processor = cpu_index(); #endif u8 *code; -#ifdef __x86_64__ +#if ENV_X86_64 #define MDUMP_SIZE 0x100 printk(BIOS_EMERG, "CPU Index %d - APIC %d Unexpected Exception:\n" diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index dc356b2..db36821 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -11,7 +11,7 @@ .long 0 .long 0 -#if defined(__x86_64__) +#if ENV_X86_64 .code64 .macro pop_eax_edx pop %rax @@ -42,13 +42,13 @@ is expected to be implemented in assembly. */ /* Migrate GDT to this text segment */ -#if defined(__x86_64__) +#if ENV_X86_64 call gdt_init64 #else call gdt_init #endif -#ifdef __x86_64__ +#if ENV_X86_64 mov %rdi, _cbmem_top_ptr #else /* The return argument is at 0(%esp), the calling argument at 4(%esp) */ @@ -67,7 +67,7 @@ call chipset_teardown_car /* Enable caching if not already enabled. */ -#ifdef __x86_64__ +#if ENV_X86_64 mov %cr0, %rax and $(~(CR0_CD | CR0_NW)), %eax mov %rax, %cr0 @@ -102,7 +102,7 @@ /* Need to align stack to 16 bytes at the call instruction. Therefore account for the 1 push. */ andl $0xfffffff0, %esp -#if defined(__x86_64__) +#if ENV_X86_64 mov %rbp, %rdi #else sub $12, %esp diff --git a/src/arch/x86/gdt_init.S b/src/arch/x86/gdt_init.S index 1558ac6..287f17b 100644 --- a/src/arch/x86/gdt_init.S +++ b/src/arch/x86/gdt_init.S @@ -15,7 +15,7 @@ .word gdt_end - gdt -1 /* compute the table limit */ .long gdt /* we know the offset */ -#ifdef __x86_64__ +#if ENV_X86_64 .code64 .section ".text._gdt64_", "ax", @progbits .globl gdt_init64 diff --git a/src/arch/x86/idt.S b/src/arch/x86/idt.S index 6807056..d763b9e 100644 --- a/src/arch/x86/idt.S +++ b/src/arch/x86/idt.S @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ .section ".text._idt", "ax", @progbits -#ifdef __x86_64__ +#if ENV_X86_64 .code64 #else .code32 @@ -109,7 +109,7 @@ .global int_hand int_hand: -#ifdef __x86_64__ +#if ENV_X86_64 /* At this point, on x86-64, on the stack there is: * 0(%rsp) vector * 8(%rsp) error code diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index b622465..e523fc0 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -236,7 +236,7 @@ { struct cpu_info *ci; __asm__( -#ifdef __x86_64__ +#if ENV_X86_64 "and %%rsp,%0; " "or %2, %0 " #else diff --git a/src/arch/x86/include/arch/registers.h b/src/arch/x86/include/arch/registers.h index 5f8f9be..7043cd1 100644 --- a/src/arch/x86/include/arch/registers.h +++ b/src/arch/x86/include/arch/registers.h @@ -42,7 +42,7 @@ uint64_t r##A; \ } __packed -#ifdef __ARCH_x86_64__ +#if ENV_X86_64 struct eregs { QUAD_DOWNTO8(a); QUAD_DOWNTO8(c); diff --git a/src/arch/x86/memcpy.c b/src/arch/x86/memcpy.c index 1cfdf89..93002cd 100644 --- a/src/arch/x86/memcpy.c +++ b/src/arch/x86/memcpy.c @@ -15,7 +15,7 @@ #endif asm volatile( -#ifdef __x86_64__ +#if ENV_X86_64 "rep ; movsd\n\t" "mov %4,%%rcx\n\t" #else diff --git a/src/arch/x86/wakeup.S b/src/arch/x86/wakeup.S index ae2efe0..dc9510b 100644 --- a/src/arch/x86/wakeup.S +++ b/src/arch/x86/wakeup.S @@ -6,7 +6,7 @@ /* CR0 bits */ #define PE (1 << 0) -#ifdef __x86_64__ +#if ENV_X86_64 .code64 #else .code32 @@ -14,7 +14,7 @@ .globl __wakeup __wakeup: -#ifdef __x86_64__ +#if ENV_X86_64 xor %rax,%rax mov %ss, %ax push %rax diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 415ed24..4489d2c 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -28,7 +28,7 @@ and $0xfffffff0, %esp /* Restore the BIST result and timestamps. */ -#if defined(__x86_64__) +#if ENV_X86_64 movd %mm2, %rdi shld %rdi, 32 movd %mm1, %rsi diff --git a/src/cpu/x86/64bit/entry64.inc b/src/cpu/x86/64bit/entry64.inc index 65c0fdc..5049169 100644 --- a/src/cpu/x86/64bit/entry64.inc +++ b/src/cpu/x86/64bit/entry64.inc @@ -9,7 +9,7 @@ * Clobbers: eax, ecx, edx */ -#if defined(__x86_64__) +#if ENV_X86_64 .code32 #if (CONFIG_ARCH_X86_64_PGTBL_LOC & 0xfff) > 0 #error pagetables must be 4KiB aligned! diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index f89d9e3..342c86d 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -39,7 +39,7 @@ static inline void setup_secondary_gdt(void) { u16 *gdt_limit; -#ifdef __x86_64__ +#if ENV_X86_64 u64 *gdt_base; #else u32 *gdt_base; diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 11ea9a7..dd902d7 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -178,7 +178,7 @@ /* Align stack to 16 bytes. Another 32 bytes are pushed below. */ andl $0xfffffff0, %esp -#ifdef __x86_64__ +#if ENV_X86_64 mov %ecx, %edi /* Backup IA32_EFER. Preserves ebx. */ movl $(IA32_EFER), %ecx @@ -197,7 +197,7 @@ * struct arg = { c_handler_params, cpu_num, smm_runtime, canary }; * c_handler(&arg) */ -#ifdef __x86_64__ +#if ENV_X86_64 push %rbx /* uintptr_t *canary */ push $(smm_runtime) push %rcx /* size_t cpu */ diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index 340840f..bb91cb1 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -43,7 +43,7 @@ #define SMM_HANDLER_OFFSET 0x0000 -#if defined(__x86_64__) +#if ENV_X86_64 .bss ia32efer_backup_eax: .long @@ -169,7 +169,7 @@ movl $0xa8000 + 0x7efc, %ebx /* core 0 address */ subl %ebp, %ebx /* subtract core X offset */ -#if defined(__x86_64__) +#if ENV_X86_64 /* Backup IA32_EFER. Preserves ebx. */ movl $(IA32_EFER), %ecx rdmsr @@ -189,7 +189,7 @@ /* Call C handler */ call smi_handler -#if defined(__x86_64__) +#if ENV_X86_64 /* * The only reason to go back to protected mode is that RSM doesn't restore * MSR registers and MSR IA32_EFER was modified by entering long mode. diff --git a/src/include/assert.h b/src/include/assert.h index 944c677..27d7309 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -80,7 +80,7 @@ *(type *)(uintptr_t)0; \ }) -#ifdef __x86_64__ +#if ENV_X86_64 #define pointer_to_uint32_safe(x) ({ \ if ((uintptr_t)(x) > 0xffffffffUL) \ die("Cast from pointer to uint32_t overflows"); \ diff --git a/src/include/cpu/x86/cr.h b/src/include/cpu/x86/cr.h index 3508505a..c70f35c 100644 --- a/src/include/cpu/x86/cr.h +++ b/src/include/cpu/x86/cr.h @@ -9,7 +9,7 @@ #define COMPILER_BARRIER "memory" -#ifdef __x86_64__ +#if ENV_X86_64 #define CRx_TYPE uint64_t #define CRx_IN "q" #define CRx_RET "=q" diff --git a/src/soc/intel/denverton_ns/soc_util.c b/src/soc/intel/denverton_ns/soc_util.c index d5b9b34..b4c707d 100644 --- a/src/soc/intel/denverton_ns/soc_util.c +++ b/src/soc/intel/denverton_ns/soc_util.c @@ -274,7 +274,7 @@ unsigned long d0, d1, d2; asm volatile( -#ifdef __x86_64__ +#if ENV_X86_64 "rep ; movsd\n\t" "mov %4,%%rcx\n\t" #else -- To view, visit https://review.coreboot.org/c/coreboot/+/44867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I152483d24af0512c0ee4fbbe8931b7312e487ac6 Gerrit-Change-Number: 44867 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Inte...
by Lean Sheng Tan (Code Review) 24 Jun '21

24 Jun '21

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34159 ) Change subject: mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP ...................................................................... mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP This patch fixes display issues on both CFL-H & S, and WHL Intel RVP platform where display are not showing up in UEFI shell, by configuring DDi ports in device tree. This patches also fixes no eDP display observed in UEFI shell on UEFI Payload. Root cause is eDP requires minimum delay between GPIO programming and eDP initialisation, which was not sufficient during FSP initialisation which causes VBT to return error during eDP init. This issue is fixed by programming eDP GPIO's in bootblock stage and skipping FSP GPIO programming by setting 'DdiPortEdp=0' in devicetree. TEST= verified eDP display, HDMI and DP functionalities on CFL-H, CFL-S & WHL Intel RVP platforms. Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Iee87649492f7803210f9a35cd46b4f9826cbc93c --- M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb 4 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/34159/1 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c index ec8f58b..aa009bb 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c @@ -593,6 +593,19 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) + /* I4 : EDP_HPD */ + PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), + + /* F19 : EDP_VDDEN */ + PAD_CFG_NF(GPP_F19, NONE, PLTRST, NF1), + + /* F20 : EDP_BKLTEN */ + PAD_CFG_NF(GPP_F20, NONE, PLTRST, NF1), + + /* F21 : EDP_BKLTCTL */ + PAD_CFG_NF(GPP_F21, NONE, PLTRST, NF1), + #endif }; diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb index 9648ac3..40da8eb 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb @@ -9,6 +9,19 @@ register "RMT" = "1" register "ScsEmmcHs400Enabled" = "1" + # Enable eDP device + register "DdiPortEdp" = "0" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "1" + register "DdiPortFHpd" = "0" + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "0" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC5)" register "usb2_ports[1]" = "USB2_PORT_MID(OC6)" register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb index 126cab0..6ee52a4 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb @@ -9,6 +9,19 @@ register "RMT" = "1" register "ScsEmmcHs400Enabled" = "1" + # Enable eDP device + register "DdiPortEdp" = "0" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "1" + register "DdiPortFHpd" = "1" + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "0" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "1" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC4)" register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb index 429d5da..e824ac9 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb @@ -9,6 +9,19 @@ register "ScsEmmcHs400Enabled" = "1" register "HeciEnabled" = "1" + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "0" + register "DdiPortFHpd" = "0" + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "0" + # Enable eDP device register "DdiPortEdp" = "1" # Enable HPD for DDI ports B/C/D/F -- To view, visit https://review.coreboot.org/c/coreboot/+/34159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee87649492f7803210f9a35cd46b4f9826cbc93c Gerrit-Change-Number: 34159 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]soc/intel/car: Add support for bootguard CAR
by Arthur Heymans (Code Review) 23 Jun '21

23 Jun '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36682 ) Change subject: [WIP]soc/intel/car: Add support for bootguard CAR ...................................................................... [WIP]soc/intel/car: Add support for bootguard CAR Bootguard sets up CAR on its own so the only thing needed is to find a free MTRR for our own CAR region. Change-Id: Ifac5267f8f4b820a61519fb4a497e2ce7075cc40 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 66 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/36682/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index d5f5081..3ae4829 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -23,11 +23,20 @@ #include <rules.h> #include <intelblocks/msr.h> +#define BOOTGUARD_MSR 0x13a + .global bootblock_pre_c_entry bootblock_pre_c_entry: post_code(0x20) +/* Bootguard setups up it's own CAR and needs separate handling */ +check_boot_guard: + movl $BOOTGUARD_MSR, %ecx + rdmsr + andl $1, %eax + jnz bootguard_car_setup + movl $no_reset, %esp /* return address */ jmp check_mtrr /* Check if CPU properly reset */ @@ -456,3 +465,60 @@ jmp car_init_done #endif + +bootguard_car_setup: + /* Configure MTRR_PHYS_MASK_HIGH for proper addressing above 4GB + * based on the physical address size supported for this processor + * This is based on read from CPUID EAX = 080000008h, EAX bits [7:0] + */ + movl $0x80000008, %eax /* Address sizes leaf */ + cpuid + sub $32, %al + movzx %al, %eax + xorl %esi, %esi + bts %eax, %esi + dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */ + + /* Figure put how many MTRRs we have */ + mov $MTRR_CAP_MSR, %ecx + rdmsr + movzb %al, %ebx /* Number of variable MTRRs */ + + /* Find a free variable MTRR */ + movl $MTRR_PHYS_MASK(0), %ecx +test_is_free_mtrr: + rdmsr + test $MTRR_PHYS_MASK_VALID, %eax + jz found_free_mtrr + addl $2, %ecx + dec %ebx + jnz test_is_free_mtrr + + jmp .halt_forever + +found_free_mtrr: + /* Assume one MTRR is enough for now */ + decl %ecx /* MTRR_PHYS_BASE */ + movl $CONFIG_DCACHE_RAM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax + xorl %edx, %edx + wrmsr + + /* Configure the MTRR mask for the size region */ + incl %ecx + mov $CONFIG_DCACHE_RAM_SIZE, %eax /* size mask */ + decl %eax + not %eax + or $MTRR_PHYS_MASK_VALID, %eax + movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ + wrmsr + +clear_cache_region: + /* Clear the cache memory region. This will also fill up the cache */ + movl $CONFIG_DCACHE_RAM_BASE, %edi + movl $CONFIG_DCACHE_RAM_SIZE, %ecx + shr $0x02, %ecx + xor %eax, %eax + cld + rep stosl + jmp car_init_done -- To view, visit https://review.coreboot.org/c/coreboot/+/36682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifac5267f8f4b820a61519fb4a497e2ce7075cc40 Gerrit-Change-Number: 36682 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

12 62

Change in coreboot[master]: soc/intel/common/cache_as_ram.S: Add macro to clear CAR
by Arthur Heymans (Code Review) 22 Jun '21

22 Jun '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37191 ) Change subject: soc/intel/common/cache_as_ram.S: Add macro to clear CAR ...................................................................... soc/intel/common/cache_as_ram.S: Add macro to clear CAR Add a macro to clear CAR which is replicated 3 times in this code. Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 15 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/37191/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index d1ae6ca..6a0728d 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -48,6 +48,17 @@ 3: .endm + .macro clear_car + /* Clear the cache memory region. This will also fill up the cache */ + movl $CONFIG_DCACHE_RAM_BASE, %edi + movl $CONFIG_DCACHE_RAM_SIZE, %ecx + shr $0x02, %ecx + xor %eax, %eax + cld + rep stosl + .endm + + .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -256,13 +267,7 @@ post_code(0x26) - /* Clear the cache memory region. This will also fill up the cache */ - movl $CONFIG_DCACHE_RAM_BASE, %edi - movl $CONFIG_DCACHE_RAM_SIZE, %ecx - shr $0x02, %ecx - xor %eax, %eax - cld - rep stosl + clear_car post_code(0x27) @@ -353,13 +358,7 @@ post_code(0x26) - /* Clear the cache memory region. This will also fill up the cache */ - movl $CONFIG_DCACHE_RAM_BASE, %edi - movl $CONFIG_DCACHE_RAM_SIZE, %ecx - shr $0x02, %ecx - xor %eax, %eax - cld - rep stosl + clear_car post_code(0x27) @@ -462,12 +461,8 @@ xorl %edx, %edx wrmsr - movl $CONFIG_DCACHE_RAM_BASE, %edi - movl $CONFIG_DCACHE_RAM_SIZE, %ecx - shr $0x02, %ecx - xor %eax, %eax - cld - rep stosl + clear_car + /* * Set IA32_PQR_ASSOC = 0x01 * At this stage we apply LLC_WAY_MASK_1 to the cache. -- To view, visit https://review.coreboot.org/c/coreboot/+/37191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Gerrit-Change-Number: 37191 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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