coreboot-gerrit October 2020

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Change in coreboot[master]: inteltool: Add Intel 200 and Z370 series chipset
by Iru Cai (vimacs) (Code Review) 24 Oct '21

24 Oct '21

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35909 to review the following change. Change subject: inteltool: Add Intel 200 and Z370 series chipset ...................................................................... inteltool: Add Intel 200 and Z370 series chipset These chipsets are in the "Intel 200 (including X299) and Intel Z370 Series Chipset Families Platform Controller Hub (PCH)" datasheet (document number 335192). Change-Id: I4bad85eebab3991048907e5bd4783ad4e6ffa641 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 5 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/35909/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index efeab56..97e1419 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1070,6 +1070,13 @@ case PCI_DEVICE_ID_INTEL_QM370: case PCI_DEVICE_ID_INTEL_HM370: case PCI_DEVICE_ID_INTEL_CM246: + case PCI_DEVICE_ID_INTEL_Z270: + case PCI_DEVICE_ID_INTEL_H270: + case PCI_DEVICE_ID_INTEL_B250: + case PCI_DEVICE_ID_INTEL_Q250: + case PCI_DEVICE_ID_INTEL_Q270: + case PCI_DEVICE_ID_INTEL_X299: + case PCI_DEVICE_ID_INTEL_Z370: print_gpio_groups(sb); return 0; case PCI_DEVICE_ID_INTEL_82371XX: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 321cf97..d43983d 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -2239,6 +2239,13 @@ case PCI_DEVICE_ID_INTEL_QM170: case PCI_DEVICE_ID_INTEL_HM170: case PCI_DEVICE_ID_INTEL_CM236: + case PCI_DEVICE_ID_INTEL_Z270: + case PCI_DEVICE_ID_INTEL_H270: + case PCI_DEVICE_ID_INTEL_B250: + case PCI_DEVICE_ID_INTEL_Q250: + case PCI_DEVICE_ID_INTEL_Q270: + case PCI_DEVICE_ID_INTEL_X299: + case PCI_DEVICE_ID_INTEL_Z370: community_count = ARRAY_SIZE(sunrise_communities); communities = sunrise_communities; pcr_init(sb); diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index db80bd2..8fef3b4 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -275,6 +275,13 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C621_SUPER, "C621 Super SKU" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C627_SUPER_2, "C627 Super SKU" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C628_SUPER, "C628 Super SKU" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z270, "Z270" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H270, "H270" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B250, "B250" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q250, "Q250" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q270, "Q270" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X299, "X299" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z370, "Z370" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H310, "H310" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H370, "H370" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z390, "Z390" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index fc6dc4b..def78c6 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -184,6 +184,14 @@ #define PCI_DEVICE_ID_INTEL_C627_SUPER_2 0xa245 #define PCI_DEVICE_ID_INTEL_C628_SUPER 0xa246 +#define PCI_DEVICE_ID_INTEL_Z270 0xa2c5 +#define PCI_DEVICE_ID_INTEL_H270 0xa2c4 +#define PCI_DEVICE_ID_INTEL_B250 0xa2c8 +#define PCI_DEVICE_ID_INTEL_Q250 0xa2c7 +#define PCI_DEVICE_ID_INTEL_Q270 0xa2c6 +#define PCI_DEVICE_ID_INTEL_X299 0xa2d2 +#define PCI_DEVICE_ID_INTEL_Z370 0xa2c9 + #define PCI_DEVICE_ID_INTEL_H310 0xa303 #define PCI_DEVICE_ID_INTEL_H370 0xa304 #define PCI_DEVICE_ID_INTEL_Z390 0xa305 diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index ef6bb39..b6dc5e8 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -117,6 +117,13 @@ case PCI_DEVICE_ID_INTEL_C627_SUPER_2: case PCI_DEVICE_ID_INTEL_C628_SUPER: case PCI_DEVICE_ID_INTEL_DNV_LPC: + case PCI_DEVICE_ID_INTEL_Z270: + case PCI_DEVICE_ID_INTEL_H270: + case PCI_DEVICE_ID_INTEL_B250: + case PCI_DEVICE_ID_INTEL_Q250: + case PCI_DEVICE_ID_INTEL_Q270: + case PCI_DEVICE_ID_INTEL_X299: + case PCI_DEVICE_ID_INTEL_Z370: p2sb = pci_get_dev(sb->access, 0, 0, 0x1f, 1); break; case PCI_DEVICE_ID_INTEL_APL_LPC: -- To view, visit https://review.coreboot.org/c/coreboot/+/35909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bad85eebab3991048907e5bd4783ad4e6ffa641 Gerrit-Change-Number: 35909 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

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Change in gerrit-avatars[master]: [TESTONLY, DONOTMERGE] Change someone else's profile picture
by Angel Pons (Code Review) 22 Oct '21

22 Oct '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/gerrit-avatars/+/42290 ) Change subject: [TESTONLY, DONOTMERGE] Change someone else's profile picture ...................................................................... [TESTONLY, DONOTMERGE] Change someone else's profile picture CB:39926 added an extra southbridge to test things, so we respond by doing the same kind of thing but with a northbridge instead :-P Change-Id: I34f127e1653194b51573f6a929cb4aeab6b03a9f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A 1000145.jpg 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/gerrit-avatars refs/changes/90/42290/1 diff --git a/1000145.jpg b/1000145.jpg new file mode 100644 index 0000000..958accd --- /dev/null +++ b/1000145.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/gerrit-avatars/+/42290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: gerrit-avatars Gerrit-Branch: master Gerrit-Change-Id: I34f127e1653194b51573f6a929cb4aeab6b03a9f Gerrit-Change-Number: 42290 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 6

Change in coreboot[master]: coreboot-id: Add coreboot id based on FMAP entries
by Furquan Shaikh (Code Review) 22 Oct '21

22 Oct '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40377 ) Change subject: coreboot-id: Add coreboot id based on FMAP entries ...................................................................... coreboot-id: Add coreboot id based on FMAP entries This change replaces the coreboot id added to bootblock/decompressor stages with a ID region in FMAP that can be used across platforms. Following changes are made as part of this: 1. Adds new Kconfig options for COREBOOT_ID_FMAP_NAME and COREBOOT_ID_SIZE which provide the details of the fmap region name used for storing coreboot ID and the size of this region. Chrome OS does not use any of the coreboot build details filled in ID region. So, they are skipped for all Chrome OS boards. 2. Adds ##COREBOOT_ID_ENTRY## to default fmd files that can be used as a marker to insert the fmap entries for coreboot ID. 3. Replaces ##COREBOOT_ID_ENTRY## marker in the default fmd files using Makefile and the newly added FMAP_CURRENT_BASE. 4. Adds coreboot build details (version, vendor, part number) to this newly added FMAP region using cbfstool add-id command. 5. Removes id.ld and id.S from all architectures using it. 6. Adds COREBOOT_ID region to all non-Chrome OS fmd files. Because of this change, following difference would be observed: 1. Non-Chrome OS boards: coreboot build details will move from near the reset vector in bootblock/decompressor to a separate FMAP region. coreboot does not rely on these details at runtime. So, there should not be any impact. I am unsure if any tools used this at runtime. If yes, then those tools will have to be updated to use FMAP instead to find the location of ID. 2. Chrome OS boards: No coreboot details added to ROM image. TEST=Verified that build details are correctly added to the ID region in FMAP. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: Ibe1aaf36bec00b4cffc46a3640a5a0d1e4bb8067 --- M Documentation/Intel/SoC/soc.html M Makefile.inc M src/Kconfig M src/arch/arm/Makefile.inc D src/arch/arm/id.S M src/arch/arm64/Makefile.inc D src/arch/arm64/id.S M src/arch/x86/Makefile.inc D src/arch/x86/id.S D src/arch/x86/id.ld M src/arch/x86/memlayout.ld M src/mainboard/51nb/x210/board.fmd M src/mainboard/cavium/cn8100_sff_evb/board.fmd M src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd M src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd M src/mainboard/emulation/qemu-q35/vboot-rwab-16M.fmd M src/mainboard/facebook/monolith/vboot-ro.fmd M src/mainboard/facebook/monolith/vboot-rw.fmd M src/mainboard/intel/cedarisland_crb/board.fmd M src/mainboard/intel/galileo/vboot.fmd M src/mainboard/intel/leafhill/leafhill.16384.fmd M src/mainboard/intel/leafhill/leafhill.8192.fmd M src/mainboard/intel/minnow3/minnow3.fmd M src/mainboard/lenovo/t400/vboot-rwa.fmd M src/mainboard/lenovo/t410/vboot-rwa.fmd M src/mainboard/lenovo/t420/vboot-rwa.fmd M src/mainboard/lenovo/t420s/vboot-rwa.fmd M src/mainboard/lenovo/t430/vboot-rwab.fmd M src/mainboard/lenovo/t430s/vboot-rwab.fmd M src/mainboard/lenovo/t440p/vboot-rwab.fmd M src/mainboard/lenovo/t520/vboot-rwa.fmd M src/mainboard/lenovo/t530/vboot-rwab.fmd M src/mainboard/lenovo/x131e/vboot-rwab.fmd M src/mainboard/lenovo/x1_carbon_gen1/vboot-rwab.fmd M src/mainboard/lenovo/x200/vboot-rwa.fmd M src/mainboard/lenovo/x201/vboot-rwa.fmd M src/mainboard/lenovo/x220/vboot-rwa.fmd M src/mainboard/lenovo/x230/vboot-rwab.fmd M src/mainboard/ocp/tiogapass/board.fmd M src/mainboard/opencellular/elgon/board.fmd M src/mainboard/opencellular/elgon/vboot.fmd M src/mainboard/siemens/mc_apl1/mc_apl1.fmd M src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd M src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd M src/mainboard/up/squared/upsquared.fmd M src/mainboard/up/squared/vboot-ro.fmd M src/mainboard/up/squared/vboot-roa.fmd M src/mainboard/up/squared/vboot-roab.fmd M util/cbfstool/default-x86.fmd M util/cbfstool/default.fmd 50 files changed, 113 insertions(+), 133 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/40377/1 diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 6b1bb30..9e4d62e 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -199,9 +199,6 @@ </li> </ul> </li> - <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/id.S">src/arch/x86/id.S</a> - added by <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Mak…">src/arch/x86/Makefile.inc</a> - </li> <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fi…">src/cpu/intel/fit/fit.S</a> added by <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fi…">src/cpu/intel/fit/Makefile.inc</a> </li> diff --git a/Makefile.inc b/Makefile.inc index ac430f7..19f018c 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -926,6 +926,15 @@ FMAP_SMMSTORE_ENTRY := endif +ifneq ($(CONFIG_COREBOOT_ID_SIZE),0) +FMAP_COREBOOT_ID_BASE := $(FMAP_CURRENT_BASE) +FMAP_COREBOOT_ID_SIZE := $(CONFIG_COREBOOT_ID_SIZE) +FMAP_COREBOOT_ID_ENTRY := COREBOOT_ID@$(FMAP_COREBOOT_ID_BASE) $(FMAP_COREBOOT_ID_SIZE) +FMAP_CURRENT_BASE := $(call int-add, $(FMAP_COREBOOT_ID_BASE) $(FMAP_COREBOOT_ID_SIZE)) +else +FMAP_COREBOOT_ID_ENTRY := +endif + # # X86 FMAP region # @@ -983,6 +992,15 @@ FMAP_MRC_CACHE_ENTRY := endif +ifneq ($(CONFIG_COREBOOT_ID_SIZE),0) +FMAP_COREBOOT_ID_BASE := $(FMAP_CURRENT_BASE) +FMAP_COREBOOT_ID_SIZE := $(CONFIG_COREBOOT_ID_SIZE) +FMAP_COREBOOT_ID_ENTRY := COREBOOT_ID@$(FMAP_COREBOOT_ID_BASE) $(FMAP_COREBOOT_ID_SIZE) +FMAP_CURRENT_BASE := $(call int-add, $(FMAP_COREBOOT_ID_BASE) $(FMAP_COREBOOT_ID_SIZE)) +else +FMAP_COREBOOT_ID_ENTRY := +endif + # # NON-X86 COREBOOT default cbfs FMAP region # @@ -1002,6 +1020,7 @@ -e "s,##CONSOLE_ENTRY##,$(FMAP_CONSOLE_ENTRY)," \ -e "s,##MRC_CACHE_ENTRY##,$(FMAP_MRC_CACHE_ENTRY)," \ -e "s,##SMMSTORE_ENTRY##,$(FMAP_SMMSTORE_ENTRY)," \ + -e "s,##COREBOOT_ID_ENTRY##,$(FMAP_COREBOOT_ID_ENTRY)," \ -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \ -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \ $(DEFAULT_FLASHMAP) > $@.tmp @@ -1028,6 +1047,11 @@ ifneq ($(CONFIG_UPDATE_IMAGE),y) $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $(IFITTOOL) $$(cpu_ucode_cbfs_file) $(obj)/fmap.fmap $(obj)/fmap.desc $(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc) +ifneq ($(CONFIG_COREBOOT_ID_FMAP_NAME),"") + $(CBFSTOOL) $@.tmp add-id -r $(CONFIG_COREBOOT_ID_FMAP_NAME) --id-version $(KERNELVERSION) \ + --id-vendor $(CONFIG_MAINBOARD_VENDOR) \ + --id-part-num $(CONFIG_MAINBOARD_PART_NUMBER) +endif ifeq ($(CONFIG_ARCH_X86),y) $(CBFSTOOL) $@.tmp add \ -f $(objcbfs)/bootblock.bin \ diff --git a/src/Kconfig b/src/Kconfig index da21af1..378f302 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -422,6 +422,22 @@ binaries. This symbol should only be used to generate a default FMAP and is unused when a non-default fmd file is provided via CONFIG_FMDFILE. +config COREBOOT_ID_FMAP_NAME + string "Name of FMAP region storing coreboot build details" + default "" if CHROMEOS + default "COREBOOT_ID" + help + This is the name of the FMAP region where coreboot build details like + version, vendor name and part number are stored by the build system. + +config COREBOOT_ID_SIZE + hex "Size of FMAP region storing coreboot build details" + default 0 if CHROMEOS + default 0x40 + help + This is the size of the FMAP region where coreboot build details like + version, vendor name and part number are stored by the build system. + endmenu # load site-local kconfig to allow user specific defaults and overrides diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index a8abfaf..998ef8e 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -31,11 +31,6 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARM),y) -decompressor-y += id.S -bootblock-y += id.S -$(call src-to-obj,decompressor,$(dir)/id.S): $(obj)/build.h -$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h - decompressor-y += boot.c bootblock-y += boot.c decompressor-y += div0.c diff --git a/src/arch/arm/id.S b/src/arch/arm/id.S deleted file mode 100644 index 3cdd013..0000000 --- a/src/arch/arm/id.S +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <build.h> - - .section ".id", "a", %progbits - - .globl __id_start -__id_start: -ver: - .asciz COREBOOT_VERSION -vendor: - .asciz CONFIG_MAINBOARD_VENDOR -part: - .asciz CONFIG_MAINBOARD_PART_NUMBER -.long __id_end - ver /* Reverse offset to the vendor id */ -.long __id_end - vendor /* Reverse offset to the vendor id */ -.long __id_end - part /* Reverse offset to the part number */ -.long CONFIG_ROM_SIZE /* Size of this romimage */ - .globl __id_end - -__id_end: -.previous diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index c3d1fe5..3e4b28d 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -31,10 +31,6 @@ bootblock-y += div0.c decompressor-y += eabi_compat.c bootblock-y += eabi_compat.c -decompressor-y += id.S -bootblock-y += id.S -$(call src-to-obj,decompressor,$(dir)/id.S): $(obj)/build.h -$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h bootblock-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c bootblock-y += transition.c transition_asm.S diff --git a/src/arch/arm64/id.S b/src/arch/arm64/id.S deleted file mode 100644 index 3cdd013..0000000 --- a/src/arch/arm64/id.S +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <build.h> - - .section ".id", "a", %progbits - - .globl __id_start -__id_start: -ver: - .asciz COREBOOT_VERSION -vendor: - .asciz CONFIG_MAINBOARD_VENDOR -part: - .asciz CONFIG_MAINBOARD_PART_NUMBER -.long __id_end - ver /* Reverse offset to the vendor id */ -.long __id_end - vendor /* Reverse offset to the vendor id */ -.long __id_end - part /* Reverse offset to the part number */ -.long CONFIG_ROM_SIZE /* Size of this romimage */ - .globl __id_end - -__id_end: -.previous diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index b28ef78..d22e203 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -111,8 +111,6 @@ bootblock-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c bootblock-$(CONFIG_BOOTBLOCK_NORMAL) += bootblock_normal.c -bootblock-y += id.S -$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h bootblock-y += bootblock_crt0.S diff --git a/src/arch/x86/id.S b/src/arch/x86/id.S deleted file mode 100644 index dd447e6..0000000 --- a/src/arch/x86/id.S +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <build.h> - - .section ".id", "a", @progbits - - .globl __id_start -__id_start: -ver: - .asciz COREBOOT_VERSION -vendor: - .asciz CONFIG_MAINBOARD_VENDOR -part: - .asciz CONFIG_MAINBOARD_PART_NUMBER -.long __id_end + CONFIG_ID_SECTION_OFFSET - ver /* Reverse offset to the - *vendor id - */ -.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the - * vendor id - */ -.long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the - * part number - */ -.long CONFIG_ROM_SIZE /* Size of this romimage */ - .globl __id_end - -__id_end: -.previous diff --git a/src/arch/x86/id.ld b/src/arch/x86/id.ld deleted file mode 100644 index 31d5738..0000000 --- a/src/arch/x86/id.ld +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -SECTIONS { - . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; - .id (.): { - KEEP(*(.id)) - } -} diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 05efac6..ed1dbb2 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -53,7 +53,6 @@ /* Bootblock specific scripts which provide more SECTION directives. */ #include <cpu/x86/16bit/entry16.ld> #include <cpu/x86/16bit/reset16.ld> -#include <arch/x86/id.ld> #if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE) #include <cpu/intel/fit/fit.ld> #endif diff --git a/src/mainboard/51nb/x210/board.fmd b/src/mainboard/51nb/x210/board.fmd index 1955a05..4e506fa 100644 --- a/src/mainboard/51nb/x210/board.fmd +++ b/src/mainboard/51nb/x210/board.fmd @@ -8,7 +8,8 @@ EC@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 SMMSTORE@0x20000 0x40000 - CONSOLE@0x60000 0x20000 + CONSOLE@0x60000 0x1ffc0 + COREBOOT_ID@0x7ffc0 0x40 FMAP@0x80000 0x200 COREBOOT(CBFS) } diff --git a/src/mainboard/cavium/cn8100_sff_evb/board.fmd b/src/mainboard/cavium/cn8100_sff_evb/board.fmd index 34f3161..7ac0d9f 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/board.fmd +++ b/src/mainboard/cavium/cn8100_sff_evb/board.fmd @@ -4,6 +4,7 @@ # 0 - 0x10000 is free for firmware usage. # bootblock starts at 0x20000 FMAP@0x0 0x1000 + COREBOOT_ID@0x1000 0x40 # bootblock includes trusted/non-trusted CLIB, CSIB, # and BL1FWs packaged in # src/soc/cavium/common/Makefile.inc. diff --git a/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd b/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd index 0d2c9da..dd06a23 100644 --- a/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd +++ b/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd @@ -10,7 +10,8 @@ WP_RO { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd b/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd index 0d2c9da..dd06a23 100644 --- a/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd +++ b/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd @@ -10,7 +10,8 @@ WP_RO { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/emulation/qemu-q35/vboot-rwab-16M.fmd b/src/mainboard/emulation/qemu-q35/vboot-rwab-16M.fmd index fcbfa95..94899f0 100644 --- a/src/mainboard/emulation/qemu-q35/vboot-rwab-16M.fmd +++ b/src/mainboard/emulation/qemu-q35/vboot-rwab-16M.fmd @@ -19,7 +19,8 @@ WP_RO { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/facebook/monolith/vboot-ro.fmd b/src/mainboard/facebook/monolith/vboot-ro.fmd index 569971a..3efe768 100644 --- a/src/mainboard/facebook/monolith/vboot-ro.fmd +++ b/src/mainboard/facebook/monolith/vboot-ro.fmd @@ -17,7 +17,8 @@ RO_SECTION@0x1000 0x8DF000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + COREBOOT_ID@0x840 0x40 + RO_FRID_PAD@0x880 0x780 GBB@0x1000 0x4000 COREBOOT(CBFS)@0x5000 0x8DA000 } diff --git a/src/mainboard/facebook/monolith/vboot-rw.fmd b/src/mainboard/facebook/monolith/vboot-rw.fmd index dc2dadf..d8636ca 100644 --- a/src/mainboard/facebook/monolith/vboot-rw.fmd +++ b/src/mainboard/facebook/monolith/vboot-rw.fmd @@ -22,7 +22,8 @@ RO_SECTION@0x1000 0x7F000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + COREBOOT_ID@0x840 0x40 + RO_FRID_PAD@0x880 0x780 GBB@0x1000 0x4000 COREBOOT(CBFS)@0x5000 0x07A000 } diff --git a/src/mainboard/intel/cedarisland_crb/board.fmd b/src/mainboard/intel/cedarisland_crb/board.fmd index 2002f6e..e63fda3 100644 --- a/src/mainboard/intel/cedarisland_crb/board.fmd +++ b/src/mainboard/intel/cedarisland_crb/board.fmd @@ -5,7 +5,8 @@ SI_ME@0x3000 0x2fd5000 SI_PT@0x2fd8000 0x10000 } - FMAP@0x03000000 0x800 + FMAP@0x03000000 0x700 + COREBOOT_ID@0x3000700 0x100 RW_MRC_CACHE@0x3000800 0x10000 COREBOOT(CBFS)@0x3010800 } diff --git a/src/mainboard/intel/galileo/vboot.fmd b/src/mainboard/intel/galileo/vboot.fmd index 4d349bd..e7f3d1c 100644 --- a/src/mainboard/intel/galileo/vboot.fmd +++ b/src/mainboard/intel/galileo/vboot.fmd @@ -44,7 +44,8 @@ RO_SECTION@0x10000 0x1f0000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + COREBOOT_ID@0x840 0x40 + RO_FRID_PAD@0x880 0x780 GBB@0x1000 0x7f000 COREBOOT(CBFS)@0x80000 0x170000 } diff --git a/src/mainboard/intel/leafhill/leafhill.16384.fmd b/src/mainboard/intel/leafhill/leafhill.16384.fmd index a91ba9a..3ae4d81 100644 --- a/src/mainboard/intel/leafhill/leafhill.16384.fmd +++ b/src/mainboard/intel/leafhill/leafhill.16384.fmd @@ -1,7 +1,8 @@ FLASH 16M { SI_DESC@0x0 0x1000 IFWI@0x1000 0x2ff000 - FMAP@0x300000 0x800 + FMAP@0x300000 0x700 + COREBOOT_ID@0x300700 0x100 COREBOOT(CBFS)@0x300800 0xc1d800 UNIFIED_MRC_CACHE@0xf1e000 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 diff --git a/src/mainboard/intel/leafhill/leafhill.8192.fmd b/src/mainboard/intel/leafhill/leafhill.8192.fmd index 3f4d21b..f754d82 100644 --- a/src/mainboard/intel/leafhill/leafhill.8192.fmd +++ b/src/mainboard/intel/leafhill/leafhill.8192.fmd @@ -1,7 +1,8 @@ FLASH 8M { SI_DESC@0x0 0x1000 IFWI@0x1000 0x300000 - FMAP@0x321000 0x800 + FMAP@0x321000 0x700 + COREBOOT_ID@0x321700 0x100 COREBOOT(CBFS)@0x321800 0x300000 UNIFIED_MRC_CACHE@0x621800 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 diff --git a/src/mainboard/intel/minnow3/minnow3.fmd b/src/mainboard/intel/minnow3/minnow3.fmd index d51b5ee..b3ee60a 100644 --- a/src/mainboard/intel/minnow3/minnow3.fmd +++ b/src/mainboard/intel/minnow3/minnow3.fmd @@ -1,7 +1,8 @@ FLASH 16M { SI_DESC@0x0 0x1000 IFWI@0x1000 0x300000 - FMAP@0x301000 0x800 + FMAP@0x301000 0x700 + COREBOOT_ID@0x301700 0x100 COREBOOT(CBFS)@0x301800 0x3dc800 UNIFIED_MRC_CACHE@0x6de000 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 diff --git a/src/mainboard/lenovo/t400/vboot-rwa.fmd b/src/mainboard/lenovo/t400/vboot-rwa.fmd index 4af3fcd..7fff352 100644 --- a/src/mainboard/lenovo/t400/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t400/vboot-rwa.fmd @@ -17,7 +17,8 @@ WP_RO { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/t410/vboot-rwa.fmd b/src/mainboard/lenovo/t410/vboot-rwa.fmd index 8f50d33..6aa8bf4 100644 --- a/src/mainboard/lenovo/t410/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t410/vboot-rwa.fmd @@ -22,7 +22,8 @@ RO_SECTION 0x11e000 { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 GBB 0x1e000 COREBOOT(CBFS) } diff --git a/src/mainboard/lenovo/t420/vboot-rwa.fmd b/src/mainboard/lenovo/t420/vboot-rwa.fmd index 8a4cd3b..ac157c6 100644 --- a/src/mainboard/lenovo/t420/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t420/vboot-rwa.fmd @@ -20,7 +20,8 @@ WP_RO@0x1e1000 0x11f000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 + COREBOOT_ID@0x840 0x40 + RO_PADDING@0x880 0x780 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 COREBOOT(CBFS)@0x20000 0xff000 diff --git a/src/mainboard/lenovo/t420s/vboot-rwa.fmd b/src/mainboard/lenovo/t420s/vboot-rwa.fmd index 8a4cd3b..ac157c6 100644 --- a/src/mainboard/lenovo/t420s/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t420s/vboot-rwa.fmd @@ -20,7 +20,8 @@ WP_RO@0x1e1000 0x11f000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 + COREBOOT_ID@0x840 0x40 + RO_PADDING@0x880 0x780 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 COREBOOT(CBFS)@0x20000 0xff000 diff --git a/src/mainboard/lenovo/t430/vboot-rwab.fmd b/src/mainboard/lenovo/t430/vboot-rwab.fmd index 1747c0e..df60275 100644 --- a/src/mainboard/lenovo/t430/vboot-rwab.fmd +++ b/src/mainboard/lenovo/t430/vboot-rwab.fmd @@ -25,7 +25,8 @@ WP_RO { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/t430s/vboot-rwab.fmd b/src/mainboard/lenovo/t430s/vboot-rwab.fmd index 1747c0e..df60275 100644 --- a/src/mainboard/lenovo/t430s/vboot-rwab.fmd +++ b/src/mainboard/lenovo/t430s/vboot-rwab.fmd @@ -25,7 +25,8 @@ WP_RO { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/t440p/vboot-rwab.fmd b/src/mainboard/lenovo/t440p/vboot-rwab.fmd index 1747c0e..df60275 100644 --- a/src/mainboard/lenovo/t440p/vboot-rwab.fmd +++ b/src/mainboard/lenovo/t440p/vboot-rwab.fmd @@ -25,7 +25,8 @@ WP_RO { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/t520/vboot-rwa.fmd b/src/mainboard/lenovo/t520/vboot-rwa.fmd index 8a4cd3b..ac157c6 100644 --- a/src/mainboard/lenovo/t520/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t520/vboot-rwa.fmd @@ -20,7 +20,8 @@ WP_RO@0x1e1000 0x11f000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 + COREBOOT_ID@0x840 0x40 + RO_PADDING@0x880 0x780 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 COREBOOT(CBFS)@0x20000 0xff000 diff --git a/src/mainboard/lenovo/t530/vboot-rwab.fmd b/src/mainboard/lenovo/t530/vboot-rwab.fmd index 1747c0e..df60275 100644 --- a/src/mainboard/lenovo/t530/vboot-rwab.fmd +++ b/src/mainboard/lenovo/t530/vboot-rwab.fmd @@ -25,7 +25,8 @@ WP_RO { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/x131e/vboot-rwab.fmd b/src/mainboard/lenovo/x131e/vboot-rwab.fmd index 1747c0e..df60275 100644 --- a/src/mainboard/lenovo/x131e/vboot-rwab.fmd +++ b/src/mainboard/lenovo/x131e/vboot-rwab.fmd @@ -25,7 +25,8 @@ WP_RO { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/x1_carbon_gen1/vboot-rwab.fmd b/src/mainboard/lenovo/x1_carbon_gen1/vboot-rwab.fmd index 1747c0e..df60275 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/vboot-rwab.fmd +++ b/src/mainboard/lenovo/x1_carbon_gen1/vboot-rwab.fmd @@ -25,7 +25,8 @@ WP_RO { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/x200/vboot-rwa.fmd b/src/mainboard/lenovo/x200/vboot-rwa.fmd index 4af3fcd..7fff352 100644 --- a/src/mainboard/lenovo/x200/vboot-rwa.fmd +++ b/src/mainboard/lenovo/x200/vboot-rwa.fmd @@ -17,7 +17,8 @@ WP_RO { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/x201/vboot-rwa.fmd b/src/mainboard/lenovo/x201/vboot-rwa.fmd index 0d1aa5d..78aaeb1 100644 --- a/src/mainboard/lenovo/x201/vboot-rwa.fmd +++ b/src/mainboard/lenovo/x201/vboot-rwa.fmd @@ -21,7 +21,8 @@ RO_SECTION { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 GBB 0x1e000 COREBOOT(CBFS) } diff --git a/src/mainboard/lenovo/x220/vboot-rwa.fmd b/src/mainboard/lenovo/x220/vboot-rwa.fmd index 8a4cd3b..ac157c6 100644 --- a/src/mainboard/lenovo/x220/vboot-rwa.fmd +++ b/src/mainboard/lenovo/x220/vboot-rwa.fmd @@ -20,7 +20,8 @@ WP_RO@0x1e1000 0x11f000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 + COREBOOT_ID@0x840 0x40 + RO_PADDING@0x880 0x780 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 COREBOOT(CBFS)@0x20000 0xff000 diff --git a/src/mainboard/lenovo/x230/vboot-rwab.fmd b/src/mainboard/lenovo/x230/vboot-rwab.fmd index 1747c0e..df60275 100644 --- a/src/mainboard/lenovo/x230/vboot-rwab.fmd +++ b/src/mainboard/lenovo/x230/vboot-rwab.fmd @@ -25,7 +25,8 @@ WP_RO { FMAP 0x800 RO_FRID 0x40 - RO_PADDING 0x7c0 + COREBOOT_ID 0x40 + RO_PADDING 0x780 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/ocp/tiogapass/board.fmd b/src/mainboard/ocp/tiogapass/board.fmd index 1e3fda7..53f848b 100644 --- a/src/mainboard/ocp/tiogapass/board.fmd +++ b/src/mainboard/ocp/tiogapass/board.fmd @@ -5,7 +5,8 @@ PLATFORM_DATA@0xa26000 0x10000 } SI_BIOS@0x1000000 0x1000000 { - FMAP@0x0 0x800 + FMAP@0x0 0x700 + COREBOOT_ID@0x700 0x100 COREBOOT(CBFS)@0x800 0xfff800 } } diff --git a/src/mainboard/opencellular/elgon/board.fmd b/src/mainboard/opencellular/elgon/board.fmd index 784f3b0..e5ea8cb 100644 --- a/src/mainboard/opencellular/elgon/board.fmd +++ b/src/mainboard/opencellular/elgon/board.fmd @@ -4,6 +4,7 @@ # 0 - 0x10000 is free for firmware usage. # bootblock starts at 0x20000 FMAP@0x0 0x1000 + COREBOOT_ID@0x1000 0x40 # bootblock includes trusted/non-trusted CLIB, CSIB, # and BL1FWs packaged in # src/soc/cavium/common/Makefile.inc. diff --git a/src/mainboard/opencellular/elgon/vboot.fmd b/src/mainboard/opencellular/elgon/vboot.fmd index 0d6af2d..909e8de 100644 --- a/src/mainboard/opencellular/elgon/vboot.fmd +++ b/src/mainboard/opencellular/elgon/vboot.fmd @@ -6,6 +6,7 @@ # bootblock starts at 0x20000 FMAP@0x0 0x1000 RO_FRID@0x1000 0x100 + COREBOOT_ID@0x1100 0x40 # bootblock includes trusted/non-trusted CLIB, CSIB, # and BL1FWs packaged in # src/soc/cavium/common/Makefile.inc. diff --git a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd index 36772d6..fdeb65c 100644 --- a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd +++ b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd @@ -1,7 +1,8 @@ FLASH 16M { SI_DESC@0x0 0x1000 IFWI 0x2ff000 - FMAP 0x800 + FMAP 0x700 + COREBOOT_ID 0x100 COREBOOT(CBFS) 0xb9d800 UNIFIED_MRC_CACHE 0x21000 { RECOVERY_MRC_CACHE 0x10000 diff --git a/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd b/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd index 8af2e9a..d165d71 100644 --- a/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd +++ b/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd @@ -6,7 +6,8 @@ RO_SECTION 0xb8f000 { FMAP 0x800 RO_FRID 0x40 - RO_FRID_PAD 0x7c0 + COREBOOT_ID 0x40 + RO_FRID_PAD 0x780 COREBOOT(CBFS) 0xb4e000 GBB 0x40000 } diff --git a/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd b/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd index a295680..aa38f37 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd +++ b/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd @@ -27,7 +27,8 @@ RO_SECTION@0x4000 0x41d000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + COREBOOT_ID@0x840 0x40 + RO_FRID_PAD@0x880 0x780 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x32d000 } diff --git a/src/mainboard/up/squared/upsquared.fmd b/src/mainboard/up/squared/upsquared.fmd index 891138e..86c7cea 100644 --- a/src/mainboard/up/squared/upsquared.fmd +++ b/src/mainboard/up/squared/upsquared.fmd @@ -9,7 +9,8 @@ RW_MRC_CACHE@0x10000 0x10000 RW_VAR_MRC_CACHE@0x20000 0x1000 } - CONSOLE@0x22000 0x20000 + CONSOLE@0x22000 0x1ffc0 + COREBOOT_ID@0x41fc0 0x40 COREBOOT(CBFS)@0x42000 0xb7d000 BIOS_UNUSABLE@0xbbf000 0x40000 } diff --git a/src/mainboard/up/squared/vboot-ro.fmd b/src/mainboard/up/squared/vboot-ro.fmd index 72f92fe..8c71f53 100644 --- a/src/mainboard/up/squared/vboot-ro.fmd +++ b/src/mainboard/up/squared/vboot-ro.fmd @@ -7,7 +7,8 @@ RO_VPD(PRESERVE)@0x2ff800 0x4000 RO_SECTION@0x303800 0xb8d800 { RO_FRID@0x0 0x40 - RO_FRID_PAD@0x40 0x7c0 + COREBOOT_ID@0x40 0x40 + RO_FRID_PAD@0x80 0x780 GBB@0x800 0x40000 COREBOOT(CBFS)@0x40800 0xb4d000 } diff --git a/src/mainboard/up/squared/vboot-roa.fmd b/src/mainboard/up/squared/vboot-roa.fmd index 330ce03..118cde9 100644 --- a/src/mainboard/up/squared/vboot-roa.fmd +++ b/src/mainboard/up/squared/vboot-roa.fmd @@ -7,7 +7,8 @@ RO_VPD(PRESERVE)@0x2ff800 0x4000 RO_SECTION@0x303800 0x1fe800 { RO_FRID@0x0 0x40 - RO_FRID_PAD@0x40 0x7c0 + COREBOOT_ID@0x40 0x40 + RO_FRID_PAD@0x80 0x780 GBB@0x800 0x40000 COREBOOT(CBFS)@0x40800 0x1be000 } diff --git a/src/mainboard/up/squared/vboot-roab.fmd b/src/mainboard/up/squared/vboot-roab.fmd index 4ddcbc0..512355d 100644 --- a/src/mainboard/up/squared/vboot-roab.fmd +++ b/src/mainboard/up/squared/vboot-roab.fmd @@ -7,7 +7,8 @@ RO_VPD(PRESERVE)@0x2ff800 0x4000 RO_SECTION@0x303800 0x1ff800 { RO_FRID@0x0 0x40 - RO_FRID_PAD@0x40 0x7c0 + COREBOOT_ID@0x40 0x40 + RO_FRID_PAD@0x80 0x780 GBB@0x800 0x40000 COREBOOT(CBFS)@0x40800 0x1bf000 } diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd index f0143e9..ac958b4 100644 --- a/util/cbfstool/default-x86.fmd +++ b/util/cbfstool/default-x86.fmd @@ -12,6 +12,7 @@ ##CONSOLE_ENTRY## ##MRC_CACHE_ENTRY## ##SMMSTORE_ENTRY## + ##COREBOOT_ID_ENTRY## FMAP@##FMAP_BASE## ##FMAP_SIZE## COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## } diff --git a/util/cbfstool/default.fmd b/util/cbfstool/default.fmd index 8f4819e..7c8fc2c 100644 --- a/util/cbfstool/default.fmd +++ b/util/cbfstool/default.fmd @@ -15,6 +15,7 @@ FMAP@##FMAP_BASE## ##FMAP_SIZE## ##CONSOLE_ENTRY## ##MRC_CACHE_ENTRY## + ##COREBOOT_ID_ENTRY## COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## } } -- To view, visit https://review.coreboot.org/c/coreboot/+/40377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe1aaf36bec00b4cffc46a3640a5a0d1e4bb8067 Gerrit-Change-Number: 40377 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

7 21

Change in coreboot[master]: util/cbfstool: Add support for filling ID region using FMAP
by Furquan Shaikh (Code Review) 22 Oct '21

22 Oct '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40376 ) Change subject: util/cbfstool: Add support for filling ID region using FMAP ...................................................................... util/cbfstool: Add support for filling ID region using FMAP This change adds a new command add-id which takes as input the following parameters: 1. ID_FMAP_REGION: Name of the FMAP region used for storing ID (coreboot build details) 2. VERSION: Coreboot version provided by the build system. 3. VENDOR: Vendor name provided by the build system. 4. PART_NUM: Part number provided by the build system. Using the above parameters, this new command finds the fmap region using ID_FMAP_REGION and copies version, vendor and part number strings into the ID region. This allows us to get rid of all the id.ld and id.S files that are currently added in coreboot to supply build details into the bootblock or decompressor binary. This command makes use of non-ASCII longopts since we are running out of good opt characters to use. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: Ic5c55a49025508ff1f27c6f48d8e420f19d88ec2 --- M util/cbfstool/cbfstool.c 1 file changed, 60 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/40376/1 diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index f15c65b..224672c 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -93,6 +93,9 @@ char *initrd; char *cmdline; int force; + const char *id_version; + const char *id_vendor; + const char *id_part_num; } param = { /* All variables not listed are initialized as zero. */ .arch = CBFS_ARCHITECTURE_UNKNOWN, @@ -1270,6 +1273,44 @@ return result; } +static int id_str_write(struct buffer *buff, const char *str) +{ + size_t len = strlen(str) + 1; + if (buffer_size(buff) < len) { + ERROR("Not enough space for string in %s\n", param.region_name); + return 1; + } + + strcpy(buffer_get(buff), str); + buffer_seek(buff, len); + return 0; +} + +static int cbfs_add_id(void) +{ + if (!param.id_version || !param.id_vendor || !param.id_part_num) { + ERROR("All ID params (version, vendor and part_num) are mandatory\n"); + return 1; + } + + printf("FUR: %s %s %s\n", param.id_version, param.id_vendor, param.id_part_num); + + struct buffer id_buffer; + + buffer_clone(&id_buffer, param.image_region); + + if (id_str_write(&id_buffer, param.id_version)) + return 1; + + if (id_str_write(&id_buffer, param.id_vendor)) + return 1; + + if (id_str_write(&id_buffer, param.id_part_num)) + return 1; + + return 0; +} + static const struct command commands[] = { {"add", "H:r:f:n:t:c:b:a:p:yvA:j:gh?", cbfs_add, true, true}, {"add-flat-binary", "H:r:f:n:l:e:c:b:p:vA:gh?", cbfs_add_flat_binary, @@ -1280,6 +1321,7 @@ true, true}, {"add-int", "H:r:i:n:b:vgh?", cbfs_add_integer, true, true}, {"add-master-header", "H:r:vh?j:", cbfs_add_master_header, true, true}, + {"add-id", "r:h?", cbfs_add_id, true, true}, {"compact", "r:h?", cbfs_compact, true, true}, {"copy", "r:R:h?", cbfs_copy, true, true}, {"create", "M:r:s:B:b:H:o:m:vh?", cbfs_create, true, true}, @@ -1297,6 +1339,9 @@ /* begin after ASCII characters */ LONGOPT_START = 256, LONGOPT_IBB = LONGOPT_START, + LONGOPT_ID_VERSION, + LONGOPT_ID_VENDOR, + LONGOPT_ID_PART_NUM, LONGOPT_END, }; @@ -1339,6 +1384,9 @@ {"mach-parseable",no_argument, 0, 'k' }, {"unprocessed", no_argument, 0, 'U' }, {"ibb", no_argument, 0, LONGOPT_IBB }, + {"id-version", required_argument, 0, LONGOPT_ID_VERSION }, + {"id-vendor", required_argument, 0, LONGOPT_ID_VENDOR }, + {"id-part-num", required_argument, 0, LONGOPT_ID_PART_NUM }, {NULL, 0, 0, 0 } }; @@ -1433,6 +1481,9 @@ " add-master-header [-r image,regions] \\ \n" " [-j topswap-size] (Intel CPUs only) " "Add a legacy CBFS master header\n" + " add-id -r ID_FMAP_REGION --id-version VERSION \\\n" + " --id-vendor VENDOR --id-part-num PART_NUM " + "Add build details to ID FMAP region\n" " remove [-r image,regions] -n NAME " "Remove a component\n" " compact -r image,regions " @@ -1752,6 +1803,15 @@ case LONGOPT_IBB: param.ibb = true; break; + case LONGOPT_ID_VERSION: + param.id_version = optarg; + break; + case LONGOPT_ID_VENDOR: + param.id_vendor = optarg; + break; + case LONGOPT_ID_PART_NUM: + param.id_part_num = optarg; + break; case 'h': case '?': usage(argv[0]); -- To view, visit https://review.coreboot.org/c/coreboot/+/40376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5c55a49025508ff1f27c6f48d8e420f19d88ec2 Gerrit-Change-Number: 40376 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

3 8

Change in gerrit-avatars[master]: My avatar.
by Bao Zheng (Code Review) 21 Oct '21

21 Oct '21

Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/gerrit-avatars/+/42273 to review the following change. Change subject: My avatar. ...................................................................... My avatar. Change-Id: If3b7be405d6f8e49177ece19ef8641b8dffd8604 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> --- M 1000034.jpg 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/gerrit-avatars refs/changes/73/42273/1 diff --git a/1000034.jpg b/1000034.jpg index 1c7d0dd..a9662ce 100644 --- a/1000034.jpg +++ b/1000034.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/gerrit-avatars/+/42273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: gerrit-avatars Gerrit-Branch: master Gerrit-Change-Id: If3b7be405d6f8e49177ece19ef8641b8dffd8604 Gerrit-Change-Number: 42273 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao <zheng.bao(a)amd.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: soc/amd/picasso: Add speed measurement for spi
by Eric Peers (Code Review) 20 Oct '21

20 Oct '21

Eric Peers has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44229 ) Change subject: soc/amd/picasso: Add speed measurement for spi ...................................................................... soc/amd/picasso: Add speed measurement for spi * Still a WIP and likely not merge-worthy * Adds speed measurement for spi prior and after espi enablmenet including DMA. BUG=b:149014878 TEST=Compile & Run on Trembyle Signed-off-by: Eric PEers <epeers(a)google.com> Change-Id: I6a27c2153e6f258ef2f6a2f6c7de4f6965d535f5 --- M src/soc/amd/picasso/southbridge.c 1 file changed, 122 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/44229/1 diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 54d7640..86cf9e1 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -28,6 +28,7 @@ #include <soc/pci_devs.h> #include <soc/nvs.h> #include <types.h> +#include <timestamp.h> #include "chip.h" /* @@ -132,6 +133,118 @@ lpc_enable_port80(); } +#if !defined(__SIMPLE_DEVICE__) +#define _LPCB_DEV pcidev_on_root(0x14, 0x3) +#else +#define _LPCB_DEV PCI_DEV(0, 0x14, 0x3) +#endif + +static void measure_spi(void) +{ + //set timer + uint8_t byte; + uint32_t dword; + uint64_t qword; + uint64_t total; + uint32_t *ptr; + uint64_t *qword_ptr; + uint8_t *byte_ptr; + uint32_t start, finish, diff; + int i; + + printk(BIOS_DEBUG, "Measuring SPI\n"); + if (0) { + printk(BIOS_DEBUG, "8b writes\n"); + //-------------- 8b writes + start = get_us_since_boot(); + byte = 0; + //we get 0x14000 worth of space. + for (byte_ptr=(uint8_t *)0xff76c000;byte_ptr<(uint8_t *)0xff76d000;byte_ptr++) { + *byte_ptr = byte; + byte++; + } + finish = get_us_since_boot(); + diff = finish-start; + printk(BIOS_DEBUG, "0x1000 bytes, in %d usec\n", diff); + } + + //--------------- 8b reads + printk(BIOS_DEBUG, "8b reads\n"); + start = get_us_since_boot(); + total = 0; + for (byte_ptr = (uint8_t *)0xff76c000; byte_ptr < (uint8_t *)0xff76d000; byte_ptr++) { + byte = *byte_ptr; + total+=byte; + } + finish = get_us_since_boot(); + diff = finish-start; + printk(BIOS_DEBUG, "0x1000 bytes, in %d usec\n", diff); + printk(BIOS_DEBUG, "TOTAL: %lld\n", total); + + + if (0) { + printk(BIOS_DEBUG, "32b writes\n"); + //---------------- 32b writes + start = get_us_since_boot(); + dword = 0; + for (ptr=(uint32_t *)0xff76d000;ptr<(uint32_t *)0xff76e000;ptr+=4) { + *ptr = dword; + dword++; + } + finish = get_us_since_boot(); + diff = finish-start; + printk(BIOS_DEBUG, "0x1000 bytes, in %d usec\n", diff); + } + + //--------------- 32b reads + printk(BIOS_DEBUG, "32b reads\n"); + start = get_us_since_boot(); + total = 0; + for (ptr=(uint32_t *)0xff76d000;ptr<(uint32_t *)0xff76e000;ptr+=4) { + dword = *ptr; + total+=dword; + } + finish = get_us_since_boot(); + diff = finish-start; + printk(BIOS_DEBUG, "0x1000 bytes, in %d usec\n", diff); + printk(BIOS_DEBUG, "TOTAL: %lld\n", total); + + //------------- 64b reads. Should prefetch + printk(BIOS_DEBUG, "64b reads\n"); + start = get_us_since_boot(); + total = 0; + for (qword_ptr=(uint64_t *)0xff76e000;qword_ptr<(uint64_t *)0xff76f000;qword_ptr+=8) { + qword = *qword_ptr; + total+=qword; + } + finish = get_us_since_boot(); + diff = finish-start; + printk(BIOS_DEBUG, "0x1000 bytes, in %d usec\n", diff); + printk(BIOS_DEBUG, "TOTAL: %lld\n", total); + + //------------ burst read + printk(BIOS_DEBUG, "burst read\n"); + start = 0; + pci_write_config32(_LPCB_DEV, 0xb0, 0xff76f000); //src addr for DMA + pci_write_config32(_LPCB_DEV, 0xb4, 0x40000000); //dest addr - put it at 1GB + dword = pci_read_config32(_LPCB_DEV, LPC_ROM_DMA_EC_HOST_CONTROL); + dword |= 0x1; //tell it GO GO GO + dword |= 0x0FC0; //pull this many cachelines+1 pf 64B which... should be be 0x1000. [15:6] 0x1000 + pci_write_config32(_LPCB_DEV, LPC_ROM_DMA_EC_HOST_CONTROL, dword); + for (i=0;i<1000;i++) { + dword = pci_read_config32(_LPCB_DEV, LPC_ROM_DMA_EC_HOST_CONTROL); + if ((dword & 0x1) == 0) break; + udelay(10); + } + if (i>=100) { + printk(BIOS_ERR, "Took too long to run DMA\n"); + } + finish = get_us_since_boot(); + diff = finish-start; + printk(BIOS_DEBUG, "0x1000 bytes, in %d usec\n", diff); + +} + /* Before console init */ void fch_pre_init(void) { @@ -141,6 +254,8 @@ lpc_configure_decodes(); fch_spi_early_init(); + + enable_acpimmio_decode_pm04(); fch_smbus_init(); sb_enable_cf9_io(); @@ -156,6 +271,7 @@ if (CONFIG(PICASSO_CONSOLE_UART)) set_uart_config(CONFIG_UART_FOR_CONSOLE); + } static void print_num_status_bits(int num_bits, uint32_t status, @@ -216,6 +332,9 @@ sb_print_pmxc0_status(); i2c_soc_early_init(); + printk(BIOS_DEBUG, "Measure spi before espi setup\n"); + measure_spi(); + if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) lpc_disable_spi_rom_sharing(); @@ -223,6 +342,9 @@ espi_setup(); espi_configure_decodes(); } + + printk(BIOS_DEBUG, "Measure spi after espi setup\n"); + measure_spi(); } void sb_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/44229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a27c2153e6f258ef2f6a2f6c7de4f6965d535f5 Gerrit-Change-Number: 44229 Gerrit-PatchSet: 1 Gerrit-Owner: Eric Peers <epeers(a)google.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: superio: nuvoton: add a driver for nct668xd
by Michael Niewöhner (Code Review) 18 Oct '21

18 Oct '21

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34948 ) Change subject: superio: nuvoton: add a driver for nct668xd ...................................................................... superio: nuvoton: add a driver for nct668xd Change-Id: I78eca4ba2948c36a386306887f62773580f6e444 --- A src/superio/nuvoton/nct668xd/Kconfig A src/superio/nuvoton/nct668xd/Makefile.inc A src/superio/nuvoton/nct668xd/nct668Xd.h A src/superio/nuvoton/nct668xd/superio.c 4 files changed, 218 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/34948/1 diff --git a/src/superio/nuvoton/nct668xd/Kconfig b/src/superio/nuvoton/nct668xd/Kconfig new file mode 100644 index 0000000..ac31463 --- /dev/null +++ b/src/superio/nuvoton/nct668xd/Kconfig @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com> +## Copyright (C) 2019 Michael Niewöhner <foss(a)mniewoehner.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_NUVOTON_NCT668XD + bool + select SUPERIO_NUVOTON_COMMON_PRE_RAM + +config SUPERIO_NUVOTON_NCT668XD_COM_A + bool + depends on SUPERIO_NUVOTON_NCT668XD + default n diff --git a/src/superio/nuvoton/nct668xd/Makefile.inc b/src/superio/nuvoton/nct668xd/Makefile.inc new file mode 100644 index 0000000..5ab05c6 --- /dev/null +++ b/src/superio/nuvoton/nct668xd/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com> +## Copyright (C) 2019 Michael Niewöhner <foss(a)mniewoehner.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT668XD) += superio.c diff --git a/src/superio/nuvoton/nct668xd/nct668Xd.h b/src/superio/nuvoton/nct668xd/nct668Xd.h new file mode 100644 index 0000000..6b74b2d --- /dev/null +++ b/src/superio/nuvoton/nct668xd/nct668Xd.h @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com> + * Copyright (C) 2019 Michael Niewöhner <foss(a)mniewoehner.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_NUVOTON_NCT668XD_H +#define SUPERIO_NUVOTON_NCT668XD_H + +/* WARNING! + * NCT668XD is a "new generation" SuperIO, which implements parts of its + * functionality in firmware. That means one should check if the desired + * function/register is mentioned in the EC Space datasheet before trying + * to modify any registers in HW. + * Both datasheets (HW and EC Space) are available on request from Nuvoton. + * + * These are the warnings from the datasheet: + * 1. All GPIO pin functions should always be customized by firmware. BIOS / + * Driver should not touch all configuration registers here and related IO + * ports unless firmware opens them. + * 2. Under any situations, CR30h should always be controlled by EC and never + * be opened for BIOS / Drivers !! + * 3. Some GPIO pin functions were configured when related SW functions of EC + * Space were enabled. For such situations BIOS or application programs + * should not alter these setting to avoid abnormal function of underlying + * firmware. Please refer to EC Space Specification before going to change + * any configuration setting of GPIO pins. + */ + +/* Logical Device Numbers (LDN) */ +#define NCT668XD_PP 0x01 /* Parallel Port */ +#define NCT668XD_SP1 0x02 /* UART A */ +#define NCT668XD_SP2 0x03 /* UART B, IR */ +#define NCT668XD_KBC 0x05 /* Keyboard Controller */ +#define NCT668XD_CIR 0x06 /* Consumer IR */ +#define NCT668XD_GPIO01234567 0x07 /* GPIO 0-7 */ +#define NCT668XD_PORT80 0x08 /* Port 80 UART */ +#define NCT668XD_GPIO89 0x09 /* GPIO 8-9, GPIO 1-8 Alternate \ + * Func., GPIO 0-1 Enhance Group \ + */ +#define NCT668XD_ACPI 0x0A /* ACPI */ +#define NCT668XD_EC 0x0B /* EC Space */ +#define NCT668XD_DSLP_PWRFAULT 0x0D /* Deep Sleep, Power Fault */ +#define NCT668XD_FAN_ASSIGN 0x0E /* Fan Assignment */ + +/* Virtual LDNs */ +#define NCT668XD_WDT1 ((0 << 8) | NCT668XD_WDT1_WDTMEM_GPIO01) +#define NCT668XD_WDTMEM ((4 << 8) | NCT668XD_WDT1_WDTMEM_GPIO01) +#define NCT668XD_GPIO0 ((0 << 8) | NCT668XD_GPIO01234567) +#define NCT668XD_GPIO1 ((1 << 8) | NCT668XD_GPIO01234567) +#define NCT668XD_GPIO2 ((2 << 8) | NCT668XD_GPIO01234567) +#define NCT668XD_GPIO3 ((3 << 8) | NCT668XD_GPIO01234567) +#define NCT668XD_GPIO4 ((4 << 8) | NCT668XD_GPIO01234567) +#define NCT668XD_GPIO5 ((5 << 8) | NCT668XD_GPIO01234567) +#define NCT668XD_GPIO6 ((6 << 8) | NCT668XD_GPIO01234567) +#define NCT668XD_GPIO7 ((7 << 8) | NCT668XD_GPIO01234567) +#define NCT668XD_GPIO8 ((0 << 8) | NCT668XD_GPIO89) +#define NCT668XD_GPIO9 ((1 << 8) | NCT668XD_GPIO89) +#define NCT668XD_DS5 ((0 << 8) | NCT668XD_DS) +#define NCT668XD_DS3 ((1 << 8) | NCT668XD_DS) +#define NCT668XD_PCHDSW ((3 << 8) | NCT668XD_DS) +#define NCT668XD_DSWWOPT ((4 << 8) | NCT668XD_DS) +#define NCT668XD_DS3OPT ((5 << 8) | NCT668XD_DS) +#define NCT668XD_DSDSS ((6 << 8) | NCT668XD_DS) +#define NCT668XD_DSPU ((7 << 8) | NCT668XD_DS) + + +#endif /* SUPERIO_NUVOTON_NCT668XD_H */ diff --git a/src/superio/nuvoton/nct668xd/superio.c b/src/superio/nuvoton/nct668xd/superio.c new file mode 100644 index 0000000..99d448d --- /dev/null +++ b/src/superio/nuvoton/nct668xd/superio.c @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2015 Matt DeVillier <matt.devillier(a)gmail.com> + * Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com> + * Copyright (C) 2019 Michael Niewöhner <foss(a)mniewoehner.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include <superio/conf_mode.h> + +#include "nct668Xd.h" + + +static void nct668Xd_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case NCT668XD_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = nct668Xd_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, NCT668XD_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, + 0x0ff8, }, + { NULL, NCT668XD_SP1, PNP_IO0 | PNP_IRQ0, + 0x0ff8, }, + { NULL, NCT668XD_SP2, PNP_IO0 | PNP_IRQ0, + 0x0ff8, }, + { NULL, NCT668XD_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, + 0x0fff, 0x0fff, }, + { NULL, NCT668XD_CIR, PNP_IO0 | PNP_IRQ0, + 0x0ff8, }, + { NULL, NCT668XD_PORT80}, + { NULL, NCT668XD_ACPI}, + { NULL, NCT668XD_EC, PNP_IO0 | PNP_IRQ0, + 0x0ff8, }, + { NULL, NCT668XD_DSLP_PWRFAULT}, + { NULL, NCT668XD_FAN_ASSIGN}, + { NULL, NCT668XD_WDT1}, + { NULL, NCT668XD_WDTMEM}, + { NULL, NCT668XD_GPIO0}, + { NULL, NCT668XD_GPIO1}, + { NULL, NCT668XD_GPIO2}, + { NULL, NCT668XD_GPIO3}, + { NULL, NCT668XD_GPIO4}, + { NULL, NCT668XD_GPIO5}, + { NULL, NCT668XD_GPIO6}, + { NULL, NCT668XD_GPIO7}, + { NULL, NCT668XD_GPIO8}, + { NULL, NCT668XD_GPIO9}, + { NULL, NCT668XD_DS5}, + { NULL, NCT668XD_DS3}, + { NULL, NCT668XD_PCHDSW}, + { NULL, NCT668XD_DSWWOPT}, + { NULL, NCT668XD_DS3OPT}, + { NULL, NCT668XD_DSDSS}, + { NULL, NCT668XD_DSPU}, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nuvoton_nct668Xd_ops = { + CHIP_NAME("NUVOTON NCT668XD Super I/O") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/34948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78eca4ba2948c36a386306887f62773580f6e444 Gerrit-Change-Number: 34948 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

4 30

Change in coreboot[master]: x86/lapic: Set EXTINT on BSP only
by Felix Held (Code Review) 17 Oct '21

17 Oct '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42434 ) Change subject: x86/lapic: Set EXTINT on BSP only ...................................................................... x86/lapic: Set EXTINT on BSP only aac79e0b8f4777f8a912ccdfc483755b7a4da52c changed the LAPIC delivery mode for both the BSP and the APs. The change on the APs caused a regression that massively slows down the boot process. Configuring the AP's LAPIC delivery mode to fixed mode fixes this regression. Change-Id: I78490d2cbe3d9f52e10ef2471508263fd6c146ba Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/cpu/x86/lapic/lapic.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/42434/1 diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 653c3b2..2e04464 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -31,6 +31,8 @@ (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING); if (boot_cpu()) lvt0_val = SET_LAPIC_DELIVERY_MODE(lvt0_val, LAPIC_MODE_EXINT); + else + lvt0_val = SET_LAPIC_DELIVERY_MODE(lvt0_val, LAPIC_MODE_FIXED); lapic_write_around(LAPIC_LVT0, lvt0_val); lapic_write_around(LAPIC_LVT1, -- To view, visit https://review.coreboot.org/c/coreboot/+/42434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78490d2cbe3d9f52e10ef2471508263fd6c146ba Gerrit-Change-Number: 42434 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

10 55

Change in coreboot[master]: [WIP] 3rdparty/libgfxinit: Update submodule pointer
by Angel Pons (Code Review) 15 Oct '21

15 Oct '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46636 ) Change subject: [WIP] 3rdparty/libgfxinit: Update submodule pointer ...................................................................... [WIP] 3rdparty/libgfxinit: Update submodule pointer This brings in improvements for Coffee Lake platforms, some workarounds and a sloppy LSPCON mode switch implementation. Tested on Librem WHL, where it fixes complete system hangs and HDMI through the DP175 LSPCON. Change-Id: Ia09a98860903192cd87e11ab12a8a7134e2333ab Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M 3rdparty/libgfxinit 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/46636/1 diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index 3318bf2..5d67c0a 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit 3318bf26803c77d41b18bef6d7ae4e051b97f9f2 +Subproject commit 5d67c0af63aa1b0ef899fecc251dcf9d1120bf07 -- To view, visit https://review.coreboot.org/c/coreboot/+/46636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia09a98860903192cd87e11ab12a8a7134e2333ab Gerrit-Change-Number: 46636 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: sc7180: Add display dsi interface programming [Patch 2 of 3]
by Ravi kumar (Code Review) 28 Sep '21

28 Sep '21

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39614 ) Change subject: sc7180: Add display dsi interface programming [Patch 2 of 3] ...................................................................... sc7180: Add display dsi interface programming [Patch 2 of 3] This change adds support for sc7180 dsi interface host programming and target specific hardware resource (ex: dsi-edp bridge/backlight) configuration. Change-Id: Ie64354ce8bc2a64b891fb9478fbca38d6ec4c321 Signed-off-by: Vinod Polimera <vpolimer(a)codeaurora.org> --- A src/soc/qualcomm/sc7180/display/dsi.c A src/soc/qualcomm/sc7180/display/dsi_panel_display.c A src/soc/qualcomm/sc7180/display/target_sc7180.c A src/soc/qualcomm/sc7180/include/soc/display/mipi_dsi.h A src/soc/qualcomm/sc7180/include/soc/display/panel_display.h A src/soc/qualcomm/sc7180/include/soc/display/target_sc7180.h 6 files changed, 1,710 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/39614/1 diff --git a/src/soc/qualcomm/sc7180/display/dsi.c b/src/soc/qualcomm/sc7180/display/dsi.c new file mode 100644 index 0000000..6967ff5 --- /dev/null +++ b/src/soc/qualcomm/sc7180/display/dsi.c @@ -0,0 +1,890 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/mmio.h> +#include <endian.h> +#include <console/console.h> +#include <delay.h> +#include <string.h> +#include <stdlib.h> +#include <soc/mdss_6_2_0.h> +#include <soc/display/msm_panel.h> +#include <soc/display/mipi_dsi.h> +#include <soc/display/dsi_phy.h> + +mdss_dsi_phy_ftable phy_intf; + +void mdss_dsi_panel_shutdown(struct msm_panel_info *pinfo); + +int mdss_dsi_host_init(struct mipi_panel_info *mipi, + uint32_t dual_dsi, + uint32_t broadcast); + +int mdss_dsi_panel_initialize(struct mipi_panel_info *mipi, + uint32_t broadcast); + +int mdss_dsi_reset(struct mipi_panel_info *mipi, uint32_t dual_dsi); + +int mdss_dsi_clear_intr(struct mipi_panel_info *mipi, uint32_t dual_dsi); + +int mdss_dsi_set_intr(uint32_t ctl_base); + +void mdss_dsi_clock_config(uint32_t ctl_base); + + +static int mdss_dsi_cmd_dma_trigger_for_panel(char dual_dsi, + uint32_t ctl_base, + uint32_t sctl_base) +{ + uint32_t ReadValue; + uint32_t count = 0; + int status = 0; + uint32_t base = dual_dsi ? sctl_base : ctl_base; + + mdss_dsi_set_intr(ctl_base); + writel(0x1, ctl_base + CMD_MODE_DMA_SW_TRIGGER); + dsb(); + + if (dual_dsi) { + mdss_dsi_set_intr(sctl_base); + writel(0x1, sctl_base + CMD_MODE_DMA_SW_TRIGGER); + dsb(); + } + + ReadValue = readl(base + INT_CTRL) & 0x00000001; + + while (ReadValue != 0x00000001) { + ReadValue = readl(base + INT_CTRL) & 0x00000001; + count++; + if (count > 0xffff) { + status = FAIL; + printk(BIOS_ERR, + "Panel CMD: count :%d command mode dma test failed\n",count); + printk(BIOS_ERR, + "Panel CMD: read value = %x, addr=%x\n", + ReadValue, (base + INT_CTRL)); + return status; + } + } + + writel((readl(base + INT_CTRL) | 0x01000001), base + INT_CTRL); + return status; +} + +static int mdss_dsi_wait4_video_done(uint32_t ctl_base) +{ + unsigned long read; + unsigned long count = 0; + int status = 0; + + /* If video mode is not enabled, return here */ + if ((readl(ctl_base + CTRL) & BIT(1)) == 0) + return 0; + + read = readl(ctl_base + INT_CTRL); + + /* Enable VIDEO MODE DONE MASK and clear the interrupt */ + read = read | DSI_VIDEO_MODE_DONE_MASK | DSI_VIDEO_MODE_DONE_AK; + writel(read, ctl_base + INT_CTRL); + dsb(); + + do { + read = readl(ctl_base + INT_CTRL) & DSI_VIDEO_MODE_DONE_STAT; + count++; + + if (count > 0xffff) { + status = FAIL; + printk(BIOS_ERR,"Panel CMD: Did not receive video mode done""interrupt\n"); + return status; + } + + } while (!read); + + writel((readl(ctl_base + INT_CTRL) | 0x01000001), ctl_base + INT_CTRL); + printk(BIOS_INFO,"Panel wait_4_video_done: Received video mode done ack\n"); + + /* Skip BLLP 4ms */ + mdelay(4); + + return status; +} + +int mdss_dsi_cmds_tx(struct mipi_panel_info *mipi, + struct mipi_dsi_cmd *cmds, + int count, + char dual_dsi) +{ + + struct mipi_dsi_cmd *cm; + uint8_t pload[256]; + size_t off; + uint32_t size; + uint32_t len; + uint32_t ctl_base, sctl_base; + bool use_tpg = true; + int data = 0; + int ret = 0; + int i = 0; + int j = 0; + uint32_t *bp = NULL; + + /* if dest controller is not specified, default to DSI0 */ + if (!mipi) { + ctl_base = MIPI_DSI0_BASE; + sctl_base = MIPI_DSI1_BASE; + } else { + ctl_base = mipi->ctl_base; + sctl_base = mipi->sctl_base; + } + + /* Align pload at 8 byte boundary */ + off = (size_t) pload; + off &= 0x07; + + if (off) + off = 8 - off; + + off += (size_t) pload; + cm = cmds; + + for (i = 0; i < count; i++) { + /* Wait for VIDEO_MODE_DONE */ + ret = mdss_dsi_wait4_video_done(ctl_base); + + if (ret) + goto wait4video_error; + + /* The payload size has to be a multiple of 4 */ + size = cm->size; + size &= 0x03; + + if (size) + size = 4 - size; + + size += cm->size; + memcpy((uint8_t *)off, (cm->payload), size); + + if (use_tpg == false) { + writel(off, ctl_base + DMA_CMD_OFFSET); + writel(size, ctl_base + DMA_CMD_LENGTH); + + if (dual_dsi) { + writel(off, sctl_base + DMA_CMD_OFFSET); + writel(size, sctl_base + DMA_CMD_LENGTH); + } + + dsb(); + } + else { + data = 0; + bp = (uint32_t *)off; + len = ALIGN(size, 4); + + if (len > DMA_TPG_FIFO_LEN) { + cm++; + continue; + } + + data = BIT(16) | BIT(17); /* select CMD_DMA_PATTERN_SEL to 3 */ + data |= BIT(2); /* select CMD_DMA_FIFO_MODE to 1 */ + data |= BIT(1); + + writel(data, ctl_base + TEST_PATTERN_GEN_CTRL); + + for (j = 0; j < len; j += 4) { + writel(*bp, ctl_base + TEST_PATTERN_GEN_CMD_DMA_INIT_VAL); + wmb(); /* Ensure write happens before next command */ + bp++; + } + + if ((len % 8) != 0) + writel(0x0, ctl_base + TEST_PATTERN_GEN_CMD_DMA_INIT_VAL); + + writel(len, ctl_base + DMA_CMD_LENGTH); + wmb(); /* make sure DMA length is programmed */ + + writel(0x01, ctl_base + CMD_MODE_DMA_SW_TRIGGER); + wmb(); /* make sure DMA trigger happens */ + + + } + + ret += mdss_dsi_cmd_dma_trigger_for_panel(dual_dsi, ctl_base, sctl_base); + + /* Reset the DMA TPG FIFO */ + writel(0x1, ctl_base + TPG_DMA_FIFO_RESET); + wmb(); /* make sure FIFO reset happens */ + + writel(0x0, ctl_base + TPG_DMA_FIFO_RESET); + wmb(); /* make sure FIFO reset happens */ + + /* Disable CMD_DMA_TPG */ + writel(0x0, ctl_base + TEST_PATTERN_GEN_CTRL); + + if (cm->wait) + mdelay(cm->wait); + else + udelay(80); + + cm++; + } + +wait4video_error: + return ret; +} + +int mdss_dsi_cmds_rx(struct mipi_panel_info *mipi, + uint32_t **rp, + int rp_len, + int rdbk_len) +{ + uint32_t *lp, data; + uint32_t *dp; + int i, off; + int rlen, res; + uint32_t ctl_base; + + /* if dest controller is not specified, default to DSI0 */ + if (!mipi) + ctl_base = MIPI_DSI0_BASE; + else + ctl_base = mipi->ctl_base; + + if (rdbk_len > rp_len) + return 0; + + if (rdbk_len <= 2) + rlen = 4; /* short read */ + else + rlen = MIPI_DSI_MRPS + 6; /* 4 bytes header + 2bytes crc */ + + if (rlen > MIPI_DSI_REG_LEN) + return 0; + + res = rlen & 0x03; + + rlen += res; /* 4 byte align */ + lp = *rp; + + rlen += 3; + rlen >>= 2; + + if (rlen > 4) + rlen = 4; /* 4 x 32 bits registers only */ + + off = RDBK_DATA0; + off += ((rlen - 1) * 4); + + for (i = 0; i < rlen; i++) { + data = readl(ctl_base + off); + *lp = ntohl(data); /* to network byte order */ + lp++; + + off -= 4; + } + + if (rdbk_len > 2) { + /* First 4 bytes + paded bytes will be header next + * len bytes would be payload + */ + for (i = 0; i < rdbk_len; i++) { + dp = *rp; + dp[i] = dp[(res + i) >> 2]; + } + } + return rdbk_len; +} + +static void mdss_dsi_force_clk_lane_hs(struct mipi_panel_info *mipi, + uint32_t dual_dsi) +{ + uint32_t tmp; + + if (dual_dsi) { + tmp = readl(mipi->sctl_base + LANE_CTL); + tmp |= BIT(28); + writel(tmp, mipi->sctl_base + LANE_CTL); + } + + tmp = readl(mipi->ctl_base + LANE_CTL); + tmp |= BIT(28); + writel(tmp, mipi->ctl_base + LANE_CTL); +} + +int mdss_dsi_host_init(struct mipi_panel_info *mipi, uint32_t + dual_dsi, uint32_t broadcast) +{ + uint8_t DMA_STREAM1 = 0; // for mdp display processor path + uint8_t EMBED_MODE1 = 1; // from frame buffer + uint8_t POWER_MODE2 = 1; // from frame buffer + uint8_t PACK_TYPE1 = 0; // long packet + uint8_t VC1 = 0; + uint8_t DT1 = 0; // non embedded mode + uint8_t WC1 = 0; // for non embedded mode only + uint8_t DLNx_EN; + uint32_t timing_ctl = 0; + uint32_t ctrl_mode = BIT(8)|BIT(0); //Enable DSI and CLKlane. + uint32_t tmp = 0; + + switch (mipi->num_of_lanes) { + default: + case 1: + DLNx_EN = 1; // 1 lane + break; + + case 2: + DLNx_EN = 3; // 2 lane + break; + + case 3: + DLNx_EN = 7; // 3 lane + break; + + case 4: + DLNx_EN = 0x0F; /* 4 lanes */ + break; + } + + timing_ctl = ((mipi->t_clk_post << 8) | mipi->t_clk_pre); + + if (mipi->cmds_post_tg) { + /* + * Need to send pixel data before sending the ON commands + * so need to configure controller to VIDEO MODE. + */ + ctrl_mode |= BIT(1); + } + else + { + //Default is command mode to send cmds. + ctrl_mode |= BIT(2); + } + + if (dual_dsi) { + writel(0x0001, mipi->sctl_base + SOFT_RESET); + writel(0x0000, mipi->sctl_base + SOFT_RESET); + + /* Turn on all DSI Clks */ + writel((0 << 16) | 0x3f, mipi->sctl_base + CLK_CTRL); + writel(DMA_STREAM1 << 8 | 0x04, mipi->sctl_base + TRIG_CTRL); + + writel(0 << 30 | DLNx_EN << 4 | ctrl_mode, mipi->sctl_base + CTRL); + + writel(broadcast << 31 | EMBED_MODE1 << 28 | POWER_MODE2 << 26 + | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1, + mipi->sctl_base + COMMAND_MODE_DMA_CTRL); + + writel(timing_ctl, mipi->sctl_base + TIMING_CTL); + + if ((mipi->mode == DSI_CMD_MODE) && + (readl(mipi->sctl_base) >= DSI_HW_REV_241)) { + tmp = readl(mipi->sctl_base + COMMAND_MODE_MDP_CTRL2); + tmp |= BIT(16); /* enable burst mode */ + writel(tmp, mipi->sctl_base + COMMAND_MODE_MDP_CTRL2); + } + + writel(((mipi->rx_eot_ignore & 0x1) << 4) | + (mipi->tx_eot_append & 0x1), + mipi->sctl_base + EOT_PACKET_CTRL); + } + + /* Turn on all DSI Clks */ + writel((0 << 16) | 0x3f, mipi->ctl_base + CLK_CTRL); + writel(DMA_STREAM1 << 8 | 0x04, mipi->ctl_base + TRIG_CTRL); + + writel(0 << 30 | DLNx_EN << 4 | ctrl_mode, mipi->ctl_base + CTRL); + writel(broadcast << 31 | EMBED_MODE1 << 28 | POWER_MODE2 << 26 + | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1, + mipi->ctl_base + COMMAND_MODE_DMA_CTRL); + + writel(timing_ctl, mipi->ctl_base + TIMING_CTL); + + if ((mipi->mode == DSI_CMD_MODE) && + (readl(mipi->ctl_base) >= DSI_HW_REV_241)) { + tmp = readl(mipi->ctl_base + COMMAND_MODE_MDP_CTRL2); + tmp |= BIT(16); /* enable burst mode */ + writel(tmp, mipi->ctl_base + COMMAND_MODE_MDP_CTRL2); + } + + writel(((mipi->rx_eot_ignore & 0x1) << 4) | (mipi->tx_eot_append & 0x1), + mipi->ctl_base + EOT_PACKET_CTRL); + + return 0; +} + +int mdss_dsi_clear_intr(struct mipi_panel_info *mipi, uint32_t dual_dsi) +{ + uint32_t uIntrStatusReg = readl(mipi->ctl_base + INT_CTRL); + + /* Get CMD mode DMA Done and map to generic HAL interface. */ + uIntrStatusReg = HWIO_OUT_FLD(uIntrStatusReg, INT_CTRL, DSI_CMD_MODE_DMA_DONE_AK, 1); + + /* Get CMD mode MDP Done and map to generic HAL interface. */ + uIntrStatusReg = HWIO_OUT_FLD(uIntrStatusReg, INT_CTRL, DSI_CMD_MODE_MDP_DONE_AK, 1); + + /* Get Video mode Done and map to generic HAL interface. */ + uIntrStatusReg = HWIO_OUT_FLD(uIntrStatusReg, INT_CTRL, DSI_VIDEO_MODE_DONE_AK, 1); + + /* Get the BTA done and map to generic HAL interface. clear the interrupt status bit */ + uIntrStatusReg = HWIO_OUT_FLD(uIntrStatusReg, INT_CTRL, DSI_BTA_DONE_AK, 1); + + uIntrStatusReg = HWIO_OUT_FLD(uIntrStatusReg, INT_CTRL, DSI_ERROR_AK, 1); + + writel(uIntrStatusReg, mipi->ctl_base + INT_CTRL); + writel(0x13FF3BFF, mipi->ctl_base + ERR_INT_MASK0); + + if (dual_dsi) { + writel(uIntrStatusReg, mipi->sctl_base + INT_CTRL); + writel(0x13FF3BFF, mipi->sctl_base + ERR_INT_MASK0); + } + + return 0; +} + +int mdss_dsi_set_intr(uint32_t ctl_base) +{ + uint32_t uRegVal = 0; + + /* Map CMD mode DMA Done to HW interrupts. */ + uRegVal = HWIO_OUT_FLD(uRegVal, INT_CTRL, DSI_CMD_MODE_DMA_DONE_MASK, 1); + + /* Map CMD mode MDP Done to HW interrupts. */ + uRegVal = HWIO_OUT_FLD(uRegVal, INT_CTRL, DSI_CMD_MODE_MDP_DONE_MASK, 1); + + /* Map Video mode Done to HW interrupts. */ + uRegVal = HWIO_OUT_FLD(uRegVal, INT_CTRL, DSI_VIDEO_MODE_DONE_MASK, 1); + + /* If any Error interrupt has been enabled? */ + uRegVal = HWIO_OUT_FLD(uRegVal, INT_CTRL, DSI_ERROR_MASK, 1); + + /* If need to enable DSI_BTA_DONE */ + uRegVal = HWIO_OUT_FLD(uRegVal, INT_CTRL, DSI_BTA_DONE_MASK, 1); + + writel(uRegVal, ctl_base + INT_CTRL); + + return 0; +} +int mdss_dsi_reset(struct mipi_panel_info *mipi, uint32_t dual_dsi) +{ + /* Disable DSI Controller, DSI lane states, + * DSI command-mode and DSI video-mode engines + */ + writel(0x0, mipi->ctl_base + CTRL); + + // DSI soft reset + writel(0x0001, mipi->ctl_base + SOFT_RESET); + writel(0x0000, mipi->ctl_base + SOFT_RESET); + + // set hs timer count speed + writel(0x0004EA60, mipi->ctl_base + HS_TIMER_CTRL); + + // dma fifo reset + writel(0x0001, mipi->ctl_base + TPG_DMA_FIFO_RESET); + writel(0x0000, mipi->ctl_base + TPG_DMA_FIFO_RESET); + + if (dual_dsi) { + /* Disable DSI Controller, DSI lane states, + * DSI command-mode and DSI video-mode engines + */ + writel(0x0, mipi->sctl_base + CTRL); + + // DSI soft reset + writel(0x0001, mipi->sctl_base + SOFT_RESET); + writel(0x0000, mipi->sctl_base + SOFT_RESET); + + // set hs timer count speed + writel(0x0004EA60, mipi->sctl_base + HS_TIMER_CTRL); + + // dma fifo reset + writel(0x0001, mipi->sctl_base + TPG_DMA_FIFO_RESET); + writel(0x0000, mipi->sctl_base + TPG_DMA_FIFO_RESET); + } + + return NO_ERROR; +} + +void mdss_dsi_panel_shutdown(struct msm_panel_info *pinfo) +{ + unsigned long read_val = 0; + uint32_t ctl_base = pinfo->mipi.ctl_base; + uint32_t sctl_base = pinfo->mipi.sctl_base; + + if (pinfo->mipi.panel_off_cmds) { + /* + * Once MDP TG is disabled, reset of DSI controller is + * needed before we send panel OFF commands. + */ + if (pinfo->type == MIPI_VIDEO_PANEL) { + read_val = readl(ctl_base + CTRL); + + writel((read_val & ~BIT(0)), ctl_base + CTRL); + writel(0x0001, ctl_base + SOFT_RESET); + dsb(); + + writel(0x0000, ctl_base + SOFT_RESET); + dsb(); + + /* Enable cmd mode only */ + writel(((read_val & ~BIT(1)) | BIT(2)),ctl_base + CTRL); + } + + if (pinfo->mipi.broadcast) { + if (pinfo->type == MIPI_VIDEO_PANEL) { + read_val = readl(sctl_base + CTRL); + writel((read_val & ~BIT(0)),sctl_base + CTRL); + + writel(0x0001, sctl_base + SOFT_RESET); + dsb(); + + writel(0x0000, sctl_base + SOFT_RESET); + dsb(); + + writel(((read_val & ~BIT(1)) | BIT(2)), + sctl_base + CTRL); + } + } + mdss_dsi_cmds_tx(&pinfo->mipi, pinfo->mipi.panel_off_cmds, + pinfo->mipi.num_of_panel_off_cmds, + pinfo->mipi.broadcast); + } +} + +int mdss_dsi_panel_initialize(struct mipi_panel_info *mipi, + uint32_t broadcast) +{ + int status = 0; + uint32_t ctrl_mode = 0; + + if (!mipi->panel_on_cmds) + goto end; + + ctrl_mode = readl(mipi->ctl_base + CTRL); + + /* Enable command mode before sending the commands. */ + writel(ctrl_mode | 0x04, mipi->ctl_base + CTRL); + + if (broadcast) + writel(ctrl_mode | 0x04, mipi->sctl_base + CTRL); + + mdelay(500); + + status = mdss_dsi_cmds_tx(mipi, + mipi->panel_on_cmds, + mipi->num_of_panel_on_cmds, + broadcast); + + writel(ctrl_mode, mipi->ctl_base + CTRL); + + if (broadcast) + writel(ctrl_mode, mipi->sctl_base + CTRL); + +end: + return status; +} + + + +int mdss_dsi_video_mode_config(struct msm_panel_info *pinfo, + uint16_t disp_width, + uint16_t disp_height, + uint16_t img_width, + uint16_t img_height, + uint16_t hsync_porch0_fp, + uint16_t hsync_porch0_bp, + uint16_t vsync_porch0_fp, + uint16_t vsync_porch0_bp, + uint16_t hsync_width, + uint16_t vsync_width, + uint16_t dst_format, + uint16_t traffic_mode, + uint8_t lane_en, + uint8_t pulse_mode_hsa_he, + uint32_t low_pwr_stop_mode, + uint8_t eof_bllp_pwr, + uint8_t interleav, + uint32_t ctl_base) +{ + int status = 0; + int last_line_interleave_en = 0; + struct dsc_desc *dsc = NULL; + + if (pinfo->compression_mode == COMPRESSION_DSC) + dsc = &pinfo->dsc; + + /*Check if EOF_BLLP_PWR_MODE bit is set*/ + if (eof_bllp_pwr & 0x8) + last_line_interleave_en = 1; + + mdss_dsi_clock_config(ctl_base); + + writel(((disp_width + hsync_porch0_bp) << 16) | hsync_porch0_bp, + ctl_base + VIDEO_MODE_ACTIVE_H); + + writel(((disp_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp), + ctl_base + VIDEO_MODE_ACTIVE_V); + + if (mdp_get_revision() >= MDSS_MDP_HW_REV_620) { + writel(((disp_height + vsync_porch0_fp + + vsync_porch0_bp - 1) << 16) | + (disp_width + hsync_porch0_fp + + hsync_porch0_bp - 1), + + ctl_base + VIDEO_MODE_TOTAL); + } + else { + writel(((disp_height + vsync_porch0_fp + + vsync_porch0_bp) << 16) | + (disp_width + hsync_porch0_fp + + hsync_porch0_bp), + ctl_base + VIDEO_MODE_TOTAL); + } + + writel((hsync_width << 16) | 0, ctl_base + VIDEO_MODE_HSYNC); + writel(0 << 16 | 0, ctl_base + VIDEO_MODE_VSYNC); + writel(vsync_width << 16 | 0, ctl_base + VIDEO_MODE_VSYNC_VPOS); + + writel(low_pwr_stop_mode << 15 | eof_bllp_pwr << 12 | traffic_mode << 8 | dst_format << 4 | 0x0, + ctl_base + VIDEO_MODE_CTRL); + + writel(0x0004EA60, ctl_base + HS_TIMER_CTRL); + + writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 + | 0x103, ctl_base + CTRL); + + if (dsc) { + if (dsc->dsi_dsc_config) + dsc->dsi_dsc_config(pinfo->mipi.ctl_base, + DSI_VIDEO_MODE, dsc); + } + + return status; +} + +int mdss_dsi_config(struct msm_fb_panel_data *panel) +{ + int ret = NO_ERROR; + struct msm_panel_info *pinfo; + struct mipi_panel_info *mipi; + struct dsc_desc *dsc = NULL; + struct mipi_dsi_cmd cmd; + + if (!panel) + return ERROR; + + pinfo = &(panel->panel_info); + mipi = &(pinfo->mipi); + + + if (pinfo->compression_mode == COMPRESSION_DSC) { + dsc = &pinfo->dsc; + if (dsc) { + if (dsc->dsc2buf) + dsc->dsc2buf(pinfo); + } + } + + printk(BIOS_INFO, "ctl_base=0x%08x, phy_base=0x%08x\n", mipi->ctl_base,mipi->phy_base); + + mdss_dsi_reset(mipi, mipi->dual_dsi); + + if (mdss_dsi_phy_intf_setup(DSI_PLL_TYPE_10NM, &phy_intf) != NO_ERROR) { + printk(BIOS_ERR, "mdss_dsi_phy_intf_setup returned error\n"); + return ERROR; + } + + if (phy_intf.dsi_phy_init != NULL) + phy_intf.dsi_phy_init(pinfo); + else { + printk(BIOS_ERR, "dsi_phy_init is NULL\n"); + return ERROR; + } + + ret = mdss_dsi_host_init(mipi, + mipi->dual_dsi, + mipi->broadcast); + if (ret) { + printk(BIOS_ERR, "dsi host init error\n"); + goto error; + } + + if (panel->pre_init_func) { + ret = panel->pre_init_func(); + if (ret) { + printk(BIOS_ERR, "pre_init_func error\n"); + goto error; + } + } + + if (mipi->force_clk_lane_hs) + mdss_dsi_force_clk_lane_hs(mipi, mipi->dual_dsi); + + if (!mipi->cmds_post_tg) { + ret = mdss_dsi_panel_initialize(mipi, mipi->broadcast); + if (ret) { + printk(BIOS_ERR, "dsi panel init error\n"); + goto error; + } + } + + if (dsc) { + cmd.size = DCS_HDR_LEN + DSC_PPS_LEN; + cmd.payload = dsc->pps_buf; + cmd.wait = 0x10; + mdss_dsi_cmds_tx(mipi, &cmd, 1, mipi->broadcast); + } + + if (pinfo->rotate && panel->rotate) + pinfo->rotate(); + + /* Reset DSI Interrupt/Error registers */ + mdss_dsi_clear_intr(mipi, mipi->dual_dsi); + +error: + return ret; +} + +int mdss_dsi_post_on(struct msm_fb_panel_data *panel) +{ + int ret = 0; + struct msm_panel_info *pinfo = &(panel->panel_info); + + if (pinfo->mipi.cmds_post_tg) { + ret = mdss_dsi_panel_initialize(&pinfo->mipi, + pinfo->mipi.broadcast); + if (ret) + printk(BIOS_ERR, "dsi panel init error\n"); + } + + return ret; +} + +int mdss_dsi_cmd_mode_config(struct msm_panel_info *pinfo, + uint16_t disp_width, + uint16_t disp_height, + uint16_t img_width, + uint16_t img_height, + uint16_t dst_format, + uint8_t ystride, + uint8_t lane_en, + uint8_t interleav, + uint32_t ctl_base) +{ + uint16_t dst_fmt = 0; + struct dsc_desc *dsc = NULL; + unsigned int data; + uint32_t uRegVal = 0; + + switch (dst_format) { + case DSI_VIDEO_DST_FORMAT_RGB565: + dst_fmt = DSI_CMD_DST_FORMAT_RGB565; + break; + + case DSI_VIDEO_DST_FORMAT_RGB666: + case DSI_VIDEO_DST_FORMAT_RGB666_LOOSE: + dst_fmt = DSI_CMD_DST_FORMAT_RGB666; + break; + + case DSI_VIDEO_DST_FORMAT_RGB888: + dst_fmt = DSI_CMD_DST_FORMAT_RGB888; + break; + + default: + printk(BIOS_ERR, "unsupported dst format\n"); + return ERROR; + } + + mdss_dsi_clock_config(ctl_base); + + writel(0, ctl_base + CTRL); + writel(0x03f03fe0, ctl_base + ERR_INT_MASK0); + + mdss_dsi_set_intr(ctl_base); + + writel(dst_fmt, ctl_base + COMMAND_MODE_MDP_CTRL); + + if (pinfo->compression_mode == COMPRESSION_DSC) + dsc = &pinfo->dsc; + + if (dsc) { + data = dsc->bytes_per_pkt; + + if (pinfo->mipi.insert_dcs_cmd) + data++; + + data <<= 16; + data |= 0x039; + writel(data, ctl_base + COMMAND_MODE_MDP_STREAM0_CTRL); + writel(data, ctl_base + COMMAND_MODE_MDP_STREAM1_CTRL); + + data = dsc->pic_height << 16; + data |= dsc->pclk_per_line; + writel(data, ctl_base + COMMAND_MODE_MDP_STREAM0_TOTAL); + writel(data, ctl_base + COMMAND_MODE_MDP_STREAM1_TOTAL); + + if (dsc->dsi_dsc_config) + dsc->dsi_dsc_config(pinfo->mipi.ctl_base, + DSI_CMD_MODE, dsc); + } + else { + + writel((img_width * ystride + 1) << 16 | 0x0039, + ctl_base + COMMAND_MODE_MDP_STREAM0_CTRL); + writel((img_width * ystride + 1) << 16 | 0x0039, + ctl_base + COMMAND_MODE_MDP_STREAM1_CTRL); + writel(img_height << 16 | img_width, + ctl_base + COMMAND_MODE_MDP_STREAM0_TOTAL); + writel(img_height << 16 | img_width, + ctl_base + COMMAND_MODE_MDP_STREAM1_TOTAL); + } + + uRegVal = readl(ctl_base+COMMAND_MODE_MDP_DCS_CMD_CTRL); + uRegVal = HWIO_OUT_FLD(uRegVal, COMMAND_MODE_MDP_DCS_CMD_CTRL, INSERT_DCS_COMMAND, 0x01); + + writel(uRegVal, ctl_base + COMMAND_MODE_MDP_DCS_CMD_CTRL); + writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 | 0x105, ctl_base + CTRL); + + uRegVal = 0; + uRegVal = HWIO_OUT_FLD( uRegVal, COMMAND_MODE_DMA_CTRL, EMBEDDED_MODE, 0x01); + uRegVal = HWIO_OUT_FLD( uRegVal, COMMAND_MODE_DMA_CTRL, POWER_MODE, 0x01); //Low power Mode + + writel(uRegVal, ctl_base + COMMAND_MODE_DMA_CTRL); + writel(BIT(28), ctl_base + MISR_CMD_CTRL); //enable MISR cmd ctrl. + + return 0; +} + +void mdss_dsi_clock_config(uint32_t ctl_base) +{ + /* Default to all clock off */ + uint32_t uClkCtrlReg = 0; + + /* Clock for AHI Bus Master, for DMA out from memory */ + uClkCtrlReg = HWIO_OUT_FLD( uClkCtrlReg, CLK_CTRL, DSI_AHBM_SCLK_ON, 1); + uClkCtrlReg = HWIO_OUT_FLD( uClkCtrlReg, CLK_CTRL, DSI_FORCE_ON_DYN_AHBM_HCLK, 1); + + /* Clock for MDP/DSI, for DMA out from MDP */ + uClkCtrlReg = HWIO_OUT_FLD( uClkCtrlReg, CLK_CTRL, DSI_PCLK_ON, 1); + + /* Clock for rest of DSI */ + uClkCtrlReg = HWIO_OUT_FLD( uClkCtrlReg, CLK_CTRL, DSI_AHBS_HCLK_ON, 1); + uClkCtrlReg = HWIO_OUT_FLD( uClkCtrlReg, CLK_CTRL, DSI_DSICLK_ON, 1); + + uClkCtrlReg = HWIO_OUT_FLD( uClkCtrlReg, CLK_CTRL, DSI_BYTECLK_ON, 1); + uClkCtrlReg = HWIO_OUT_FLD( uClkCtrlReg, CLK_CTRL, DSI_ESCCLK_ON, 1); + + writel(uClkCtrlReg, ctl_base + CLK_CTRL); + +} + + diff --git a/src/soc/qualcomm/sc7180/display/dsi_panel_display.c b/src/soc/qualcomm/sc7180/display/dsi_panel_display.c new file mode 100644 index 0000000..35efa9a --- /dev/null +++ b/src/soc/qualcomm/sc7180/display/dsi_panel_display.c @@ -0,0 +1,472 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/mmio.h> +#include <stdlib.h> +#include <console/console.h> +#include <string.h> +#include <soc/mdss_6_2_0.h> +#include <soc/display/panel.h> +#include <soc/display/msm_panel.h> +#include <soc/display/mipi_dsi.h> +#include <soc/display/panel_display.h> +#include <soc/display/target_sc7180.h> + +int dsi_video_panel_config(struct msm_panel_info *pinfo, + struct lcdc_panel_info *plcdc); + +int dsi_cmd_panel_config(struct msm_panel_info *pinfo, + struct lcdc_panel_info *plcdc); + +static int dsi_platform_base_offset_adjust(uint32_t base) +{ + return target_display_get_base_offset(base); +} + +static int dsi_panel_ctl_base_setup(struct msm_panel_info *pinfo, + char *panel_destination) +{ + int base_offset = 0, + base1_offset = 0, + base_phy_offset = 0, + base1_phy_offset = 0; + + /* + * Base offsets may vary for few platforms. Add the difference to get + * proper base offset for the respective platform. + */ + base_offset = dsi_platform_base_offset_adjust(MIPI_DSI0_BASE); + base1_offset = dsi_platform_base_offset_adjust(MIPI_DSI1_BASE); + base_phy_offset = dsi_platform_base_offset_adjust(DSI0_PHY_BASE); + base1_phy_offset = dsi_platform_base_offset_adjust(DSI1_PHY_BASE); + + if (!strcmp(panel_destination, "DISPLAY_1")) { + pinfo->dest = DISPLAY_1; + pinfo->mipi.ctl_base = MIPI_DSI0_BASE + base_offset; + pinfo->mipi.phy_base = DSI0_PHY_BASE + base_phy_offset; + pinfo->mipi.sctl_base = MIPI_DSI1_BASE + base1_offset; + pinfo->mipi.sphy_base = DSI1_PHY_BASE + base1_phy_offset; + + if (pinfo->mipi.use_dsi1_pll) { + printk(BIOS_ERR, + "%s: Invalid combination: DSI0 controller +" + "DSI1 PLL, using DSI0 PLL\n", __func__); + pinfo->mipi.use_dsi1_pll = 0; + } + + } else if (!strcmp(panel_destination, "DISPLAY_2")) { + pinfo->dest = DISPLAY_2; + pinfo->mipi.ctl_base = MIPI_DSI1_BASE + base1_offset; + pinfo->mipi.phy_base = DSI1_PHY_BASE + base1_phy_offset; + pinfo->mipi.sctl_base = MIPI_DSI0_BASE + base_offset; + pinfo->mipi.sphy_base = DSI0_PHY_BASE + base_phy_offset; + + } else { + pinfo->dest = DISPLAY_UNKNOWN; + printk(BIOS_ERR, "%s: Unknown panel destination: %d\n", + __func__, pinfo->dest); + return ERROR; + } + + return NO_ERROR; +} + +int dsi_panel_init(struct msm_panel_info *pinfo, + struct panel_struct *pstruct) +{ + int ret = NO_ERROR; + /* Resolution setting*/ + pinfo->xres = pstruct->panelres->panel_width; + pinfo->yres = pstruct->panelres->panel_height; + pinfo->lcdc.h_back_porch = pstruct->panelres->hback_porch; + pinfo->lcdc.h_front_porch = pstruct->panelres->hfront_porch; + pinfo->lcdc.h_pulse_width = pstruct->panelres->hpulse_width; + pinfo->lcdc.v_back_porch = pstruct->panelres->vback_porch; + pinfo->lcdc.v_front_porch = pstruct->panelres->vfront_porch; + pinfo->lcdc.v_pulse_width = pstruct->panelres->vpulse_width; + pinfo->lcdc.hsync_skew = pstruct->panelres->hsync_skew; + + pinfo->border_top = pstruct->panelres->vtop_border; + pinfo->border_bottom = pstruct->panelres->vbottom_border; + pinfo->border_left = pstruct->panelres->hleft_border; + pinfo->border_right = pstruct->panelres->hright_border; + + printk(BIOS_INFO, "%s: left=%d right=%d top=%d bottom=%d\n", __func__, + pinfo->border_left, pinfo->border_right, + pinfo->border_top, pinfo->border_bottom); + + pinfo->xres += (pinfo->border_left + pinfo->border_right); + pinfo->yres += (pinfo->border_top + pinfo->border_bottom); + + if (pstruct->paneldata->panel_operating_mode & DUAL_PIPE_FLAG) + pinfo->lcdc.dual_pipe = 1; + + if (pstruct->paneldata->panel_operating_mode & PIPE_SWAP_FLAG) + pinfo->lcdc.pipe_swap = 1; + + if (pstruct->paneldata->panel_operating_mode & SPLIT_DISPLAY_FLAG) + pinfo->lcdc.split_display = 1; + + if (pstruct->paneldata->panel_operating_mode & DST_SPLIT_FLAG) + pinfo->lcdc.dst_split = 1; + + if (pstruct->paneldata->panel_operating_mode & DUAL_DSI_FLAG) + pinfo->mipi.dual_dsi = 1; + + if (pstruct->paneldata->panel_operating_mode & USE_DSI1_PLL_FLAG) + pinfo->mipi.use_dsi1_pll = 1; + + /* Color setting*/ + pinfo->lcdc.border_clr = pstruct->color->border_color; + pinfo->lcdc.underflow_clr = pstruct->color->underflow_color; + pinfo->mipi.rgb_swap = pstruct->color->color_order; + pinfo->bpp = pstruct->color->color_format; + + switch (pinfo->bpp) { + case BPP_16: + pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB565; + break; + case BPP_18: + if (pstruct->color->pixel_packing) + pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB666_LOOSE; + else + pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB666; + break; + case BPP_24: + default: + pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888; + break; + } + + /* Panel generic info */ + pinfo->mipi.mode = pstruct->paneldata->panel_type; + + if (pinfo->mipi.mode) + pinfo->type = MIPI_CMD_PANEL; + else + pinfo->type = MIPI_VIDEO_PANEL; + + pinfo->clk_rate = pstruct->paneldata->panel_clockrate; + pinfo->orientation = pstruct->paneldata->panel_orientation; + pinfo->mipi.interleave_mode = pstruct->paneldata->interleave_mode; + pinfo->mipi.broadcast = pstruct->paneldata->panel_broadcast_mode; + pinfo->mipi.vc = pstruct->paneldata->dsi_virtualchannel_id; + pinfo->mipi.frame_rate = pstruct->paneldata->panel_framerate; + pinfo->mipi.stream = pstruct->paneldata->dsi_stream; + pinfo->mipi.mode_gpio_state = pstruct->paneldata->mode_gpio_state; + pinfo->mipi.bitclock = pstruct->paneldata->panel_bitclock_freq; + + if (pinfo->mipi.bitclock) { + /* panel_clockrate is depcrated in favor of bitclock_freq */ + pinfo->clk_rate = pinfo->mipi.bitclock; + } + + pinfo->mipi.use_enable_gpio = pstruct->paneldata->panel_with_enable_gpio; + + ret = dsi_panel_ctl_base_setup(pinfo, + pstruct->paneldata->panel_destination); + + if (ret) + return ret; + + /* Video Panel configuration */ + pinfo->mipi.pulse_mode_hsa_he = pstruct->videopanel->hsync_pulse; + pinfo->mipi.hfp_power_stop = pstruct->videopanel->hfp_power_mode; + pinfo->mipi.hbp_power_stop = pstruct->videopanel->hbp_power_mode; + pinfo->mipi.hsa_power_stop = pstruct->videopanel->hsa_power_mode; + pinfo->mipi.eof_bllp_power_stop = pstruct->videopanel->bllp_eof_power_mode; + pinfo->mipi.bllp_power_stop = pstruct->videopanel->bllp_power_mode; + pinfo->mipi.traffic_mode = pstruct->videopanel->traffic_mode; + pinfo->mipi.eof_bllp_power = pstruct->videopanel->bllp_eof_power; + + /* Command Panel configuration */ + pinfo->mipi.insert_dcs_cmd = pstruct->commandpanel->tedcs_command; + pinfo->mipi.wr_mem_continue = pstruct->commandpanel->tevsync_continue_lines; + pinfo->mipi.wr_mem_start = pstruct->commandpanel->tevsync_rdptr_irqline; + pinfo->mipi.te_sel = pstruct->commandpanel->tepin_select; + pinfo->autorefresh_enable = pstruct->commandpanel->autorefresh_enable; + pinfo->autorefresh_framenum = pstruct->commandpanel->autorefresh_framenumdiv; + + /* Data lane configuraiton */ + pinfo->mipi.num_of_lanes = pstruct->laneconfig->dsi_lanes; + pinfo->mipi.data_lane0 = pstruct->laneconfig->lane0_state; + pinfo->mipi.data_lane1 = pstruct->laneconfig->lane1_state; + pinfo->mipi.data_lane2 = pstruct->laneconfig->lane2_state; + pinfo->mipi.data_lane3 = pstruct->laneconfig->lane3_state; + pinfo->mipi.lane_swap = pstruct->laneconfig->dsi_lanemap; + pinfo->mipi.force_clk_lane_hs = pstruct->laneconfig->force_clk_lane_hs; + + pinfo->mipi.t_clk_post = pstruct->paneltiminginfo->tclk_post; + pinfo->mipi.t_clk_pre = pstruct->paneltiminginfo->tclk_pre; + pinfo->mipi.mdp_trigger = pstruct->paneltiminginfo->dsi_mdp_trigger; + pinfo->mipi.dma_trigger = pstruct->paneltiminginfo->dsi_dma_trigger; + + if (pinfo->compression_mode == COMPRESSION_DSC) { + struct dsc_desc *dsc = &pinfo->dsc; + struct dsc_parameters *dsc_params = NULL; + + if (!pstruct->config) { + printk(BIOS_ERR, + "ERROR: DSC cannot be used without topology_config\n"); + return ERROR; + } + dsc_params = pstruct->config->dsc; + if (!dsc_params) { + printk(BIOS_ERR, "ERROR: DSC params are NULL\n"); + return ERROR; + } + + dsc->major = dsc_params->major; + dsc->minor = dsc_params->minor; + dsc->scr_rev = dsc_params->scr_rev; + dsc->pps_id = dsc_params->pps_id; + dsc->slice_height = dsc_params->slice_height; + dsc->slice_width = dsc_params->slice_width; + dsc->bpp = dsc_params->bpp; + dsc->bpc = dsc_params->bpc; + dsc->slice_per_pkt = dsc_params->slice_per_pkt; + dsc->block_pred_enable = dsc_params->block_prediction; + dsc->enable_422 = 0; + dsc->convert_rgb = 1; + dsc->vbr_enable = 0; + + if (dsc->parameter_calc) + dsc->parameter_calc(pinfo); + } + + pinfo->pre_on = dsi_panel_pre_on; + pinfo->pre_off = dsi_panel_pre_off; + pinfo->on = dsi_panel_post_on; + pinfo->off = dsi_panel_post_off; + pinfo->rotate = dsi_panel_rotation; + pinfo->config = dsi_panel_config; + + return NO_ERROR; +} + +/* Panel Callbacks */ +int dsi_panel_pre_on(void) +{ + return target_display_pre_on(); +} + +int dsi_panel_pre_off(void) +{ + return target_display_pre_off(); +} + +int dsi_panel_post_on(void) +{ + int ret = NO_ERROR; + + ret = target_display_post_on(); + if (ret) + return ret; + + return oem_panel_on(); +} + +int dsi_panel_post_off(void) +{ + int ret = NO_ERROR; + + ret = target_display_post_off(); + if (ret) + return ret; + + return oem_panel_off(); +} + +int dsi_panel_rotation(void) +{ + return oem_panel_rotation(); +} + +int dsi_video_panel_config(struct msm_panel_info *pinfo, + struct lcdc_panel_info *plcdc) +{ + int ret = NO_ERROR; + uint8_t lane_enable = 0; + uint32_t panel_width = pinfo->xres; + uint32_t final_xres, final_yres, final_width; + uint32_t final_height, final_hbp, final_hfp, final_vbp; + uint32_t final_vfp, final_hpw, final_vpw, low_pwr_stop; + struct dsc_desc *dsc = NULL; + + if (pinfo->mipi.dual_dsi) + panel_width = panel_width / 2; + + if (pinfo->mipi.data_lane0) + lane_enable |= (1 << 0); + if (pinfo->mipi.data_lane1) + lane_enable |= (1 << 1); + if (pinfo->mipi.data_lane2) + lane_enable |= (1 << 2); + if (pinfo->mipi.data_lane3) + lane_enable |= (1 << 3); + + if (pinfo->compression_mode == COMPRESSION_DSC) { + dsc = &pinfo->dsc; + panel_width = dsc->pclk_per_line; + } + + final_xres = panel_width; + final_width = panel_width + pinfo->lcdc.xres_pad; + final_yres = pinfo->yres; + final_height = pinfo->yres + pinfo->lcdc.yres_pad; + final_hbp = pinfo->lcdc.h_back_porch; + final_hfp = pinfo->lcdc.h_front_porch; + final_vbp = pinfo->lcdc.v_back_porch; + final_vfp = pinfo->lcdc.v_front_porch; + final_hpw = pinfo->lcdc.h_pulse_width; + final_vpw = pinfo->lcdc.v_pulse_width; + low_pwr_stop = (pinfo->mipi.hfp_power_stop << 8) | + (pinfo->mipi.hbp_power_stop << 4) | + pinfo->mipi.hsa_power_stop; + + ret = mdss_dsi_video_mode_config(pinfo, + final_width, final_height, + final_xres, final_yres, + final_hfp, final_hbp + final_hpw, + final_vfp, final_vbp + final_vpw, + final_hpw, final_vpw, + pinfo->mipi.dst_format, + pinfo->mipi.traffic_mode, + lane_enable, + pinfo->mipi.pulse_mode_hsa_he, + low_pwr_stop, + pinfo->mipi.eof_bllp_power, + pinfo->mipi.interleave_mode, + pinfo->mipi.ctl_base); + + if (pinfo->mipi.dual_dsi) + ret = mdss_dsi_video_mode_config(pinfo, + final_width, final_height, + final_xres, final_yres, + final_hfp, final_hbp + final_hpw, + final_vfp, final_vbp + final_vpw, + final_hpw, final_vpw, + pinfo->mipi.dst_format, + pinfo->mipi.traffic_mode, + lane_enable, + pinfo->mipi.pulse_mode_hsa_he, + low_pwr_stop, + pinfo->mipi.eof_bllp_power, + pinfo->mipi.interleave_mode, + pinfo->mipi.sctl_base); + + return ret; +} + +int dsi_cmd_panel_config(struct msm_panel_info *pinfo, + struct lcdc_panel_info *plcdc) +{ + int ret = NO_ERROR; + uint8_t lane_en = 0; + uint8_t ystride = pinfo->bpp / 8; + uint32_t panel_width = pinfo->xres; + struct dsc_desc *dsc = NULL; + uint32_t final_xres, final_yres, final_width; + uint32_t final_height; + + if (pinfo->mipi.dual_dsi) + panel_width = panel_width / 2; + + if (pinfo->mipi.data_lane0) + lane_en |= (1 << 0); + + if (pinfo->mipi.data_lane1) + lane_en |= (1 << 1); + + if (pinfo->mipi.data_lane2) + lane_en |= (1 << 2); + + if (pinfo->mipi.data_lane3) + lane_en |= (1 << 3); + + if (pinfo->compression_mode == COMPRESSION_DSC) { + dsc = &pinfo->dsc; + panel_width = dsc->pclk_per_line; + } + + final_xres = panel_width; + final_width = panel_width + pinfo->lcdc.xres_pad; + final_yres = pinfo->yres; + final_height = pinfo->yres + pinfo->lcdc.yres_pad; + + ret = mdss_dsi_cmd_mode_config(pinfo, final_width, final_height, + final_xres, final_yres, + pinfo->mipi.dst_format, + ystride, lane_en, + pinfo->mipi.interleave_mode, + pinfo->mipi.ctl_base); + + if (pinfo->mipi.dual_dsi) + ret = mdss_dsi_cmd_mode_config(pinfo, final_width, final_height, + final_xres, final_yres, + pinfo->mipi.dst_format, + ystride, lane_en, + pinfo->mipi.interleave_mode, + pinfo->mipi.sctl_base); + + return ret; +} + + +int dsi_panel_config(void *pdata) +{ + struct msm_panel_info *pinfo = (struct msm_panel_info *)pdata; + struct lcdc_panel_info *plcdc = NULL; + int ret = NO_ERROR; + + if (pinfo == NULL) + return ERROR; + + plcdc = &(pinfo->lcdc); + if (plcdc == NULL) + return ERROR; + + + if (pinfo->mipi.mode == DSI_VIDEO_MODE) + ret = dsi_video_panel_config(pinfo, plcdc); + else + ret = dsi_cmd_panel_config(pinfo, plcdc); + + return ret; +} + +int32_t panel_name_to_id(struct panel_list supp_panels[], + uint32_t supp_panels_size, + const char *panel_name) +{ + uint32_t i; + int32_t panel_id = ERROR; + + if (!panel_name) { + printk(BIOS_ERR, "Invalid panel name\n"); + return panel_id; + } + + for (i = 0; i < supp_panels_size; i++) { + if (!strncmp(panel_name, supp_panels[i].name, + MAX_PANEL_ID_LEN)) { + panel_id = supp_panels[i].id; + break; + } + } + + return panel_id; +} + diff --git a/src/soc/qualcomm/sc7180/display/target_sc7180.c b/src/soc/qualcomm/sc7180/display/target_sc7180.c new file mode 100644 index 0000000..e79c4cb --- /dev/null +++ b/src/soc/qualcomm/sc7180/display/target_sc7180.c @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/mmio.h> +#include <lib.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <edid.h> +#include <stdlib.h> +#include <string.h> +#include <soc/display/panel.h> +#include <soc/display/msm_panel.h> +#include <soc/mdss_6_2_0.h> +#include <soc/display/mipi_dsi.h> +#include <soc/display/panel_display.h> +#include <soc/display/target_sc7180.h> +#include <gpio.h> +#include <soc/gpio.h> + +#define STRENGTH_SIZE_IN_BYTES_SDM845 10 +#define REGULATOR_SIZE_IN_BYTES_SDM845 5 +#define LANE_SIZE_IN_BYTES_SDM845 20 + +int target_dsi_phy_config(struct mdss_dsi_phy_ctrl *phy_db) +{ + memcpy(phy_db->strength, panel_strength_ctrl, + STRENGTH_SIZE_IN_BYTES_SDM845 * sizeof(uint32_t)); + memcpy(phy_db->regulator, panel_regulator_settings, + REGULATOR_SIZE_IN_BYTES_SDM845 * sizeof(uint32_t)); + memcpy(phy_db->laneCfg, panel_lane_config, + LANE_SIZE_IN_BYTES_SDM845); + return NO_ERROR; +} + +int target_backlight_ctrl(uint8_t enable) +{ + + if (enable) { + gpio_configure(GPIO(12), GPIO_FUNC_GPIO, GPIO_NO_PULL, + GPIO_2MA, GPIO_OUTPUT_ENABLE); //BackLight enable GPIO + + gpio_set(GPIO(12), 1); + + } else { + gpio_set(GPIO(12), 1); + + } + return NO_ERROR; +} + +int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq, + struct msm_panel_info *pinfo) +{ + return NO_ERROR; + +} + +int target_set_switch_gpio(int enable) +{ + printk(BIOS_INFO, "%s: Turn bridge gpio's on\n", __func__); + if (enable) { + gpio_configure(GPIO(14), GPIO_FUNC_GPIO, GPIO_NO_PULL, + GPIO_2MA, GPIO_OUTPUT_ENABLE); //Bridge Enable GPIO + + gpio_set(GPIO(14), 1); + + gpio_configure(GPIO(106), GPIO_FUNC_GPIO, GPIO_NO_PULL, + GPIO_8MA, GPIO_OUTPUT_ENABLE); //PP3300 EDP power supply + + gpio_set(GPIO(106), 1); + } else { + gpio_set(GPIO(14), 1); + gpio_set(GPIO(106), 1); + } + return NO_ERROR; +} + +int target_display_pre_on(void) +{ + return NO_ERROR; +} + +int target_display_pre_off(void) +{ + return NO_ERROR; +} +int target_display_post_on(void) +{ + return NO_ERROR; +} +int target_display_post_off(void) +{ + return NO_ERROR; +} +int target_display_get_base_offset(uint32_t base) +{ + return 0; +} + diff --git a/src/soc/qualcomm/sc7180/include/soc/display/mipi_dsi.h b/src/soc/qualcomm/sc7180/include/soc/display/mipi_dsi.h new file mode 100644 index 0000000..b3eebf8 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/display/mipi_dsi.h @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _PLATFORM_MSM_SHARED_MIPI_DSI_H_ +#define _PLATFORM_MSM_SHARED_MIPI_DSI_H_ + +#include <soc/display/msm_panel.h> + +#define PASS 0 +#define FAIL 1 +#define DSI_VIDEO_MODE_DONE_MASK BIT(17) +#define DSI_VIDEO_MODE_DONE_AK BIT(16) +#define DSI_VIDEO_MODE_DONE_STAT BIT(16) +/********************************************************** + DSI register configuration options + **********************************************************/ +#define MIPI_DSI_MRPS 0x04 /* Maximum Return Packet Size */ +#define MIPI_DSI_REG_LEN 16 /* 4 x 4 bytes register */ +#define TIMING_FLUSH 0x1E4 +#define TIMING_DB_MODE 0x1E8 +#define DSI_HW_REV_241 0x20040001 /* SDM845 */ +#define RDBK_DATA0 0x06C +#define DSI_VIDEO_DST_FORMAT_RGB565 0 +#define DSI_VIDEO_DST_FORMAT_RGB666 1 +#define DSI_VIDEO_DST_FORMAT_RGB666_LOOSE 2 +#define DSI_VIDEO_DST_FORMAT_RGB888 3 +#define DSI_CMD_DST_FORMAT_RGB111 0 +#define DSI_CMD_DST_FORMAT_RGB332 3 +#define DSI_CMD_DST_FORMAT_RGB444 4 +#define DSI_CMD_DST_FORMAT_RGB565 6 +#define DSI_CMD_DST_FORMAT_RGB666 7 +#define DSI_CMD_DST_FORMAT_RGB888 8 + +struct mipi_dsi_cmd { + uint32_t size; + char *payload; + int wait; +}; + +enum { + DSI_VIDEO_MODE, + DSI_CMD_MODE, +}; + +int mdss_dsi_config(struct msm_fb_panel_data *panel); +int mdss_dsi_video_mode_config(struct msm_panel_info *pinfo, + uint16_t disp_width, + uint16_t disp_height, + uint16_t img_width, + uint16_t img_height, + uint16_t hsync_porch0_fp, + uint16_t hsync_porch0_bp, + uint16_t vsync_porch0_fp, + uint16_t vsync_porch0_bp, + uint16_t hsync_width, + uint16_t vsync_width, + uint16_t dst_format, + uint16_t traffic_mode, + uint8_t lane_en, + uint8_t pulse_mode_hsa_he, + uint32_t low_pwr_stop_mode, + uint8_t eof_bllp_pwr, + uint8_t interleav, + uint32_t ctl_base); + +int mdss_dsi_cmd_mode_config(struct msm_panel_info *pinfo, + uint16_t disp_width, + uint16_t disp_height, + uint16_t img_width, + uint16_t img_height, + uint16_t dst_format, + uint8_t ystride, + uint8_t lane_en, + uint8_t interleav, + uint32_t ctl_base); + +int mdss_dsi_cmds_tx(struct mipi_panel_info *mipi, + struct mipi_dsi_cmd *cmds, int count, char dual_dsi); +int mdss_dsi_cmds_rx(struct mipi_panel_info *mipi, uint32_t **rp, int rp_len, + int rdbk_len); +int mdss_dsi_post_on(struct msm_fb_panel_data *panel); + +#endif + diff --git a/src/soc/qualcomm/sc7180/include/soc/display/panel_display.h b/src/soc/qualcomm/sc7180/include/soc/display/panel_display.h new file mode 100644 index 0000000..a36e31b --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/display/panel_display.h @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _PANEL_DISPLAY_H_ +#define _PANEL_DISPLAY_H_ +/*---------------------------------------------------------------------------*/ +/* MACRO definition */ +/*---------------------------------------------------------------------------*/ +#define BPP_16 16 +#define BPP_18 18 +#define BPP_24 24 +#define TIMING_SIZE 48 +#define REGULATOR_SIZE 28 +#define DUAL_DSI_FLAG 0x1 +#define DUAL_PIPE_FLAG 0x2 +#define PIPE_SWAP_FLAG 0x4 +#define SPLIT_DISPLAY_FLAG 0x8 +#define DST_SPLIT_FLAG 0x10 +#define USE_DSI1_PLL_FLAG 0x20 +#define MAX_PANEL_ID_LEN 64 +#include <soc/display/panel.h> +/*---------------------------------------------------------------------------*/ +/* struct definition */ +/*---------------------------------------------------------------------------*/ +struct panel_struct { + struct panel_config *paneldata; + struct panel_resolution *panelres; + struct color_info *color; + struct videopanel_info *videopanel; + struct commandpanel_info *commandpanel; + struct command_state *state; + struct lane_configuration *laneconfig; + struct panel_timing *paneltiminginfo; + struct panel_reset_sequence *panelresetseq; + struct backlight *backlightinfo; + struct topology_config *config; +}; + +struct panel_list { + char name[MAX_PANEL_ID_LEN]; + uint32_t id; +}; + +/*---------------------------------------------------------------------------*/ +/* API */ +/*---------------------------------------------------------------------------*/ +int dsi_panel_init(struct msm_panel_info *pinfo, + struct panel_struct *pstruct); +int dsi_panel_pre_on(void); +int dsi_panel_post_on(void); +int dsi_panel_pre_off(void); +int dsi_panel_post_off(void); +int dsi_panel_rotation(void); +int dsi_panel_config(void *cfg); +int oem_panel_rotation(void); +int oem_panel_on(void); +int oem_panel_off(void); + +/* OEM support API */ +int32_t panel_name_to_id(struct panel_list supp_panels[], + uint32_t supp_panels_size, const char *panel_name); + +int oem_panel_select(const char *panel_name, struct panel_struct *panelstruct, + struct msm_panel_info *pinfo, struct mdss_dsi_phy_ctrl *phy_db); +#endif + diff --git a/src/soc/qualcomm/sc7180/include/soc/display/target_sc7180.h b/src/soc/qualcomm/sc7180/include/soc/display/target_sc7180.h new file mode 100644 index 0000000..1ca9c1d --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/display/target_sc7180.h @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2020 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _TARGET_DISPLAY_H +#define _TARGET_DISPLAY_H + +#include <soc/display/panel.h> +#include <soc/display/msm_panel.h> + +/*---------------------------------------------------------------------------*/ +/* Target Physical configuration */ +/*---------------------------------------------------------------------------*/ +static const uint32_t panel_strength_ctrl[] = { + 0x55, 0x03, + 0x55, 0x03, + 0x55, 0x03, + 0x55, 0x03, + 0x55, 0x00 +}; + +static const uint32_t panel_regulator_settings[] = { + 0x1d, 0x1d, 0x1d, 0x1d, 0x1d +}; + +static const char panel_lane_config[] = { + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x80, +}; + +static const char panel_bist_ctrl[] = { }; +static const uint32_t panel_physical_ctrl[] = { }; + +/*---------------------------------------------------------------------------*/ +/* Functions */ +/*---------------------------------------------------------------------------*/ +int target_display_pre_on(void); +int target_display_pre_off(void); +int target_display_post_on(void); +int target_display_post_off(void); +int target_display_get_base_offset(uint32_t base); +int target_backlight_ctrl(uint8_t enable); +int target_set_switch_gpio(int enable_dsi2hdmibridge); +int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq, + struct msm_panel_info *pinfo); +int target_dsi_phy_config(struct mdss_dsi_phy_ctrl *phy_db); +#endif + -- To view, visit https://review.coreboot.org/c/coreboot/+/39614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie64354ce8bc2a64b891fb9478fbca38d6ec4c321 Gerrit-Change-Number: 39614 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020