coreboot-gerrit October 2020

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Change in coreboot[master]: arch/x86/acpi_s3.c: Only call APM with CONFIG_HAVE_SMI_HANDLER
by Arthur Heymans (Code Review) 18 May '21

18 May '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46381 ) Change subject: arch/x86/acpi_s3.c: Only call APM with CONFIG_HAVE_SMI_HANDLER ...................................................................... arch/x86/acpi_s3.c: Only call APM with CONFIG_HAVE_SMI_HANDLER Change-Id: If38c53cba7efd39a8894fde956d2f6aa06620e9a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/acpi_s3.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/46381/1 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 2802bd3..e8ef600 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -74,7 +74,8 @@ void __noreturn acpi_resume(void *wake_vec) { /* Restore GNVS pointer in SMM if found. */ - apm_control(APM_CNT_GNVS_UPDATE); + if (CONFIG(HAVE_SMI_HANDLER)) + apm_control(APM_CNT_GNVS_UPDATE); /* Call mainboard resume handler first, if defined. */ mainboard_suspend_resume(); -- To view, visit https://review.coreboot.org/c/coreboot/+/46381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If38c53cba7efd39a8894fde956d2f6aa06620e9a Gerrit-Change-Number: 46381 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/intelp2m/snr: Remove incorrent GPO macro
by Maxim Polyakov (Code Review) 17 May '21

17 May '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44472 ) Change subject: util/intelp2m/snr: Remove incorrent GPO macro ...................................................................... util/intelp2m/snr: Remove incorrent GPO macro GPIO Driver mode is used for configuration interrupt routing for external devices through GPI. But there is no point in configuring this for GPO and according to the changes in the project [1], this patch removes the code to generate PAD_CFG_GPO_GPIO_DRIVER macro. [1] Change-Id: I74c318897647836f4604a937543254f44b470433 Change-Id: Ibe7b787d455b638e70e54fb8b048c8aad8283037 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/intelp2m/platforms/snr/macro.go 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/44472/1 diff --git a/util/intelp2m/platforms/snr/macro.go b/util/intelp2m/platforms/snr/macro.go index 86cc7b7..3340ec0 100644 --- a/util/intelp2m/platforms/snr/macro.go +++ b/util/intelp2m/platforms/snr/macro.go @@ -213,11 +213,6 @@ dw0.CntrMaskFieldsClear(common.RxLevelEdgeConfigurationMask) } macro.Set("PAD_CFG") - if macro.IsOwnershipDriver() { - // PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) - macro.Add("_GPO_GPIO_DRIVER").Add("(").Id().Val().Rstsrc().Pull().Add("),") - return - } if term != 0 { // e.g. PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP), macro.Add("_TERM") -- To view, visit https://review.coreboot.org/c/coreboot/+/44472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe7b787d455b638e70e54fb8b048c8aad8283037 Gerrit-Change-Number: 44472 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/supermicro/x11-lga1151: undo set DRIVER for GPO
by Maxim Polyakov (Code Review) 17 May '21

17 May '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44465 ) Change subject: mb/supermicro/x11-lga1151: undo set DRIVER for GPO ...................................................................... mb/supermicro/x11-lga1151: undo set DRIVER for GPO GPIO Driver mode is used for configuration interrupt routing for external devices through GPI. But there is no point in configuring this for GPO. This patch replaces the PAD_CFG_GPO_GPIO_DRIVER macro with others that do not set the corresponding bit in the Host Software Pad Ownership register. Change-Id: I5aed5769600bb9c442ad13a2efbcf9d5fd8da537 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h 1 file changed, 27 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/44465/1 diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h index f5e71ad..98e2d62 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h @@ -34,8 +34,8 @@ PAD_NC(GPP_A23, NONE), /* GPIO Group GPP_B */ - PAD_CFG_GPO_GPIO_DRIVER(GPP_B0, 1, DEEP, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_B1, 1, DEEP, NONE), + PAD_CFG_GPO(GPP_B0, 1, DEEP), + PAD_CFG_GPO(GPP_B1, 1, DEEP), PAD_NC(GPP_B2, NONE), PAD_NC(GPP_B3, NONE), PAD_NC(GPP_B4, NONE), @@ -45,7 +45,7 @@ PAD_NC(GPP_B8, NONE), PAD_NC(GPP_B9, NONE), PAD_NC(GPP_B10, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_B11, 0, DEEP, NONE), + PAD_CFG_GPO(GPP_B11, 0, DEEP), PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), @@ -54,7 +54,7 @@ PAD_NC(GPP_B17, NONE), PAD_NC(GPP_B18, NONE), PAD_NC(GPP_B19, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_B20, 1, PLTRST, NONE), + PAD_CFG_GPO(GPP_B20, 1, PLTRST), PAD_NC(GPP_B21, NONE), PAD_NC(GPP_B22, NONE), PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), @@ -65,7 +65,7 @@ PAD_NC(GPP_C2, NONE), // PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), - PAD_CFG_GPO_GPIO_DRIVER(GPP_C5, 1, DEEP, NONE), + PAD_CFG_GPO(GPP_C5, 1, DEEP), // PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), PAD_CFG_GPI_INT(GPP_C8, NONE, PLTRST, OFF), @@ -87,10 +87,10 @@ /* GPIO Group GPP_D */ PAD_NC(GPP_D0, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_D1, 1, DEEP, NONE), + PAD_CFG_GPO(GPP_D1, 1, DEEP), PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE), PAD_NC(GPP_D3, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_D4, 0, PLTRST, NONE), + PAD_CFG_GPO(GPP_D4, 0, PLTRST), PAD_NC(GPP_D5, NONE), PAD_NC(GPP_D6, NONE), PAD_NC(GPP_D7, NONE), @@ -104,10 +104,10 @@ PAD_NC(GPP_D15, NONE), PAD_NC(GPP_D16, NONE), PAD_NC(GPP_D17, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_D18, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_D19, 1, PLTRST, NONE), + PAD_CFG_GPO(GPP_D18, 1, PLTRST), + PAD_CFG_GPO(GPP_D19, 1, PLTRST), PAD_NC(GPP_D20, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_D21, 0, DEEP, NONE), + PAD_CFG_GPO(GPP_D21, 0, DEEP), PAD_CFG_GPI_INT(GPP_D22, NONE, RSMRST, OFF), PAD_NC(GPP_D23, NONE), @@ -133,9 +133,9 @@ PAD_NC(GPP_F3, NONE), PAD_NC(GPP_F4, NONE), PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), - PAD_CFG_GPO_GPIO_DRIVER(GPP_F6, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_F7, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_F8, 1, PLTRST, NONE), + PAD_CFG_GPO(GPP_F6, 1, PLTRST), + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + PAD_CFG_GPO(GPP_F8, 1, PLTRST), PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), @@ -150,7 +150,7 @@ PAD_NC(GPP_F20, NONE), PAD_NC(GPP_F21, NONE), PAD_NC(GPP_F22, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_F23, 0, RSMRST, NONE), + PAD_CFG_GPO(GPP_F23, 0, RSMRST), /* GPIO Group GPP_G */ PAD_CFG_GPI_INT(GPP_G0, NONE, DEEP, OFF), @@ -179,16 +179,16 @@ PAD_NC(GPP_G23, NONE), /* GPIO Group GPP_H */ - PAD_CFG_GPO_GPIO_DRIVER(GPP_H0, 1, DEEP, NONE), + PAD_CFG_GPO(GPP_H0, 1, DEEP), PAD_CFG_GPI_INT(GPP_H1, NONE, PLTRST, OFF), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H2, 1, DEEP, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H3, 1, DEEP, NONE), + PAD_CFG_GPO(GPP_H2, 1, DEEP), + PAD_CFG_GPO(GPP_H3, 1, DEEP), PAD_CFG_GPI_INT(GPP_H4, NONE, PLTRST, OFF), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H5, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H6, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H7, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H8, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H9, 1, PLTRST, NONE), + PAD_CFG_GPO(GPP_H5, 1, PLTRST), + PAD_CFG_GPO(GPP_H6, 1, PLTRST), + PAD_CFG_GPO(GPP_H7, 1, PLTRST), + PAD_CFG_GPO(GPP_H8, 1, PLTRST), + PAD_CFG_GPO(GPP_H9, 1, PLTRST), PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), PAD_NC(GPP_H12, NONE), @@ -198,11 +198,11 @@ PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), PAD_NC(GPP_H18, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H19, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H20, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H21, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H22, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H23, 1, PLTRST, NONE), + PAD_CFG_GPO(GPP_H19, 1, PLTRST), + PAD_CFG_GPO(GPP_H20, 1, PLTRST), + PAD_CFG_GPO(GPP_H21, 1, PLTRST), + PAD_CFG_GPO(GPP_H22, 1, PLTRST), + PAD_CFG_GPO(GPP_H23, 1, PLTRST), /* GPIO Group GPP_I */ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), -- To view, visit https://review.coreboot.org/c/coreboot/+/44465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5aed5769600bb9c442ad13a2efbcf9d5fd8da537 Gerrit-Change-Number: 44465 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/glkrvp: Undo set DRIVER for GPO
by Maxim Polyakov (Code Review) 17 May '21

17 May '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44466 ) Change subject: mb/intel/glkrvp: Undo set DRIVER for GPO ...................................................................... mb/intel/glkrvp: Undo set DRIVER for GPO GPIO Driver mode is used for configuration interrupt routing for external devices through GPI. But there is no point in configuring this for GPO. This patch replaces the PAD_CFG_GPO_GPIO_DRIVER macro with others that do not set the corresponding bit in the Host Software Pad Ownership register. Change-Id: Iac7d674e79e0caee467fc087e6d36192e84a12d8 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/44466/1 diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c index 56df526..d70a064 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c @@ -35,7 +35,7 @@ PAD_CFG_NF(GPIO_21, UP_20K, DEEP, NF2), /* CNV_MFUART2_RXD */ PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), /* CNV_MFUART2_TXD */ PAD_CFG_NF(GPIO_23, UP_20K, DEEP, NF2), /* CNV_GNSS_PABLANKIt */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_24, 1, DEEP, DN_20K), + PAD_CFG_TERM_GPO(GPIO_24, 1, DN_20K, DEEP), PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_25, 1, DEEP, UP_20K, TxLASTRxE, SAME),/*WWAN /RF_KILL_GPS*/ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_26, UP_20K, DEEP, NF2, HIZCRx1, DISPUPD),/* NFC Interrupt */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_27, 1, DEEP, NONE, IGNORE, DISPUPD),/* RF_KILL_WiFi/WiFi_Disable */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac7d674e79e0caee467fc087e6d36192e84a12d8 Gerrit-Change-Number: 44466 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/fizz/endeavour/gpio: Undo set DRIVER for GPO
by Maxim Polyakov (Code Review) 17 May '21

17 May '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44467 ) Change subject: mb/google/fizz/endeavour/gpio: Undo set DRIVER for GPO ...................................................................... mb/google/fizz/endeavour/gpio: Undo set DRIVER for GPO GPIO Driver mode is used for configuration interrupt routing for external devices through GPI. But there is no point in configuring this for GPO. This patch replaces the PAD_CFG_GPO_GPIO_DRIVER macro with others that do not set the corresponding bit in the Host Software Pad Ownership register. Change-Id: Icbbc644adda0dde768171e9581ae345cb9750eea Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/google/fizz/variants/endeavour/gpio.c 1 file changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/44467/1 diff --git a/src/mainboard/google/fizz/variants/endeavour/gpio.c b/src/mainboard/google/fizz/variants/endeavour/gpio.c index 432a180..716be3f 100644 --- a/src/mainboard/google/fizz/variants/endeavour/gpio.c +++ b/src/mainboard/google/fizz/variants/endeavour/gpio.c @@ -28,9 +28,9 @@ /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* ISH_GP0 */ PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, LEVEL), /* 7322_INTO */ -/* ISH_GP1 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_A19, 1, DEEP, NONE), /* 7322_OE */ +/* ISH_GP1 */ PAD_CFG_GPO(GPP_A19, 1, DEEP), /* 7322_OE */ /* ISH_GP2 */ PAD_CFG_GPI_INT(GPP_A20, NONE, PLTRST, LEVEL), /* 7322_INTO */ -/* ISH_GP3 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_A21, 1, DEEP, NONE), /* 7322_OE */ +/* ISH_GP3 */ PAD_CFG_GPO(GPP_A21, 1, DEEP), /* 7322_OE */ /* ISH_GP4 */ PAD_CFG_NC(GPP_A22), /* ISH_GP5 */ PAD_CFG_NC(GPP_A23), @@ -134,13 +134,11 @@ /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* MB_PCIE_SATA#_DET */ /* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), -/* CPU_GP0 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 0, DEEP, - NONE), /* TPU_RST_PIN40 */ +/* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 0, DEEP), /* TPU_RST_PIN40 */ /* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* TP103 */ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ /* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */ -/* CPU_GP1 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_E7, 0, DEEP, - NONE), /* TPU_RST_PIN42 */ +/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 0, DEEP), /* TPU_RST_PIN42 */ /* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP96 */ /* USB2_OCO# */ PAD_CFG_NC(GPP_E9), /* T1037 */ /* USB2_OC1# */ PAD_CFG_NC(GPP_E10), /* T1025 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbbc644adda0dde768171e9581ae345cb9750eea Gerrit-Change-Number: 44467 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/cedarisland/gpio: use macros for bidirectional pads
by Maxim Polyakov (Code Review) 17 May '21

17 May '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43456 ) Change subject: mb/intel/cedarisland/gpio: use macros for bidirectional pads ...................................................................... mb/intel/cedarisland/gpio: use macros for bidirectional pads The configuration contains pads in which both buffers (Tx/Rx) [1] are enabled. Therefore, they are bidirectional. Use the new macros instead PAD_CFG_GPIO_BIDIRECT() [2] of common _PAD_CFG_STRUCT() to configure these pads. [1] Intel document #549921 [2] https://review.coreboot.org/c/coreboot/+/42914 Change-Id: I32a10ead1d965811f6e644124ba84ceb2264ddc4 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/intel/cedarisland_crb/include/gpio.h 1 file changed, 10 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/43456/1 diff --git a/src/mainboard/intel/cedarisland_crb/include/gpio.h b/src/mainboard/intel/cedarisland_crb/include/gpio.h index cd15fed..2a5fb11 100644 --- a/src/mainboard/intel/cedarisland_crb/include/gpio.h +++ b/src/mainboard/intel/cedarisland_crb/include/gpio.h @@ -173,10 +173,7 @@ /* GPP_C9 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, RSMRST, OFF, DRIVER), /* GPP_C10 - GPIO */ - _PAD_CFG_STRUCT(GPP_C10, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_C10, 0, NONE, RSMRST, OFF, ACPI), /* GPP_C11 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, RSMRST, OFF, ACPI), /* GPP_C12 - GPIO */ @@ -318,10 +315,7 @@ /* GPP_I3 - LAN_TDI */ PAD_CFG_NF(GPP_I3, NONE, RSMRST, NF2), /* GPP_I4 - GPIO */ - _PAD_CFG_STRUCT(GPP_I4, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_I4, 0, NONE, RSMRST, OFF, ACPI), /* GPP_I5 - GPIO */ PAD_CFG_GPO(GPP_I5, 0, RSMRST), /* GPP_I6 - GPIO */ @@ -364,17 +358,11 @@ /* GPP_J12 - GPIO */ PAD_CFG_GPO(GPP_J12, 0, RSMRST), /* GPP_J13 - GPIO */ - _PAD_CFG_STRUCT(GPP_J13, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_J13, 0, NONE, RSMRST, OFF, ACPI), /* GPP_J14 - GPIO */ PAD_CFG_GPO(GPP_J14, 0, RSMRST), /* GPP_J15 - GPIO */ - _PAD_CFG_STRUCT(GPP_J15, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_J15, 0, NONE, RSMRST, OFF, ACPI), /* GPP_J16 - GPIO */ PAD_CFG_GPO(GPP_J16, 0, RSMRST), /* GPP_J17 - GPIO */ @@ -468,42 +456,24 @@ /* ------- GPIO Group GPP_H ------- */ /* GPP_H0 - GPIO */ - _PAD_CFG_STRUCT(GPP_H0, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_H0, 0, NONE, RSMRST, OFF, ACPI), /* GPP_H1 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, RSMRST, OFF, ACPI), /* GPP_H2 - GPIO */ - _PAD_CFG_STRUCT(GPP_H2, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_H2, 0, NONE, RSMRST, OFF, ACPI), /* GPP_H3 - GPIO */ - _PAD_CFG_STRUCT(GPP_H3, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_H3, 0, NONE, RSMRST, OFF, ACPI), /* GPP_H4 - GPIO */ - _PAD_CFG_STRUCT(GPP_H4, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_H4, 0, NONE, RSMRST, OFF, ACPI), /* GPP_H5 - RESERVED */ /* GPP_H6 - SRCCLKREQ12# */ PAD_CFG_NF(GPP_H6, NONE, RSMRST, NF1), /* GPP_H7 - GPIO */ - _PAD_CFG_STRUCT(GPP_H7, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_H7, 0, NONE, RSMRST, OFF, ACPI), /* GPP_H8 - SRCCLKREQ14# */ PAD_CFG_NF(GPP_H8, NONE, RSMRST, NF1), /* GPP_H9 - GPIO */ - _PAD_CFG_STRUCT(GPP_H9, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_H9, 0, NONE, RSMRST, OFF, ACPI), /* GPP_H10 - RESERVED */ /* GPP_H11 - RESERVED */ /* GPP_H12 - GPIO */ -- To view, visit https://review.coreboot.org/c/coreboot/+/43456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32a10ead1d965811f6e644124ba84ceb2264ddc4 Gerrit-Change-Number: 43456 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/{apl,glk}: add options to configure GPU
by Maxim Polyakov (Code Review) 17 May '21

17 May '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39764 ) Change subject: soc/intel/{apl,glk}: add options to configure GPU ...................................................................... soc/intel/{apl,glk}: add options to configure GPU Adds options to select the primary GPU device and configure IGD, which allows to override the appropriate FSP options in the SoC code. These changes do not affect the configuration of the boards with the Apollo Lake and Gemini Lake processors, because if these parameters are not defined in the devicetree, they will be set to the default values. Change-Id: I6e8013980259aadeb3a1fd504d31062ccb5ef7af Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/romstage.c 2 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/39764/1 diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index c7fa3e7..8bea454 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -48,6 +48,39 @@ /* Common structure containing soc config data required by common code*/ struct soc_intel_common_config common_soc_config; + /* Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size */ + enum { + DVMT_64MB = 2, /* Default */ + DVMT_96MB, + DVMT_128MB, + DVMT_160MB, + DVMT_192MB, + DVMT_224MB, + DVMT_256MB, + DVMT_288MB, + DVMT_320MB, + DVMT_352MB, + DVMT_384MB, + DVMT_416MB, + DVMT_448MB, + DVMT_480MB, + DVMT_512MB, + } igd_dvmt_50_pre_alloc_size; + + /* Select the Aperture Size for GPU device */ + enum { + APERTURE_128MB = 1, /* Default */ + APERTURE_256MB, + APERTURE_512MB, + } igd_aperture_size; + + /* Select the GTT Size for GPU device */ + enum { + GTT_2MB = 1, + GTT_4MB, + GTT_8MB, /* Default */ + } igd_gtt_size; + /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has * four CLKREQ inputs, but six root ports. Root ports without an diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 2efb520..5872e7a 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -264,10 +264,23 @@ static void soc_gpu_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + const struct soc_intel_apollolake_config *soc_cfg = config_of_soc(); const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); if (dev && dev->enabled && CONFIG(ONBOARD_VGA_IS_PRIMARY) { m_cfg->PrimaryVideoAdaptor = PRIMARY_IGD; + /* + * Override FSP settings for IGD only if they are set in the devicetree. + * Otherwise, the default values from UPD will be used for them + */ + if (soc_cfg->igd_dvmt_50_pre_alloc_size) + m_cfg->IgdDvmt50PreAlloc = soc_cfg->igd_dvmt_50_pre_alloc_size; + + if (soc_cfg->igd_aperture_size) + m_cfg->IgdApertureSize = soc_cfg->igd_aperture_size; + + if (soc_cfg->igd_gtt_size) + m_cfg->GttSize = soc_cfg->igd_gtt_size; } else { m_cfg->PrimaryVideoAdaptor = PRIMARY_PCI; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e8013980259aadeb3a1fd504d31062ccb5ef7af Gerrit-Change-Number: 39764 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/intel/skylake: Add ucode for SKL/CLX SP
by Maxim Polyakov (Code Review) 17 May '21

17 May '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35761 ) Change subject: src/soc/intel/skylake: Add ucode for SKL/CLX SP ...................................................................... src/soc/intel/skylake: Add ucode for SKL/CLX SP Adds ucode for Family 6 Model 85 Stepping 4,7 CPUs. Corresponds to the latest changes in the intel repository: github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/commit/5ada2f3 Change-Id: I2c63d9944b2b74ffdf7e2753d0a826ce8c1fedec Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/skylake/Makefile.inc 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/35761/1 diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index ef741f8..b86ee88 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -83,7 +83,12 @@ postcar-y += i2c.c postcar-y += uart.c -ifeq ($(CONFIG_SKYLAKE_SOC_PCH_H),y) +ifeq ($(WELISBURG_SOC_PCH_H),y) +# Cascade Lake B1 +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-55-07 +# Skylake H0, M0, U0 && Skylake D M1 +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-55-04 +else ifeq ($(CONFIG_SKYLAKE_SOC_PCH_H),y) # Skylake H Q0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-5e-03 # Kabylake H B0 S0 -- To view, visit https://review.coreboot.org/c/coreboot/+/35761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c63d9944b2b74ffdf7e2753d0a826ce8c1fedec Gerrit-Change-Number: 35761 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Add Cascade Lake SP support
by Maxim Polyakov (Code Review) 17 May '21

17 May '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35126 ) Change subject: soc/intel: Add Cascade Lake SP support ...................................................................... soc/intel: Add Cascade Lake SP support Adds Xeon Cascade Lake processor CPUIDs and Sky Lake-E DMI3 Host Bridge PCI Id Change-Id: If351d554db62c51849ff6c7bb49074e587f14e6d Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/skylake/bootblock/report_platform.c 5 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/35126/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index ac70d8c..2727a6f 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3176,6 +3176,7 @@ #define PCI_DEVICE_ID_INTEL_KBL_ID_S 0x590f #define PCI_DEVICE_ID_INTEL_SKL_ID_H_EM 0x1918 #define PCI_DEVICE_ID_INTEL_SKL_ID_DT 0x191f +#define PCI_DEVICE_ID_INTEL_SKL_ID_E 0x2020 #define PCI_DEVICE_ID_INTEL_KBL_ID_U 0x5904 #define PCI_DEVICE_ID_INTEL_KBL_ID_Y 0x590c #define PCI_DEVICE_ID_INTEL_KBL_ID_H 0x5910 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index e0cee17..6a6ae17 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -56,11 +56,15 @@ { X86_VENDOR_INTEL, CPUID_SKYLAKE_D0 }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_HQ0 }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_HR0 }, + { X86_VENDOR_INTEL, CPUID_SKYLAKE_HMU0 }, { X86_VENDOR_INTEL, CPUID_KABYLAKE_G0 }, { X86_VENDOR_INTEL, CPUID_KABYLAKE_H0 }, { X86_VENDOR_INTEL, CPUID_KABYLAKE_Y0 }, { X86_VENDOR_INTEL, CPUID_KABYLAKE_HA0 }, { X86_VENDOR_INTEL, CPUID_KABYLAKE_HB0 }, + { X86_VENDOR_INTEL, CPUID_CASCADELAKE_A0 }, + { X86_VENDOR_INTEL, CPUID_CASCADELAKE_BLR0 }, + { X86_VENDOR_INTEL, CPUID_CASCADELAKE_BLR1 }, { X86_VENDOR_INTEL, CPUID_CANNONLAKE_A0 }, { X86_VENDOR_INTEL, CPUID_CANNONLAKE_B0 }, { X86_VENDOR_INTEL, CPUID_CANNONLAKE_C0 }, diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index 5ef7641..cf04659 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -21,6 +21,10 @@ /* Supported CPUIDs for different SOCs */ #define CPUID_SKYLAKE_C0 0x406e2 #define CPUID_SKYLAKE_D0 0x406e3 +#define CPUID_SKYLAKE_HMU0 0x50654 +#define CPUID_CASCADELAKE_A0 0x50655 +#define CPUID_CASCADELAKE_BLR0 0x50656 +#define CPUID_CASCADELAKE_BLR1 0x50657 #define CPUID_SKYLAKE_HQ0 0x506e1 #define CPUID_SKYLAKE_HR0 0x506e3 #define CPUID_KABYLAKE_G0 0x406e8 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index b7964e6..30ff7c9 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -349,6 +349,7 @@ PCI_DEVICE_ID_INTEL_KBL_ID_S, PCI_DEVICE_ID_INTEL_SKL_ID_H_EM, PCI_DEVICE_ID_INTEL_SKL_ID_DT, + PCI_DEVICE_ID_INTEL_SKL_ID_E, PCI_DEVICE_ID_INTEL_KBL_ID_U, PCI_DEVICE_ID_INTEL_KBL_ID_Y, PCI_DEVICE_ID_INTEL_KBL_ID_H, diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 279273f..f717678 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -41,6 +41,10 @@ { CPUID_KABYLAKE_Y0, "Kabylake Y0" }, { CPUID_KABYLAKE_HA0, "Kabylake H A0" }, { CPUID_KABYLAKE_HB0, "Kabylake H B0" }, + { CPUID_SKYLAKE_HMU0, "Skylake H0/M0/U0" }, + { CPUID_CASCADELAKE_A0, "Cascade Lake A0" }, + { CPUID_CASCADELAKE_BLR0, "Cascade Lake B0/L0/R0" }, + { CPUID_CASCADELAKE_BLR1, "Cascade Lake B1/L1/R1" }, }; static struct { @@ -56,6 +60,7 @@ { PCI_DEVICE_ID_INTEL_SKL_ID_H_2, "Skylake-H (2 Core)" }, { PCI_DEVICE_ID_INTEL_SKL_ID_S_2, "Skylake-S (2 Core)" }, { PCI_DEVICE_ID_INTEL_SKL_ID_S_4, "Skylake-S (4 Core)" }, + { PCI_DEVICE_ID_INTEL_SKL_ID_E, "Sky Lake-E" }, { PCI_DEVICE_ID_INTEL_KBL_ID_U, "Kabylake-U" }, { PCI_DEVICE_ID_INTEL_KBL_U_R, "Kabylake-R ULT"}, { PCI_DEVICE_ID_INTEL_KBL_ID_Y, "Kabylake-Y" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/35126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If351d554db62c51849ff6c7bb49074e587f14e6d Gerrit-Change-Number: 35126 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/ifdtool: Identify chipset without platform name
by Subrata Banik (Code Review) 14 May '21

14 May '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44815 ) Change subject: util/ifdtool: Identify chipset without platform name ...................................................................... util/ifdtool: Identify chipset without platform name Able to uniquely identify the chipset without specifying the platform specific quirks (adl/cnl/icl/jsl/tgl etc.). BUG=b:153888802 TEST=Able to dump FD contains correctly without specifying platform quirks on Hatch Platform. > ifdtool -d coreboot.rom Without this CL : ICH Revision: 100 series Sunrise Point With this CL : ICH Revision: 300 series Cannon Point/ 400 series Ice Point Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I83763adb721e069343b19a10e503975ffa6abb24 --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h 2 files changed, 42 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/44815/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index e096864..1880900 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -59,6 +59,7 @@ "ICH8", "ICH9", "ICH10", + "Unknown PCH", "5 series Ibex Peak", "6 series Cougar Point", "7 series Panther Point", @@ -68,7 +69,10 @@ "8 series Wellsburg", "9 series Wildcat Point", "9 series Wildcat Point LP", - "100 series Sunrise Point", + "Gemini Lake: N5xxx, J5xxx, N4xxx, J4xxx", + "100/200 series Sunrise Point", + "300 series Cannon Point/ 400 series Ice Point", + "500 series Tiger Point", "C620 series Lewisburg", NULL }; @@ -161,14 +165,42 @@ return PTR_IN_RANGE(fmsba, image, size) ? fmsba : NULL; } +static enum ich_chipset guess_ifd_2_chipset(const fpsba_t *fpsba) +{ + uint32_t pchstrp_22 = fpsba->pchstrp[22]; + uint32_t pchstrp_23 = fpsba->pchstrp[23]; + + /* Offset 0x5B is the last PCH descriptor record */ + if (pchstrp_23 == 0xFFFFFFFF) + return CHIPSET_N_J_SERIES; + + /* Offset 0x58 is PCH descriptor record is reserved */ + if (pchstrp_22 == 0x0) + return CHIPSET_300_400_SERIES_CANNON_ICE_POINT; + + /* Offset 0x58 bit [2:0] is reserved 0x4 and 0x5a bit [7:0] is reserved 0x58 */ + if (((pchstrp_22 & 0x07) == 0x4) && + ((pchstrp_22 & 0xFF0000) >> 16 == 0x58)) + return CHIPSET_500_SERIES_TIGER_POINT; + + return CHIPSET_PCH_UNKNOWN; +} + /* port from flashrom */ -static enum ich_chipset guess_ich_chipset(const fdbar_t *fdb) +static enum ich_chipset guess_ich_chipset(const fdbar_t *fdb, const fpsba_t *fpsba) { uint32_t iccriba = (fdb->flmap2 >> 16) & 0xff; uint32_t msl = (fdb->flmap2 >> 8) & 0xff; uint32_t isl = (fdb->flmap1 >> 24); uint32_t nm = (fdb->flmap1 >> 8) & 0x7; + int temp_chipset; + /* Check for IFD2 chipset type */ + temp_chipset = guess_ifd_2_chipset(fpsba); + if (temp_chipset != CHIPSET_PCH_UNKNOWN) + return temp_chipset; + + /* Rest for IFD1 chipset type */ if (iccriba == 0x00) { if (msl == 0 && isl <= 2) return CHIPSET_ICH8; @@ -192,7 +224,7 @@ } else if (nm == 6) { return CHIPSET_C620_SERIES_LEWISBURG; } else { - return CHIPSET_100_SERIES_SUNRISE_POINT; + return CHIPSET_100_200_SERIES_SUNRISE_POINT; } } @@ -232,10 +264,11 @@ int read_freq; const fcba_t *fcba = find_fcba(image, size); const fdbar_t *fdb = find_fd(image, size); + const fpsba_t *fpsba = find_fpsba(image, size); if (!fcba || !fdb) exit(EXIT_FAILURE); - chipset = guess_ich_chipset(fdb); + chipset = guess_ich_chipset(fdb, fpsba); /* TODO: port ifd_version and max_regions * against guess_ich_chipset() */ diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index 840d7fe..a113d29 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -23,6 +23,7 @@ CHIPSET_ICH8, CHIPSET_ICH9, CHIPSET_ICH10, + CHIPSET_PCH_UNKNOWN, CHIPSET_5_SERIES_IBEX_PEAK, CHIPSET_6_SERIES_COUGAR_POINT, CHIPSET_7_SERIES_PANTHER_POINT, @@ -34,9 +35,10 @@ CHIPSET_8_SERIES_WELLSBURG, CHIPSET_9_SERIES_WILDCAT_POINT, CHIPSET_9_SERIES_WILDCAT_POINT_LP, - CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) - * variants - */ + CHIPSET_N_J_SERIES, /* Gemini Lake: N5xxx, J5xxx, N4xxx, J4xxx */ + CHIPSET_100_200_SERIES_SUNRISE_POINT, /* 6th-7th gen Core i/o (LP) variants */ + CHIPSET_300_400_SERIES_CANNON_ICE_POINT, /* 8th-10th gen Core i/o (LP) variants */ + CHIPSET_500_SERIES_TIGER_POINT, /* 11th gen Core i/o (LP) variants onwards */ CHIPSET_C620_SERIES_LEWISBURG, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/44815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83763adb721e069343b19a10e503975ffa6abb24 Gerrit-Change-Number: 44815 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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