coreboot-gerrit October 2020

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Change in coreboot[master]: volteer: Create trondo variant
by David Wu (Code Review) 13 May '21

13 May '21

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40686 ) Change subject: volteer: Create trondo variant ...................................................................... volteer: Create trondo variant Create the trondo variant of the volteer reference board by copying the template files to a new directory named for the variant. BUG=b:154678884 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_TRONDO Change-Id: Ie4f9bfe4798e14f91c6cb439f5c5ab2b9ea52b51 --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/trondo/Makefile.inc A src/mainboard/google/volteer/variants/trondo/gpio.c A src/mainboard/google/volteer/variants/trondo/include/variant/ec.h A src/mainboard/google/volteer/variants/trondo/include/variant/gpio.h A src/mainboard/google/volteer/variants/trondo/overridetree.cb 7 files changed, 75 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/40686/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 0870c61..51ad460 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -58,6 +58,7 @@ default "Halvor" if BOARD_GOOGLE_HALVOR default "Malefor" if BOARD_GOOGLE_MALEFOR default "Ripto" if BOARD_GOOGLE_RIPTO + default "Trondo" if BOARD_GOOGLE_TRONDO default "Volteer" if BOARD_GOOGLE_VOLTEER config MAX_CPUS @@ -73,6 +74,7 @@ default "halvor" if BOARD_GOOGLE_HALVOR default "malefor" if BOARD_GOOGLE_MALEFOR default "ripto" if BOARD_GOOGLE_RIPTO + default "trondo" if BOARD_GOOGLE_TRONDO default "volteer" if BOARD_GOOGLE_VOLTEER endif # BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 62aabb1..41ba332 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -12,6 +12,10 @@ bool "-> Ripto" select BOARD_GOOGLE_BASEBOARD_VOLTEER +config BOARD_GOOGLE_TRONDO + bool "-> Trondo" + select BOARD_GOOGLE_BASEBOARD_VOLTEER + config BOARD_GOOGLE_VOLTEER bool "-> Volteer" select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/trondo/Makefile.inc b/src/mainboard/google/volteer/variants/trondo/Makefile.inc new file mode 100644 index 0000000..a115fcc --- /dev/null +++ b/src/mainboard/google/volteer/variants/trondo/Makefile.inc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. + +SPD_SOURCES = + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/trondo/gpio.c b/src/mainboard/google/volteer/variants/trondo/gpio.c new file mode 100644 index 0000000..6c4fb52 --- /dev/null +++ b/src/mainboard/google/volteer/variants/trondo/gpio.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + +}; + +const struct pad_config *variant_base_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/google/volteer/variants/trondo/include/variant/ec.h b/src/mainboard/google/volteer/variants/trondo/include/variant/ec.h new file mode 100644 index 0000000..33e7971 --- /dev/null +++ b/src/mainboard/google/volteer/variants/trondo/include/variant/ec.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/volteer/variants/trondo/include/variant/gpio.h b/src/mainboard/google/volteer/variants/trondo/include/variant/gpio.h new file mode 100644 index 0000000..55725ad --- /dev/null +++ b/src/mainboard/google/volteer/variants/trondo/include/variant/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Copied from baseboard and may need to change for the new variant. */ + +#endif diff --git a/src/mainboard/google/volteer/variants/trondo/overridetree.cb b/src/mainboard/google/volteer/variants/trondo/overridetree.cb new file mode 100644 index 0000000..75422d8 --- /dev/null +++ b/src/mainboard/google/volteer/variants/trondo/overridetree.cb @@ -0,0 +1,4 @@ +chip soc/intel/tigerlake + device domain 0 on + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/40686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4f9bfe4798e14f91c6cb439f5c5ab2b9ea52b51 Gerrit-Change-Number: 40686 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

7 13

Change in coreboot[master]: mb/purism/librem_whl: Add libgfxinit support
by Angel Pons (Code Review) 13 May '21

13 May '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46627 ) Change subject: mb/purism/librem_whl: Add libgfxinit support ...................................................................... mb/purism/librem_whl: Add libgfxinit support Only the DisplayPort output is working as of now. The HDMI 2.0 output is provided by a Parade DP175 LSPCON, which is internally connected to DP2. LSPCON setup in libgfxinit is missing as of now, but will be added soon. Change-Id: I0da26fef304583eec0375eee2082a9d2ebe27292 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/purism/librem_whl/Kconfig M src/mainboard/purism/librem_whl/Makefile.inc A src/mainboard/purism/librem_whl/gma-mainboard.ads 3 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/46627/1 diff --git a/src/mainboard/purism/librem_whl/Kconfig b/src/mainboard/purism/librem_whl/Kconfig index bc25fb5..ea79d90 100644 --- a/src/mainboard/purism/librem_whl/Kconfig +++ b/src/mainboard/purism/librem_whl/Kconfig @@ -6,6 +6,7 @@ select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT select NO_UART_ON_SUPERIO select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HDA_VERB diff --git a/src/mainboard/purism/librem_whl/Makefile.inc b/src/mainboard/purism/librem_whl/Makefile.inc index ba157df..0725df5 100644 --- a/src/mainboard/purism/librem_whl/Makefile.inc +++ b/src/mainboard/purism/librem_whl/Makefile.inc @@ -4,4 +4,6 @@ ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-y += ramstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/purism/librem_whl/gma-mainboard.ads b/src/mainboard/purism/librem_whl/gma-mainboard.ads new file mode 100644 index 0000000..5494485 --- /dev/null +++ b/src/mainboard/purism/librem_whl/gma-mainboard.ads @@ -0,0 +1,16 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- DisplayPort connector + DP2, -- HDMI connector through Parade DP175 LSPCON + others => Disabled); + +end GMA.Mainboard; -- To view, visit https://review.coreboot.org/c/coreboot/+/46627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0da26fef304583eec0375eee2082a9d2ebe27292 Gerrit-Change-Number: 46627 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

5 16

Change in coreboot[master]: mb/ocp/deltalake: Set coreboot log level via VPD variable
by Johnny Lin (Code Review) 12 May '21

12 May '21

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45134 ) Change subject: mb/ocp/deltalake: Set coreboot log level via VPD variable ...................................................................... mb/ocp/deltalake: Set coreboot log level via VPD variable If the VPD variable 'coreboot_log_level' is not found, will set to COREBOOT_LOG_LEVEL_DEFAULT. Tested=On OCP Delta Lake, coreboot log level can be changed via VPD. Change-Id: I278e392bed178df7a8cdb90685963c1fedf0bcc4 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/ocp/deltalake/Makefile.inc A src/mainboard/ocp/deltalake/loglevel.c M src/mainboard/ocp/deltalake/vpd.h 4 files changed, 31 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/45134/1 diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index b229c94..9d8f5d8 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -3,6 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_65536 + select CONSOLE_OVERRIDE_LOGLEVEL select FSP_CAR select HAVE_ACPI_TABLES select MAINBOARD_USES_FSP2_0 diff --git a/src/mainboard/ocp/deltalake/Makefile.inc b/src/mainboard/ocp/deltalake/Makefile.inc index be6af24..262d6c0 100644 --- a/src/mainboard/ocp/deltalake/Makefile.inc +++ b/src/mainboard/ocp/deltalake/Makefile.inc @@ -1,11 +1,14 @@ ## SPDX-License-Identifier: GPL-2.0-or-later bootblock-y += bootblock.c - +bootblock-$(CONFIG_CONSOLE_OVERRIDE_LOGLEVEL) += loglevel.c +postcar-$(CONFIG_CONSOLE_OVERRIDE_LOGLEVEL) += loglevel.c romstage-y += romstage.c +romstage-$(CONFIG_CONSOLE_OVERRIDE_LOGLEVEL) += loglevel.c romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi.c ramstage-y += ramstage.c ipmi.c +ramstage-$(CONFIG_CONSOLE_OVERRIDE_LOGLEVEL) += loglevel.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/ocp/deltalake/loglevel.c b/src/mainboard/ocp/deltalake/loglevel.c new file mode 100644 index 0000000..fb00f8d --- /dev/null +++ b/src/mainboard/ocp/deltalake/loglevel.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <drivers/vpd/vpd.h> +#include <string.h> + +#include "vpd.h" + +int get_console_loglevel(void) +{ + uint8_t val; + char val_str[VPD_LEN]; + + if (vpd_gets(COREBOOT_LOG_LEVEL, val_str, VPD_LEN, VPD_RW_THEN_RO)) { + val = (uint8_t)atol(val_str); + if (val > 8) + return COREBOOT_LOG_LEVEL_DEFAULT; + return val; + } else { + return COREBOOT_LOG_LEVEL_DEFAULT; + } +} diff --git a/src/mainboard/ocp/deltalake/vpd.h b/src/mainboard/ocp/deltalake/vpd.h index ae2099d..43070c2 100644 --- a/src/mainboard/ocp/deltalake/vpd.h +++ b/src/mainboard/ocp/deltalake/vpd.h @@ -32,4 +32,8 @@ #define FSP_DCI "fsp_dci_enable" /* 1 or 0: enable or disable DCI */ #define FSP_DCI_DEFAULT 0 /* Default value when the VPD variable is not found */ +/* coreboot log level */ +#define COREBOOT_LOG_LEVEL "coreboot_log_level" +#define COREBOOT_LOG_LEVEL_DEFAULT 4 + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I278e392bed178df7a8cdb90685963c1fedf0bcc4 Gerrit-Change-Number: 45134 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

8 42

Change in coreboot[master]: mb/ocp/deltalake: Configure IIO PCIe ports via FSP
by Johnny Lin (Code Review) 12 May '21

12 May '21

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42096 ) Change subject: mb/ocp/deltalake: Configure IIO PCIe ports via FSP ...................................................................... mb/ocp/deltalake: Configure IIO PCIe ports via FSP Change-Id: I7cff6d71588f91c3210cbaa17484644d5b89cc62 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/cpxsp_dl_iio.h M src/mainboard/ocp/deltalake/romstage.c M src/soc/intel/xeon_sp/cpx/acpi.c M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h 5 files changed, 271 insertions(+), 80 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/42096/1 diff --git a/src/mainboard/ocp/deltalake/cpxsp_dl_iio.h b/src/mainboard/ocp/deltalake/cpxsp_dl_iio.h index b7f8c85..b9535ff 100644 --- a/src/mainboard/ocp/deltalake/cpxsp_dl_iio.h +++ b/src/mainboard/ocp/deltalake/cpxsp_dl_iio.h @@ -5,69 +5,82 @@ #include <FspmUpd.h> #include <soc/pci_devs.h> +#include <hob_iiouds.h> -#if 0 /* * DeltaLake Iio PCIe Port Table */ -static const UPD_PCI_PORT_CONFIG dl_iio_pci_port = { - // PortIndex | HidePort | DeEmphasis | PortLinkSpeed | MaxPayload | - // DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbPpd | - // NtbSplitBar | NtbBarSizePBar23 | NtbBarSizePBar4 | NtbBarSizePBar5 | - // NtbBarSizePBar45 | NtbBarSizeSBar23 | NtbBarSizeSBar4 | NtbBarSizeSbar5 | - // NtbBarSizeSBar45 | NtbSBar01Prefetch | NtbXlinkCtlOverride -/* - { PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_1B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_1C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_1D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2D, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3A, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_4A, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_4B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_4C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_4D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, -*/ +static const UPD_IIO_PCIE_PORT_CONFIG dl_iio_pci_port[] = { + /* Socket | PortIndex | HidePort | DeEmphasis | PortLinkSpeed | MaxPayload | + DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbIndex | + NtbPpd | NtbBarSizeOverride | NtbSplitBar | NtbBarSizeImBar1 | NtbBarSizeImBar2 + NtbBarSizeImBar2_0 | NtbBarSizeImBar2_1| NtbBarSizeEmBarSZ1 | NtbBarSizeEmBarSZ2 + NtbBarSizeEmBarSZ2_0 | NtbBarSizeEmBarSZ2_1 | NtbXlinkCtlOverride */ + /* PORT_1A ~ PORT_1D */ + { 0, PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_1B, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_1C, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_1D, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + /* PORT_2A ~ PORT_2D */ + { 0, PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_2B, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_2C, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_2D, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + /* PORT_3A ~ PORT_3D does not exist */ + /* PORT_4A ~ PORT_4D */ + { 0, PORT_4A, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_4B, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_4C, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_4D, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, }; -#endif /* * DeltaLake PCH PCIe Port Table diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index eabbd6b..ecfb910 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -61,13 +61,30 @@ uint8_t index; oem_update_iio(mupd); - -#if 0 - mupd->FspmConfig.IioPciConfig.ConfigurationTable = - (UPD_PCI_PORT_CONFIG *) dl_iio_pci_port; - mupd->FspmConfig.IioPciConfig.NumberOfEntries = - ARRAY_SIZE(dl_iio_pci_port); -#endif + /* Config IIO PCIe ports from table */ + mupd->FspmConfig.IioPcieConfigTablePtr = (uint32_t) dl_iio_pci_port; + mupd->FspmConfig.IioPcieConfigTableNumber = ARRAY_SIZE(dl_iio_pci_port); + /* Config all IIO PCIe ports? */ + mupd->FspmConfig.IIOPcieRootPortEnable = 1; + mupd->FspmConfig.DeEmphasis = 0x00; + mupd->FspmConfig.IIOPciePortLinkSpeed = PcieAuto; //0 + mupd->FspmConfig.IIOPcieMaxPayload = 0x0; + mupd->FspmConfig.DfxDnTxPreset = 0xFF; + mupd->FspmConfig.DfxRxPreset = 0xFF; + mupd->FspmConfig.DfxUpTxPreset = 0xFF; + mupd->FspmConfig.PcieCommonClock = 0x1; + mupd->FspmConfig.NtbPpd = NTB_PORT_TRANSPARENT; //0 + mupd->FspmConfig.NtbBarSizeOverride = 0x00; + mupd->FspmConfig.NtbSplitBar = 0x00; + mupd->FspmConfig.NtbBarSizeImBar1 = 0x16; + mupd->FspmConfig.NtbBarSizeImBar2 = 0x16; + mupd->FspmConfig.NtbBarSizeImBar2_0 = 0x0C; + mupd->FspmConfig.NtbBarSizeImBar2_1 = 0x0C; + mupd->FspmConfig.NtbBarSizeEmBarSZ1 = 0x16; + mupd->FspmConfig.NtbBarSizeEmBarSZ2 = 0x16; + mupd->FspmConfig.NtbBarSizeEmBarSZ2_0 = 0x0C; + mupd->FspmConfig.NtbBarSizeEmBarSZ2_1 = 0x0C; + mupd->FspmConfig.NtbXlinkCtlOverride = 0x03; for (index = 0; index < ARRAY_SIZE(dl_pch_pci_port); index++) { mupd->FspmConfig.PchPcieForceEnable[dl_pch_pci_port[index].PortIndex] = diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 8cdd01e..6789e92 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -424,11 +424,11 @@ else if (p >= PORT_2A && p <= PORT_2D) return PSTACK1; else if (p >= PORT_4A && p <= PORT_4D) - return PSTACK2; + return PSTACK3; else if (p >= PORT_5A && p <= PORT_5D) - return PSTACK3; // MCP0 + return PSTACK4; // MCP0 else - return PSTACK4; // MCP1 + return MAX_STACKS; // MCP1 } static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack, diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index 4374058..72a3b13 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -77,6 +77,9 @@ KTI_LINK5 } KTI_LOGIC_LINK; +#define HIDE 1 +#define NOT_HIDE 0 + #define IIO_BIFURCATE_xxxxxxxx 0xFE #define IIO_BIFURCATE_x4x4x4x4 0x0 #define IIO_BIFURCATE_x4x4xxx8 0x1 @@ -133,6 +136,44 @@ Iio_IouMax } IIO_IOUS; +typedef struct { + //For IioPcieConfig + UINT8 Socket; + UINT16 PortIndex; + UINT8 HidePort; + UINT8 DeEmphasis; + UINT8 PortLinkSpeed; + UINT8 MaxPayload; + UINT8 DfxDnTxPreset; + UINT8 DfxRxPreset; + UINT8 DfxUpTxPreset; + UINT8 Sris; + UINT8 PcieCommonClock; + //For IIO Ntb^M + UINT8 NtbIndex; + UINT8 NtbPpd; + UINT8 NtbBarSizeOverride; + UINT8 NtbSplitBar; + UINT8 NtbBarSizeImBar1; + UINT8 NtbBarSizeImBar2; + UINT8 NtbBarSizeImBar2_0; + UINT8 NtbBarSizeImBar2_1; + UINT8 NtbBarSizeEmBarSZ1; + UINT8 NtbBarSizeEmBarSZ2; + UINT8 NtbBarSizeEmBarSZ2_0; + UINT8 NtbBarSizeEmBarSZ2_1; + UINT8 NtbXlinkCtlOverride; +} UPD_IIO_PCIE_PORT_CONFIG; + +/** + NTB Per Port Definition + **/ +typedef enum { + NTB_PORT_TRANSPARENT = 0, + NTB_PORT_NTB_NTB +} NTB_PPD; + + /** UPD_PCH_PCIE_PORT: PortIndex - PCH PCIe Port Index. @@ -535,45 +576,160 @@ **/ UINT8 IioConfigIOU4[8]; -/** Offset 0x00F7 - PchAdrEn +/** Offset 0x00F7 +**/ + UINT8 UnusedUpdSpace4; + +/** Offset 0x00F8 - Usage type for IIO PCIE Config Table Ptr + IIO PCIE Config Table Ptr +**/ + UINT32 IioPcieConfigTablePtr; + +/** Offset 0x00FC - Usage type for IIO PCIE Config Table Number + IIO PCIE Config Table Number +**/ + UINT32 IioPcieConfigTableNumber; + +/** Offset 0x0100 - Usage type for IIO PCIE Root Port Enable or Disable + IIO PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, + the value is 0x00 +**/ + UINT8 IIOPcieRootPortEnable; + +/** Offset 0x0101 - Usage type for IIO DeEmphasis + IIO DeEmphasis +**/ + UINT8 DeEmphasis; + +/** Offset 0x0102 - Usage type for IIO PCIE Root Port link speed + IIO root port link speed +**/ + UINT8 IIOPciePortLinkSpeed; + +/** Offset 0x0103 - Usage type for IIO PCIE Root Port Max Payload + IIO Root Port Max Payload +**/ + UINT8 IIOPcieMaxPayload; + +/** Offset 0x0104 - Usage type for IIO DfxDnTxPreset + IIO DfxDnTxPreset +**/ + UINT8 DfxDnTxPreset; + +/** Offset 0x0105 - Usage type for IIO DfxRxPreset + IIO DfxRxPreset +**/ + UINT8 DfxRxPreset; + +/** Offset 0x0106 - Usage type for IIO DfxUpTxPreset + IIO DfxUpTxPreset +**/ + UINT8 DfxUpTxPreset; + +/** Offset 0x0107 - Usage type for IIO PcieCommonClock + IIO PcieCommonClock +**/ + UINT8 PcieCommonClock; + +/** Offset 0x0108 - Usage type for IIO NtbPpd + IIO NtbPpd +**/ + UINT8 NtbPpd; + +/** Offset 0x0109 - Usage type for IIO NtbBarSizeOverride + IIO NtbBarSizeOverride +**/ + UINT8 NtbBarSizeOverride; + +/** Offset 0x010A - Usage type for IIO NtbSplitBar + IIO NtbSplitBar +**/ + UINT8 NtbSplitBar; + +/** Offset 0x010B - Usage type for IIO NtbBarSizeImBar1 + IIO NtbBarSizeImBar1 +**/ + UINT8 NtbBarSizeImBar1; + +/** Offset 0x010C - Usage type for IIO NtbBarSizeImBar2 + IIO PNtbBarSizeImBar2 +**/ + UINT8 NtbBarSizeImBar2; + +/** Offset 0x010D - Usage type for IIO NtbBarSizeImBar2_0 + IIO PNtbBarSizeImBar2_0 +**/ + UINT8 NtbBarSizeImBar2_0; + +/** Offset 0x010E - Usage type for IIO NtbBarSizeImBar2_1 + IIO NtbBarSizeImBar2_1 +**/ + UINT8 NtbBarSizeImBar2_1; + +/** Offset 0x010F - Usage type for IIO NtbBarSizeEmBarSZ1 + IIO NtbBarSizeEmBarSZ1 +**/ + UINT8 NtbBarSizeEmBarSZ1; + +/** Offset 0x0110 - Usage type for IIO NtbBarSizeEmBarSZ2 + IIO NtbBarSizeEmBarSZ2 +**/ + UINT8 NtbBarSizeEmBarSZ2; + +/** Offset 0x0111 - Usage type for IIO NtbBarSizeEmBarSZ2_0 + IIO NtbBarSizeEmBarSZ2_0 +**/ + UINT8 NtbBarSizeEmBarSZ2_0; + +/** Offset 0x0112 - Usage type for IIO NtbBarSizeEmBarSZ2_1 + IIO NtbBarSizeEmBarSZ2_1 +**/ + UINT8 NtbBarSizeEmBarSZ2_1; + +/** Offset 0x0113 - Usage type for IIO NtbXlinkCtlOverride + IIO NtbXlinkCtlOverride +**/ + UINT8 NtbXlinkCtlOverride; + +/** Offset 0x0114 - PchAdrEn Enable or Disable PchAdr **/ UINT8 PchAdrEn; -/** Offset 0x00F8 - } TYPE:{Combo +/** Offset 0x0115 - } TYPE:{Combo Root port swapping based on device connection status : TRUE or FALSE TRUE : 0x01, FALSE : 0x00 **/ UINT8 PchPcieRootPortFunctionSwap; -/** Offset 0x00F9 - PCH PCIE PLL Ssc +/** Offset 0x0116 - PCH PCIE PLL Ssc Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0%), Auto : 0xFE(Set to hardware default), Disable : 0xFF **/ UINT8 PchPciePllSsc; -/** Offset 0x00FA - Usage type for PCH PCIE Root Port Index +/** Offset 0x0117 - Usage type for PCH PCIE Root Port Index Index assigned to every PCH PCIE Root Port **/ UINT8 PchPciePortIndex[20]; -/** Offset 0x010E - Usage type for PCH PCIE Root Port Enable or Disable +/** Offset 0x012B - Usage type for PCH PCIE Root Port Enable or Disable 0-19: PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, the value is 0x00 **/ UINT8 PchPcieForceEnable[20]; -/** Offset 0x0122 - Usage type for PCH PCIE Root Port Link Speed +/** Offset 0x013F - Usage type for PCH PCIE Root Port Link Speed 0-19: PCH rootport, 0x00 : Pcie Auto Speed, 0x01 : Pcie Gen1 Speed, 0x02 : Pcie Gen2 Speed, 0x03 : Pcie Gen3 Speed **/ UINT8 PchPciePortLinkSpeed[20]; -/** Offset 0x0136 +/** Offset 0x0153 **/ - UINT8 UnusedUpdSpace4[2]; + UINT8 UnusedUpdSpace5[1]; -/** Offset 0x0138 +/** Offset 0x0154 **/ UINT8 ReservedMemoryInitUpd[16]; } FSP_M_CONFIG; @@ -594,11 +750,11 @@ **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0148 +/** Offset 0x0164 **/ - UINT8 UnusedUpdSpace5[6]; + UINT8 UnusedUpdSpace6[2]; -/** Offset 0x014E +/** Offset 0x0166 **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h index 7ac630f..79b7d7a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -102,6 +102,11 @@ PORT_2C, PORT_2D, // IOU2 + PORT_3A, + PORT_3B, + PORT_3C, + PORT_3D, + // IOU3 PORT_4A, PORT_4B, PORT_4C, -- To view, visit https://review.coreboot.org/c/coreboot/+/42096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cff6d71588f91c3210cbaa17484644d5b89cc62 Gerrit-Change-Number: 42096 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

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Change in libgfxinit[master]: [HACK] Switch LSPCON to PCON mode
by Angel Pons (Code Review) 11 May '21

11 May '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/46631 ) Change subject: [HACK] Switch LSPCON to PCON mode ...................................................................... [HACK] Switch LSPCON to PCON mode Change-Id: I3c9e67caf9511d62b19c0c175e8e75080fb7ac7d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M common/hw-gfx-dp_aux_ch.adb M common/hw-gfx-dp_aux_ch.ads M common/hw-gfx-dp_info.adb 3 files changed, 156 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/31/46631/1 diff --git a/common/hw-gfx-dp_aux_ch.adb b/common/hw-gfx-dp_aux_ch.adb index b8eb510..7406d5e 100644 --- a/common/hw-gfx-dp_aux_ch.adb +++ b/common/hw-gfx-dp_aux_ch.adb @@ -371,6 +371,42 @@ ---------------------------------------------------------------------------- + procedure I2C_Write_Byte + (Port : in T; + Address : in I2C.Transfer_Address; + Offset : in Word8; + Value : in Word8; + Success : out Boolean) + is + Index_Payload : constant DP_Defs.Aux_Payload := (Offset, Value, others => 16#00#); + + Length : constant I2C.Transfer_Length := 1; + Data : constant I2C.Transfer_Data := (Value, others => 16#00#); + begin + Do_I2C_Write (Port, Address, 1 + Length, Index_Payload, Success); + end I2C_Write_Byte; + + procedure I2C_Read_Byte + (Port : in T; + Address : in I2C.Transfer_Address; + Offset : in Word8; + Value : out Word8; + Success : out Boolean) + is + Index_Payload : constant DP_Defs.Aux_Payload := (Offset, others => 16#00#); + + Length : I2C.Transfer_Length := 1; + Data : I2C.Transfer_Data := (others => 16#00#); + begin + Do_I2C_Write (Port, Address, 1, Index_Payload, Success); + + if Success then + Do_I2C_Read (Port, Address, Length, Data, Success); + Success := Success and Length = 1; + end if; + Value := Data (0); + end I2C_Read_Byte; + procedure I2C_Read (Port : in T; Address : in I2C.Transfer_Address; diff --git a/common/hw-gfx-dp_aux_ch.ads b/common/hw-gfx-dp_aux_ch.ads index 85fddd0..78709a8 100644 --- a/common/hw-gfx-dp_aux_ch.ads +++ b/common/hw-gfx-dp_aux_ch.ads @@ -45,6 +45,20 @@ ---------------------------------------------------------------------------- + procedure I2C_Write_Byte + (Port : in T; + Address : in I2C.Transfer_Address; + Offset : in Word8; + Value : in Word8; + Success : out Boolean); + + procedure I2C_Read_Byte + (Port : in T; + Address : in I2C.Transfer_Address; + Offset : in Word8; + Value : out Word8; + Success : out Boolean); + procedure I2C_Read (Port : in T; Address : in I2C.Transfer_Address; diff --git a/common/hw-gfx-dp_info.adb b/common/hw-gfx-dp_info.adb index bf09933..93a1caf 100644 --- a/common/hw-gfx-dp_info.adb +++ b/common/hw-gfx-dp_info.adb @@ -15,15 +15,115 @@ with Ada.Unchecked_Conversion; with HW.Debug; +with HW.Time; with GNAT.Source_Info; with HW.GFX.DP_Defs; +with HW.GFX.I2C; use type HW.Word8; use type HW.Word16; package body HW.GFX.DP_Info is + procedure Read_Lspcon_Mode + (Port : in T; + Mode : out Word8; + Success : out Boolean) + is + begin + pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + + for I in 1 .. 6 loop + Aux_Ch.I2C_Read_Byte + (Port => Port, + Address => 16#40#, + Offset => 16#41#, + Value => Mode, + Success => Success); + exit when Success; + Time.U_Delay (500); + end loop; + end Read_Lspcon_Mode; + + procedure Write_Lspcon_Mode + (Port : in T; + Mode : in Word8; + Success : out Boolean) + is + begin + pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + + for I in 1 .. 6 loop + Aux_Ch.I2C_Write_Byte + (Port => Port, + Address => 16#40#, + Offset => 16#40#, + Value => 16#01#, + Success => Success); + exit when Success; + Time.U_Delay (500); + end loop; + end Write_Lspcon_Mode; + + procedure Set_Lspcon_To_Pcon_Mode (Port : in T; Success : out Boolean) + is + Timeout : constant Natural := 20; + Lspcon_Mode : Word8; + begin + pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + + Read_Lspcon_Mode + (Port => Port, + Mode => Lspcon_Mode, + Success => Success); + + if not Success then + pragma Debug (Debug.Put_Line ("Could not determine LSPCON mode.")); + return; + end if; + + pragma Debug (Debug.Put_Line ("Current LSPCON mode: " & Lspcon_Mode'Image)); + + if Lspcon_Mode /= 0 then + pragma Debug (Debug.Put_Line ("LSPCON mode is good enough.")); + return; + end if; + + -- Change to PCON mode if necessary + Write_Lspcon_Mode + (Port => Port, + Mode => Lspcon_Mode, + Success => Success); + + if not Success then + pragma Debug (Debug.Put_Line ("Could not write new LSPCON mode.")); + return; + end if; + + for I in 1 .. Timeout loop + Read_Lspcon_Mode + (Port => Port, + Mode => Lspcon_Mode, + Success => Success); + if not Success then + pragma Debug (Debug.Put_Line ("Could not determine new LSPCON mode.")); + return; + end if; + if Lspcon_Mode /= 0 then + pragma Debug (Debug.Put_Line ("Successfully set LSPCON to PCON mode.")); + pragma Debug (Debug.Put_Line ("Current LSPCON mode: " & Lspcon_Mode'Image)); + return; + end if; + Time.M_Delay (100); + end loop; + if Success then + pragma Debug (Debug.Put_Line ("Timed out waiting for LSPCON mode change.")); + pragma Debug (Debug.Put_Line ("Current LSPCON mode: " & Lspcon_Mode'Image)); + Success := False; + end if; + end Set_Lspcon_To_Pcon_Mode; + procedure Read_Caps (Link : in out DP_Link; Port : in T; @@ -36,6 +136,12 @@ begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + Set_Lspcon_To_Pcon_Mode (Port, Success); + + if not Success then + pragma Debug (Debug.Put_Line ("Could not change LSPCON mode.")); + end if; + Length := Caps_Size; Aux_Ch.Aux_Read (Port => Port, -- To view, visit https://review.coreboot.org/c/libgfxinit/+/46631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I3c9e67caf9511d62b19c0c175e8e75080fb7ac7d Gerrit-Change-Number: 46631 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 13

Change in coreboot[master]: arch/riscv: Fixed exception handling when CONFIG_RISCV_WORKING_HARTID...
by Xiang Wang (Code Review) 07 May '21

07 May '21

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37461 ) Change subject: arch/riscv: Fixed exception handling when CONFIG_RISCV_WORKING_HARTID not equal 0 ...................................................................... arch/riscv: Fixed exception handling when CONFIG_RISCV_WORKING_HARTID not equal 0 Change-Id: Ic45560b4bfbf9366425ef4006ac2765113457349 Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org> --- M src/arch/riscv/trap_util.S 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/37461/1 diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 8aba48b..8c1f6cc 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -118,6 +118,7 @@ # someday this gets fixed. //csrr sp, mhartid csrr sp, 0xf14 + addi sp, sp, -CONFIG_RISCV_WORKING_HARTID .Lsmp_hang: bnez sp, .Lsmp_hang -- To view, visit https://review.coreboot.org/c/coreboot/+/37461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic45560b4bfbf9366425ef4006ac2765113457349 Gerrit-Change-Number: 37461 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-MessageType: newchange

3 7

Change in libgfxinit[master]: [HACK] Implement more WAs
by Angel Pons (Code Review) 06 May '21

06 May '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/46635 ) Change subject: [HACK] Implement more WAs ...................................................................... [HACK] Implement more WAs Change-Id: I4cd64cf4c1e702dc05709adc345a976a4e3c1ded Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M common/skylake/hw-gfx-gma-power_and_clocks.adb 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/35/46635/1 diff --git a/common/skylake/hw-gfx-gma-power_and_clocks.adb b/common/skylake/hw-gfx-gma-power_and_clocks.adb index c860e1b..1501ea7 100644 --- a/common/skylake/hw-gfx-gma-power_and_clocks.adb +++ b/common/skylake/hw-gfx-gma-power_and_clocks.adb @@ -82,6 +82,9 @@ CNP_PWM_CGE_GATING_DISABLE : constant := 1 * 2 ** 13; + DISP_FBC_MEMORY_WAKE : constant := 1 * 2 ** 31; + DISP_FBC_WM_DIS : constant := 1 * 2 ** 15; + ---------------------------------------------------------------------------- CDCLK_CTL_CD_FREQ_SELECT_MASK : constant := 3 * 2 ** 26; @@ -340,6 +343,13 @@ (Register => Registers.PCH_DSPCLK_GATE_D, Mask => CNP_PWM_CGE_GATING_DISABLE); + -- Display WA #0562 WaFbcTurnOffFbcWatermark:cfl + -- Display WA #0859 WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl + Registers.Set_Mask + (Register => Registers.ARB_CTL, + Mask => DISP_FBC_WM_DIS or + DISP_FBC_MEMORY_WAKE); + Get_Cur_CDClk (Config.CDClk); Get_Max_CDClk (Config.Max_CDClk); Set_CDClk (Config.Default_CDClk_Freq); -- To view, visit https://review.coreboot.org/c/libgfxinit/+/46635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I4cd64cf4c1e702dc05709adc345a976a4e3c1ded Gerrit-Change-Number: 46635 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 11

Change in coreboot[master]: [TEST] mb/google/volteer: Update PL1 and PL2 setting on halvor
by John Su (Code Review) 03 May '21

03 May '21

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44630 ) Change subject: [TEST] mb/google/volteer: Update PL1 and PL2 setting on halvor ...................................................................... [TEST] mb/google/volteer: Update PL1 and PL2 setting on halvor This is test patch to update PL1 and PL2 on halvor. Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I26be0031c70264cd652ceb288ade30dd4d0c7c92 --- M src/mainboard/google/volteer/variants/halvor/overridetree.cb 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/44630/1 diff --git a/src/mainboard/google/volteer/variants/halvor/overridetree.cb b/src/mainboard/google/volteer/variants/halvor/overridetree.cb index c6ac1b7..d85bc3e 100644 --- a/src/mainboard/google/volteer/variants/halvor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/halvor/overridetree.cb @@ -17,7 +17,32 @@ register "SaGv" = "SaGv_Disabled" + register "power_limits_config[POWER_LIMITS_Y_4_CORE]" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 15, + }" + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 7000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200,}" + + register "controls.power_limits.pl2" = "{ + .min_power = 7000, + .max_power = 15000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000,}" + + device generic 0 on end + end + end # DPTF device pci 15.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- To view, visit https://review.coreboot.org/c/coreboot/+/44630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26be0031c70264cd652ceb288ade30dd4d0c7c92 Gerrit-Change-Number: 44630 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: HACK: soc/mediatek: Add function to raise the big CPU frequency
by Yidi Lin (Code Review) 02 May '21

02 May '21

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46410 to review the following change. Change subject: HACK: soc/mediatek: Add function to raise the big CPU frequency ...................................................................... HACK: soc/mediatek: Add function to raise the big CPU frequency Implement mt_pll_raise_ca76_freq() in MT8192 to raise the frequency. usage: mt_pll_raise_ca76_freq(2200UL * MHz); Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> Change-Id: I2ebc4c0230e7c42c887bdac227eb366deb743986 --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/pll.c 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/46410/1 diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index d9ba230..54b12e8 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -59,6 +59,7 @@ int pll_set_rate(const struct pll *pll, u32 rate); void mt_pll_init(void); void mt_pll_raise_little_cpu_freq(u32 freq); +void mt_pll_raise_ca76_freq(u32 freq); enum fmeter_type { FMETER_ABIST = 0, diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index 0366cd6..cd65d25 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -546,3 +546,30 @@ return 0; } + +void mt_pll_raise_ca76_freq(u32 freq) +{ + /* enable [4] intermediate clock armpll_divider_pll1_ck */ + setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); + + /* switch ca76 clock source to intermediate clock */ + clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, + MCU_MUX_SRC_DIV_PLL1); + + /* disable armpll_bl frequency output */ + clrbits32(plls[APMIXED_ARMPLL_BL].reg, PLL_EN); + + /* raise armpll_bl frequency */ + pll_set_rate(&plls[APMIXED_ARMPLL_BL], freq); + + /* enable armpll_bl frequency output */ + setbits32(plls[APMIXED_ARMPLL_BL].reg, PLL_EN); + udelay(PLL_EN_DELAY); + + /* switch ca76 clock source back to armpll_bl */ + clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, + MCU_MUX_SRC_PLL); + + /* disable [4] intermediate clock armpll_divider_pll1_ck */ + clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ebc4c0230e7c42c887bdac227eb366deb743986 Gerrit-Change-Number: 46410 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: [WIP]mb/lenovo/w541: Add Lenovo ThinkPad W541
by Peter Lemenkov (Code Review) 26 Apr '21

26 Apr '21

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38733 ) Change subject: [WIP]mb/lenovo/w541: Add Lenovo ThinkPad W541 ...................................................................... [WIP]mb/lenovo/w541: Add Lenovo ThinkPad W541 UNTESTED. Change-Id: I315627cba495bfc376321c632248e50734daac71 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- A src/mainboard/lenovo/w541/Kconfig A src/mainboard/lenovo/w541/Kconfig.name A src/mainboard/lenovo/w541/Makefile.inc A src/mainboard/lenovo/w541/acpi/ec.asl A src/mainboard/lenovo/w541/acpi/platform.asl A src/mainboard/lenovo/w541/acpi/superio.asl A src/mainboard/lenovo/w541/acpi_tables.c A src/mainboard/lenovo/w541/board_info.txt A src/mainboard/lenovo/w541/data.vbt A src/mainboard/lenovo/w541/devicetree.cb A src/mainboard/lenovo/w541/dsdt.asl A src/mainboard/lenovo/w541/gma-mainboard.ads A src/mainboard/lenovo/w541/gpio.c A src/mainboard/lenovo/w541/hda_verb.c A src/mainboard/lenovo/w541/mainboard.c A src/mainboard/lenovo/w541/romstage.c A src/mainboard/lenovo/w541/smihandler.c 17 files changed, 807 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/38733/1 diff --git a/src/mainboard/lenovo/w541/Kconfig b/src/mainboard/lenovo/w541/Kconfig new file mode 100644 index 0000000..4c016fa --- /dev/null +++ b/src/mainboard/lenovo/w541/Kconfig @@ -0,0 +1,42 @@ +if BOARD_LENOVO_THINKPAD_W541 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_2048 # FIXME: correct this + select CPU_INTEL_HASWELL + select EC_LENOVO_H8 + select EC_LENOVO_PMH7 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + string + default "lenovo/w541" + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad W541" + +config VGA_BIOS_FILE + string + default "pci8086,0416.rom" + +config VGA_BIOS_ID + string + default "8086,0416" + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/lenovo/w541/Kconfig.name b/src/mainboard/lenovo/w541/Kconfig.name new file mode 100644 index 0000000..f2ee59c --- /dev/null +++ b/src/mainboard/lenovo/w541/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_THINKPAD_W541 + bool "ThinkPad W541" diff --git a/src/mainboard/lenovo/w541/Makefile.inc b/src/mainboard/lenovo/w541/Makefile.inc new file mode 100644 index 0000000..fa6e7af --- /dev/null +++ b/src/mainboard/lenovo/w541/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +smm-y += smihandler.c diff --git a/src/mainboard/lenovo/w541/acpi/ec.asl b/src/mainboard/lenovo/w541/acpi/ec.asl new file mode 100644 index 0000000..3ff0ff7 --- /dev/null +++ b/src/mainboard/lenovo/w541/acpi/ec.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/lenovo/h8/acpi/ec.asl> diff --git a/src/mainboard/lenovo/w541/acpi/platform.asl b/src/mainboard/lenovo/w541/acpi/platform.asl new file mode 100644 index 0000000..add8c2d --- /dev/null +++ b/src/mainboard/lenovo/w541/acpi/platform.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + /* ME may not be up yet. */ + Store (0, \_TZ.MEB1) + Store (0, \_TZ.MEB2) + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC.RADI(0) +} diff --git a/src/mainboard/lenovo/w541/acpi/superio.asl b/src/mainboard/lenovo/w541/acpi/superio.asl new file mode 100644 index 0000000..3139e35 --- /dev/null +++ b/src/mainboard/lenovo/w541/acpi/superio.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/w541/acpi_tables.c b/src/mainboard/lenovo/w541/acpi_tables.c new file mode 100644 index 0000000..ff6c05a --- /dev/null +++ b/src/mainboard/lenovo/w541/acpi_tables.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/lynxpoint/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* the lid is open by default */ + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/lenovo/w541/board_info.txt b/src/mainboard/lenovo/w541/board_info.txt new file mode 100644 index 0000000..cd1d140 --- /dev/null +++ b/src/mainboard/lenovo/w541/board_info.txt @@ -0,0 +1,4 @@ +Category: laptop +FIXME: put ROM package, ROM socketed, ROM protocol, Flashrom support +Board URL: https://www.lenovo.com/us/en/laptops/thinkpad/w-series/w541/ +Release year: 2015 diff --git a/src/mainboard/lenovo/w541/data.vbt b/src/mainboard/lenovo/w541/data.vbt new file mode 100644 index 0000000..4471ca1 --- /dev/null +++ b/src/mainboard/lenovo/w541/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/w541/devicetree.cb b/src/mainboard/lenovo/w541/devicetree.cb new file mode 100644 index 0000000..d7057e4 --- /dev/null +++ b/src/mainboard/lenovo/w541/devicetree.cb @@ -0,0 +1,123 @@ +chip northbridge/intel/haswell # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.ndid" = "3" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "0" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "0" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "0" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + subsystemid 0x17aa 0x2211 inherit + + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics Unsupported PCI device 8086:0c01 + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x17aa 0x221e + end + device pci 03.0 on end # Mini-HD audio Audio controller + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x007c1601" + register "gen2_dec" = "0x000c15e1" + register "gen3_dec" = "0x00040291" + register "gen4_dec" = "0x000c06a1" + register "gpi13_routing" = "2" + register "gpi1_routing" = "2" + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x87" + register "pirqd_routing" = "0x86" + register "pirqe_routing" = "0x8b" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x8a" + register "pirqh_routing" = "0x89" + register "sata_ahci" = "1" + register "sata_port_map" = "0x21" + device pci 14.0 on end # xHCI Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 on end # Management Engine KT + device pci 19.0 on # Intel Gigabit Ethernet Unsupported PCI device 8086:153a + subsystemid 0x17aa 0x2210 + end + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge PCI-LPC bridge + chip ec/lenovo/pmh7 + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + device pnp ff.1 on end # dummy + end + chip ec/lenovo/h8 # FIXME: has_keyboard_backlight, has_power_management_beeps, has_uwb + register "beepmask0" = "0x00" + register "beepmask1" = "0x86" + register "config0" = "0xa6" + register "config1" = "0x05" + register "config2" = "0xa8" + register "config3" = "0xc4" + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xd0" + register "event5_enable" = "0x3c" + register "event7_enable" = "0x81" + register "event8_enable" = "0x7b" + register "event9_enable" = "0xff" + register "eventb_enable" = "0x08" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0x9d" + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on # SMBus + chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/lenovo/w541/dsdt.asl b/src/mainboard/lenovo/w541/dsdt.asl new file mode 100644 index 0000000..69cd416 --- /dev/null +++ b/src/mainboard/lenovo/w541/dsdt.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 +#define THINKPAD_EC_GPE 17 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/lenovo/w541/gma-mainboard.ads b/src/mainboard/lenovo/w541/gma-mainboard.ads new file mode 100644 index 0000000..d7afe73 --- /dev/null +++ b/src/mainboard/lenovo/w541/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/w541/gpio.c b/src/mainboard/lenovo/w541/gpio.c new file mode 100644 index 0000000..23d4cdb --- /dev/null +++ b/src/mainboard/lenovo/w541/gpio.c @@ -0,0 +1,205 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_OUTPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio3 = GPIO_LEVEL_LOW, + .gpio4 = GPIO_LEVEL_LOW, + .gpio5 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/lenovo/w541/hda_verb.c b/src/mainboard/lenovo/w541/hda_verb.c new file mode 100644 index 0000000..6c9c43c --- /dev/null +++ b/src/mainboard/lenovo/w541/hda_verb.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0292, /* Codec Vendor / Device ID: Realtek */ + 0x17aa2211, /* Subsystem ID */ + 12, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x17aa2211), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x0321101f), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x03a11020), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40738105), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/w541/mainboard.c b/src/mainboard/lenovo/w541/mainboard.c new file mode 100644 index 0000000..c53471b --- /dev/null +++ b/src/mainboard/lenovo/w541/mainboard.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <ec/lenovo/h8/h8.h> + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/w541/romstage.c b/src/mainboard/lenovo/w541/romstage.c new file mode 100644 index 0000000..eb95283 --- /dev/null +++ b/src/mainboard/lenovo/w541/romstage.c @@ -0,0 +1,104 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/romstage.h> +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/pei_data.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/lynxpoint/pch.h> + +static const struct rcba_config_instruction rcba_config[] = { + RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +void mainboard_config_superio(void) +{ +} + +void mainboard_romstage_entry(void) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 0, /* mobile */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + /* note that SPD addresses are left-shifted by 1. */ + .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* FIXME: check this */ + .ec_present = 0, + .gbe_enable = 0, /* FIXME: check this */ + .dimm_channel0_disabled = 0, /* FIXME: leave channel 0 enabled */ + .dimm_channel1_disabled = 0, /* FIXME: leave channel 1 enabled */ + .max_ddr3_freq = 1600, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + }, + .usb3_ports = { + { 1, 0 }, + { 1, 0 }, + { 1, USB_OC_PIN_SKIP }, + { 1, USB_OC_PIN_SKIP }, + { 1, 1 }, + { 1, 1 }, + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = rcba_config, + }; + + romstage_common(&romstage_params); +} diff --git a/src/mainboard/lenovo/w541/smihandler.c b/src/mainboard/lenovo/w541/smihandler.c new file mode 100644 index 0000000..29bf797 --- /dev/null +++ b/src/mainboard/lenovo/w541/smihandler.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <ec/lenovo/h8/h8.h> +#include <delay.h> +#include <southbridge/intel/lynxpoint/pch.h> + +#define GPE_EC_SCI 1 +/* FIXME: check this */ +#define GPE_EC_WAKE 13 + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +int mainboard_smi_apmc(u8 data) +{ + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route EC_SCI to SCI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route EC_SCI to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, + * enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + /* Redirect EC WAKE GPE to SCI. */ + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/38733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I315627cba495bfc376321c632248e50734daac71 Gerrit-Change-Number: 38733 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020