Change in coreboot[master]: arch/riscv: Fixed exception handling when CONFIG_RISCV_WORKING_HARTID...
Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37461 )
Change subject: arch/riscv: Fixed exception handling when CONFIG_RISCV_WORKING_HARTID not equal 0 ......................................................................
arch/riscv: Fixed exception handling when CONFIG_RISCV_WORKING_HARTID not equal 0
Change-Id: Ic45560b4bfbf9366425ef4006ac2765113457349 Signed-off-by: Xiang Wang merle@hardenedlinux.org --- M src/arch/riscv/trap_util.S 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/37461/1
diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 8aba48b..8c1f6cc 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -118,6 +118,7 @@ # someday this gets fixed. //csrr sp, mhartid csrr sp, 0xf14 + addi sp, sp, -CONFIG_RISCV_WORKING_HARTID .Lsmp_hang: bnez sp, .Lsmp_hang
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37461 )
Change subject: arch/riscv: Fixed exception handling when CONFIG_RISCV_WORKING_HARTID not equal 0 ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/37461/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37461/1//COMMIT_MSG@7 PS1, Line 7: Fixed Present tense (imperative mood): Fix
Hello ron minnich, Paul Menzel, build bot (Jenkins), Philipp Hug,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37461
to look at the new patch set (#2).
Change subject: arch/riscv: Fix exception handling when CONFIG_RISCV_WORKING_HARTID not equal 0 ......................................................................
arch/riscv: Fix exception handling when CONFIG_RISCV_WORKING_HARTID not equal 0
Change-Id: Ic45560b4bfbf9366425ef4006ac2765113457349 Signed-off-by: Xiang Wang merle@hardenedlinux.org --- M src/arch/riscv/trap_util.S 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/37461/2
Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37461 )
Change subject: arch/riscv: Fix exception handling when CONFIG_RISCV_WORKING_HARTID not equal 0 ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37461/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37461/1//COMMIT_MSG@7 PS1, Line 7: Fixed
Present tense (imperative mood): Fix
Done
Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37461 )
Change subject: arch/riscv: Fix exception handling when CONFIG_RISCV_WORKING_HARTID not equal 0 ......................................................................
Patch Set 2:
Have anything update ?
Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37461 )
Change subject: arch/riscv: Fix exception handling when CONFIG_RISCV_WORKING_HARTID not equal 0 ......................................................................
Patch Set 2:
Have anything update?
Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37461 )
Change subject: arch/riscv: Fix exception handling when CONFIG_RISCV_WORKING_HARTID not equal 0 ......................................................................
Patch Set 2:
Have anything update?
Xiang W has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37461 )
Change subject: arch/riscv: Fix exception handling when CONFIG_RISCV_WORKING_HARTID not equal 0 ......................................................................
Abandoned
This is an imperfect solution, please refer to https://review.coreboot.org/c/coreboot/+/53944
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Paul Menzel (Code Review) -
Xiang W (Code Review)
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Xiang Wang (Code Review)