coreboot-gerrit October 2020

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Change in coreboot[master]: sb/intel/i82371eb: Claim less I/O ports in ACPI
by Keith Hui (Code Review) 06 Apr '21

06 Apr '21

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41093 ) Change subject: sb/intel/i82371eb: Claim less I/O ports in ACPI ...................................................................... sb/intel/i82371eb: Claim less I/O ports in ACPI To avoid resource conflicts, this change leaves unclaimed: - PM and SMBus ports (claimed by MBRS device written in SSDT) - Ports 0x2e-0x2f (After reviewing Asus P3B-F OEM firmware) Change-Id: Id5adb37d047621d7c8faf81607ceea4cbcac3d34 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/i82371eb/acpi/i82371eb.asl 1 file changed, 4 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/41093/1 diff --git a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl index 8b60edb..45e7a5e 100644 --- a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl +++ b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl @@ -31,15 +31,13 @@ { Name (BUF1, ResourceTemplate () { - /* PM register ports */ - IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06) - /* SMBus register ports */ - IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07) /* PIIX4E ports */ /* Aliased DMA ports */ IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, ) /* Aliased PIC ports */ - IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E, ) + /* Do not claim 0x2e-0x2f, per P3B-F vendor DSDT */ + IO (Decode16, 0x0022, 0x0022, 0x01, 0x0C, ) + IO (Decode16, 0x0030, 0x0030, 0x01, 0x10, ) /* Aliased timer ports */ IO (Decode16, 0x0050, 0x0050, 0x01, 0x04, ) IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, ) @@ -49,18 +47,10 @@ IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E, ) IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10, ) IO (Decode16, 0x0294, 0x0294, 0x01, 0x04, ) + /* W83977TF/EF Super I/O config ports */ IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, ) IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, ) }) - CreateWordField (BUF1, _Y06._MIN, PMLO) - CreateWordField (BUF1, _Y06._MAX, PMRL) - CreateWordField (BUF1, _Y07._MIN, SBLO) - CreateWordField (BUF1, _Y07._MAX, SBRL) - - And (\_SB.PCI0.PX43.PM00, 0xFFFE, PMLO) - And (\_SB.PCI0.PX43.SB00, 0xFFFE, SBLO) - Store (PMLO, PMRL) - Store (SBLO, SBRL) Return (BUF1) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/41093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5adb37d047621d7c8faf81607ceea4cbcac3d34 Gerrit-Change-Number: 41093 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 18

Change in coreboot[master]: mb/google/zork: add DDR4 3200 MT40A1G16RC-062E-B 16Gb SPD
by Kevin Chiu (Code Review) 05 Apr '21

05 Apr '21

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44861 ) Change subject: mb/google/zork: add DDR4 3200 MT40A1G16RC-062E-B 16Gb SPD ...................................................................... mb/google/zork: add DDR4 3200 MT40A1G16RC-062E-B 16Gb SPD BUG=b:165956925 BRANCH=zork TEST=emerge-zork coreboot Change-Id: I438310fb74d96953bc83374df3109e4c56192a5f Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- A src/mainboard/google/zork/spd/micron-MT40A1G16RC-062E-B.spd.hex 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/44861/1 diff --git a/src/mainboard/google/zork/spd/micron-MT40A1G16RC-062E-B.spd.hex b/src/mainboard/google/zork/spd/micron-MT40A1G16RC-062E-B.spd.hex new file mode 100644 index 0000000..8483e99 --- /dev/null +++ b/src/mainboard/google/zork/spd/micron-MT40A1G16RC-062E-B.spd.hex @@ -0,0 +1,33 @@ +# Micron MT40A1G16KD-062E:E +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 40 36 +0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 21 7D +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 31 47 +31 36 52 43 2D 30 36 32 45 3A 42 20 20 31 80 2C +42 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/44861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I438310fb74d96953bc83374df3109e4c56192a5f Gerrit-Change-Number: 44861 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: mb/google/asurada: Add Chrome OS GPIOs
by Yidi Lin (Code Review) 01 Apr '21

01 Apr '21

Hello Hung-Te Lin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46386 to review the following change. Change subject: mb/google/asurada: Add Chrome OS GPIOs ...................................................................... mb/google/asurada: Add Chrome OS GPIOs Add the Chrome OS specific GPIOs (WP, EC, H1, ...) GPIOs. BUG=None TEST=emerge-asurada coreboot; # also boots into emmc BRANCH=None Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Change-Id: Ieeeee88a09ae4c3af15e2ae93a29684d30dde493 --- M src/mainboard/google/asurada/Makefile.inc M src/mainboard/google/asurada/bootblock.c M src/mainboard/google/asurada/chromeos.c A src/mainboard/google/asurada/gpio.h 4 files changed, 48 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/46386/1 diff --git a/src/mainboard/google/asurada/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc index c742539..02fb830 100644 --- a/src/mainboard/google/asurada/Makefile.inc +++ b/src/mainboard/google/asurada/Makefile.inc @@ -2,12 +2,15 @@ bootblock-y += memlayout.ld bootblock-y += bootblock.c +bootblock-y += chromeos.c verstage-y += memlayout.ld +verstage-y += chromeos.c verstage-y += reset.c romstage-y += memlayout.ld romstage-y += boardid.c +romstage-y += chromeos.c romstage-y += romstage.c romstage-y += sdram_configs.c diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c index 3eb05e1..04e8898 100644 --- a/src/mainboard/google/asurada/bootblock.c +++ b/src/mainboard/google/asurada/bootblock.c @@ -3,9 +3,12 @@ #include <bootblock_common.h> #include <soc/spi.h> +#include "gpio.h" + void bootblock_mainboard_init(void) { mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); - //gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING); + setup_chromeos_gpios(); + gpio_eint_configure(GPIO_H1_AP_INT, IRQ_TYPE_EDGE_RISING); } diff --git a/src/mainboard/google/asurada/chromeos.c b/src/mainboard/google/asurada/chromeos.c index 8f9fa53..18a350b 100644 --- a/src/mainboard/google/asurada/chromeos.c +++ b/src/mainboard/google/asurada/chromeos.c @@ -5,16 +5,35 @@ #include <gpio.h> #include <security/tpm/tis.h> +#include "gpio.h" + +void setup_chromeos_gpios(void) +{ + gpio_input(GPIO_WP); + gpio_input_pullup(GPIO_EC_AP_INT); + gpio_input_pullup(GPIO_EC_IN_RW); + gpio_input_pullup(GPIO_H1_AP_INT); + gpio_input_pullup(GPIO_SD_CD); + gpio_output(GPIO_RESET, 0); +} + void fill_lb_gpios(struct lb_gpios *gpios) { + struct lb_gpio chromeos_gpios[] = { + {GPIO_EC_IN_RW.id, ACTIVE_HIGH, -1, "EC in RW"}, + {GPIO_EC_AP_INT.id, ACTIVE_LOW, -1, "EC interrupt"}, + {GPIO_H1_AP_INT.id, ACTIVE_HIGH, -1, "TPM interrupt"}, + {GPIO_SD_CD.id, ACTIVE_HIGH, -1, "SD card detect"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_write_protect_state(void) { - return 0; + return !gpio_get(GPIO_WP); } int tis_plat_irq_status(void) { - return 0; + return gpio_eint_poll(GPIO_H1_AP_INT); } diff --git a/src/mainboard/google/asurada/gpio.h b/src/mainboard/google/asurada/gpio.h new file mode 100644 index 0000000..90de583 --- /dev/null +++ b/src/mainboard/google/asurada/gpio.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MAINBOARD_GOOGLE_ASURADA_GPIO_H__ +#define __MAINBOARD_GOOGLE_ASURADA_GPIO_H__ + +#include <soc/gpio.h> + +/* AP_FLASH_WP */ +#define GPIO_WP GPIO(EINT14) +#define GPIO_EC_AP_INT GPIO(EINT5) +#define GPIO_EC_IN_RW GPIO(ANT_SEL8) +#define GPIO_H1_AP_INT GPIO(ANT_SEL9) +/* SD Card Detection */ +#define GPIO_SD_CD GPIO(EINT17) +/* AP_EC_WARM_RST_REQ */ +#define GPIO_RESET GPIO(CAM_PDN2) + +void setup_chromeos_gpios(void); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieeeee88a09ae4c3af15e2ae93a29684d30dde493 Gerrit-Change-Number: 46386 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: soc/ti/am335x: Map useable RAM
by Sam Lewis (Code Review) 30 Mar '21

30 Mar '21

Sam Lewis has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44388 ) Change subject: soc/ti/am335x: Map useable RAM ...................................................................... soc/ti/am335x: Map useable RAM Maps the useable RAM so that it can be used for booting a payload. TEST: Booted a simple ELF payload (that just flashes LEDs) on the Beaglebone Black. Change-Id: I7f657c97e4753071c90ba8ca800a96108807e6b9 Signed-off-by: Sam Lewis <sam.vr.lewis(a)gmail.com> --- M src/soc/ti/am335x/soc.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/44388/1 diff --git a/src/soc/ti/am335x/soc.c b/src/soc/ti/am335x/soc.c index 0362ed9..99c651f 100644 --- a/src/soc/ti/am335x/soc.c +++ b/src/soc/ti/am335x/soc.c @@ -1,7 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> +#include <symbols.h> +#include <bootmem.h> + +static void soc_enable(struct device *dev) +{ + ram_resource(dev, 0, (uintptr_t)_dram / KiB, CONFIG_DRAM_SIZE_MB * MiB / KiB); +} struct chip_operations soc_ti_am335x_ops = { CHIP_NAME("TI AM335X") + .enable_dev = soc_enable, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/44388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f657c97e4753071c90ba8ca800a96108807e6b9 Gerrit-Change-Number: 44388 Gerrit-PatchSet: 1 Gerrit-Owner: Sam Lewis <sam.vr.lewis(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/ti/beaglebone: Initialize DDR3
by Sam Lewis (Code Review) 30 Mar '21

30 Mar '21

Sam Lewis has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44387 ) Change subject: mb/ti/beaglebone: Initialize DDR3 ...................................................................... mb/ti/beaglebone: Initialize DDR3 Adds initialisation of 512MB of DDR memory on the BBB to the romstage. The parameters for the DDR peripherals are taken from U-Boot. TEST: Booted from romstage into ramstage. Also successfully managed to run the "ram_check" in lib.h. Change-Id: I692bfd913c8217a78d073d19c5344c9bb40722a8 Signed-off-by: Sam Lewis <sam.vr.lewis(a)gmail.com> --- M src/mainboard/ti/beaglebone-black/Kconfig A src/mainboard/ti/beaglebone-black/ddr3.h M src/mainboard/ti/beaglebone-black/romstage.c 3 files changed, 76 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/44387/1 diff --git a/src/mainboard/ti/beaglebone-black/Kconfig b/src/mainboard/ti/beaglebone-black/Kconfig index a695942..5e60f25 100644 --- a/src/mainboard/ti/beaglebone-black/Kconfig +++ b/src/mainboard/ti/beaglebone-black/Kconfig @@ -24,7 +24,7 @@ config DRAM_SIZE_MB int - default 256 + default 512 config UART_FOR_CONSOLE int diff --git a/src/mainboard/ti/beaglebone-black/ddr3.h b/src/mainboard/ti/beaglebone-black/ddr3.h new file mode 100644 index 0000000..5ed8f5e --- /dev/null +++ b/src/mainboard/ti/beaglebone-black/ddr3.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Parameters to initialise the DDR3 memory on the Beaglebone Black + * Taken and adapted from U-Boot. + */ + +#ifndef __MAINBOARD_TI_BEAGLEBONE_DDR3_H__ +#define __MAINBOARD_TI_BEAGLEBONE_DDR3_H__ + +/* Micron MT41K256M16HA-125E */ +#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007 +#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB +#define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA +#define MT41K256M16HA125E_EMIF_TIM3 0x501F867F +#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332 +#define MT41K256M16HA125E_EMIF_SDREF 0xC30 +#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4 +#define MT41K256M16HA125E_RATIO 0x80 +#define MT41K256M16HA125E_INVERT_CLKOUT 0x0 +#define MT41K256M16HA125E_RD_DQS 0x38 +#define MT41K256M16HA125E_WR_DQS 0x44 +#define MT41K256M16HA125E_PHY_WR_DATA 0x7D +#define MT41K256M16HA125E_PHY_FIFO_WE 0x94 +#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B + +#define EMIF_OCP_CONFIG_BEAGLEBONE_BLACK 0x00141414 + +const struct ctrl_ioregs ioregs_bonelt = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + +static const struct ddr_data ddr3_beagleblack_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_beagleblack_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; + +#endif diff --git a/src/mainboard/ti/beaglebone-black/romstage.c b/src/mainboard/ti/beaglebone-black/romstage.c index f1f68f9..bdaaaef 100644 --- a/src/mainboard/ti/beaglebone-black/romstage.c +++ b/src/mainboard/ti/beaglebone-black/romstage.c @@ -2,11 +2,20 @@ #include <program_loading.h> #include <console/console.h> +#include <cbmem.h> + +#include <soc/ti/am335x/sdram.h> +#include "ddr3.h" void main(void) { console_init(); printk(BIOS_INFO, "Hello from romstage.\n"); + config_ddr(400, &ioregs_bonelt, &ddr3_beagleblack_data, &ddr3_beagleblack_cmd_ctrl_data, + &ddr3_beagleblack_emif_reg_data, 0); + + cbmem_initialize_empty(); + run_ramstage(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I692bfd913c8217a78d073d19c5344c9bb40722a8 Gerrit-Change-Number: 44387 Gerrit-PatchSet: 1 Gerrit-Owner: Sam Lewis <sam.vr.lewis(a)gmail.com> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: soc/ti/am335x: Add SDRAM initialization driver
by Sam Lewis (Code Review) 30 Mar '21

30 Mar '21

Sam Lewis has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44386 ) Change subject: soc/ti/am335x: Add SDRAM initialization driver ...................................................................... soc/ti/am335x: Add SDRAM initialization driver Adds code taken and (barely) adapted from U-Boot for SDRAM initialization. This should in theory work for other configurations than the Beaglebone Black's DRAM configuration, but hasn't been tested. Change-Id: Ib1bc2fa606f7010c8c789aa7a5c37cd41bc484b9 Signed-off-by: Sam Lewis <sam.vr.lewis(a)gmail.com> --- M src/soc/ti/am335x/Makefile.inc A src/soc/ti/am335x/sdram.c A src/soc/ti/am335x/sdram.h 3 files changed, 714 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/44386/1 diff --git a/src/soc/ti/am335x/Makefile.inc b/src/soc/ti/am335x/Makefile.inc index 990a61e..18d28796 100644 --- a/src/soc/ti/am335x/Makefile.inc +++ b/src/soc/ti/am335x/Makefile.inc @@ -7,6 +7,7 @@ romstage-y += cbmem.c romstage-y += timer.c romstage-y += mmc.c +romstage-y += sdram.c ramstage-y += timer.c ramstage-y += soc.c diff --git a/src/soc/ti/am335x/sdram.c b/src/soc/ti/am335x/sdram.c new file mode 100644 index 0000000..ac9dffb --- /dev/null +++ b/src/soc/ti/am335x/sdram.c @@ -0,0 +1,329 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Taken and adapted from U-Boot. + */ + +#include "sdram.h" +#include <types.h> +#include <device/mmio.h> +#include <delay.h> +#include "clock.h" + +static struct vtp_reg *vtpreg[2] = {(struct vtp_reg *)VTP0_CTRL_ADDR, + (struct vtp_reg *)VTP1_CTRL_ADDR}; + +/** + * Base address for EMIF instances + */ +static struct emif_reg_struct *emif_reg[2] = {(struct emif_reg_struct *)EMIF4_0_CFG_BASE, + (struct emif_reg_struct *)EMIF4_1_CFG_BASE}; + +/** + * Base addresses for DDR PHY cmd/data regs + */ +static struct ddr_cmd_regs *ddr_cmd_reg[2] = {(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR, + (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2}; + +static struct ddr_data_regs *ddr_data_reg[2] = {(struct ddr_data_regs *)DDR_PHY_DATA_ADDR, + (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2}; + +/** + * Base address for ddr io control instances + */ +static struct ddr_cmdtctrl *ioctrl_reg = {(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR}; + +struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE; + +static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; + + +static void config_vtp(int nr) +{ + write32(&vtpreg[nr]->vtp0ctrlreg, read32(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE); + write32(&vtpreg[nr]->vtp0ctrlreg, + read32(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN)); + write32(&vtpreg[nr]->vtp0ctrlreg, read32(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN); + + /* Poll for READY */ + while ((read32(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) != VTP_CTRL_READY) + ; +} + +/** + * Configure SDRAM + */ +static void config_sdram(const struct emif_regs *regs, int nr) +{ + if (regs->zq_config) { + write32(&emif_reg[nr]->emif_zq_config, regs->zq_config); + write32(&cstat->secure_emif_sdram_config, regs->sdram_config); + write32(&emif_reg[nr]->emif_sdram_config, regs->sdram_config); + + /* Trigger initialization */ + write32(&emif_reg[nr]->emif_sdram_ref_ctrl, 0x00003100); + /* Wait 1ms because of L3 timeout error */ + udelay(1000); + + /* Write proper sdram_ref_cref_ctrl value */ + write32(&emif_reg[nr]->emif_sdram_ref_ctrl, regs->ref_ctrl); + write32(&emif_reg[nr]->emif_sdram_ref_ctrl_shdw, regs->ref_ctrl); + } + write32(&emif_reg[nr]->emif_sdram_ref_ctrl, regs->ref_ctrl); + write32(&emif_reg[nr]->emif_sdram_ref_ctrl_shdw, regs->ref_ctrl); + write32(&emif_reg[nr]->emif_sdram_config, regs->sdram_config); + + /* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */ + if (regs->ocp_config) + write32(&emif_reg[nr]->emif_l3_config, regs->ocp_config); +} + +/** + * Configure DDR DATA registers + */ +static void config_ddr_data(const struct ddr_data *data, int nr) +{ + int i; + + if (!data) + return; + + for (i = 0; i < DDR_DATA_REGS_NR; i++) { + write32(&(ddr_data_reg[nr] + i)->dt0rdsratio0, data->datardsratio0); + write32(&(ddr_data_reg[nr] + i)->dt0wdsratio0, data->datawdsratio0); + write32(&(ddr_data_reg[nr] + i)->dt0wiratio0, data->datawiratio0); + write32(&(ddr_data_reg[nr] + i)->dt0giratio0, data->datagiratio0); + write32(&(ddr_data_reg[nr] + i)->dt0fwsratio0, data->datafwsratio0); + write32(&(ddr_data_reg[nr] + i)->dt0wrsratio0, data->datawrsratio0); + } +} + +static void config_io_ctrl(const struct ctrl_ioregs *ioregs) +{ + if (!ioregs) + return; + + write32(&ioctrl_reg->cm0ioctl, ioregs->cm0ioctl); + write32(&ioctrl_reg->cm1ioctl, ioregs->cm1ioctl); + write32(&ioctrl_reg->cm2ioctl, ioregs->cm2ioctl); + write32(&ioctrl_reg->dt0ioctl, ioregs->dt0ioctl); + write32(&ioctrl_reg->dt1ioctl, ioregs->dt1ioctl); +} + + +/** + * Configure DDR CMD control registers + */ +static void config_cmd_ctrl(const struct cmd_control *cmd, int nr) +{ + if (!cmd) + return; + + write32(&ddr_cmd_reg[nr]->cm0csratio, cmd->cmd0csratio); + write32(&ddr_cmd_reg[nr]->cm0iclkout, cmd->cmd0iclkout); + + write32(&ddr_cmd_reg[nr]->cm1csratio, cmd->cmd1csratio); + write32(&ddr_cmd_reg[nr]->cm1iclkout, cmd->cmd1iclkout); + + write32(&ddr_cmd_reg[nr]->cm2csratio, cmd->cmd2csratio); + write32(&ddr_cmd_reg[nr]->cm2iclkout, cmd->cmd2iclkout); +} + +static inline uint32_t get_emif_rev(uint32_t base) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + return (read32(&emif->emif_mod_id_rev) & EMIF_REG_MAJOR_REVISION_MASK) + >> EMIF_REG_MAJOR_REVISION_SHIFT; +} + +/* + * Get SDRAM type connected to EMIF. + * Assuming similar SDRAM parts are connected to both EMIF's + * which is typically the case. So it is sufficient to get + * SDRAM type from EMIF1. + */ +static inline uint32_t emif_sdram_type(uint32_t sdram_config) +{ + return (sdram_config & EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT; +} + +/* + * Configure EXT PHY registers for software leveling + */ +static void ext_phy_settings_swlvl(const struct emif_regs *regs, int nr) +{ + uint32_t *ext_phy_ctrl_base = 0; + uint32_t *emif_ext_phy_ctrl_base = 0; + uint32_t i = 0; + + ext_phy_ctrl_base = (uint32_t *)&(regs->emif_ddr_ext_phy_ctrl_1); + emif_ext_phy_ctrl_base = (uint32_t *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1); + + /* Configure external phy control timing registers */ + for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) { + write32(emif_ext_phy_ctrl_base++, *ext_phy_ctrl_base); + /* Update shadow registers */ + write32(emif_ext_phy_ctrl_base++, *ext_phy_ctrl_base++); + } +} + +/* + * Configure EXT PHY registers for hardware leveling + */ +static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr) +{ + /* + * Enable hardware leveling on the EMIF. For details about these + * magic values please see the EMIF registers section of the TRM. + */ + if (regs->emif_ddr_phy_ctlr_1 & 0x00040000) { + /* PHY_INVERT_CLKOUT = 1 */ + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_1, 0x00040100); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw, 0x00040100); + } else { + /* PHY_INVERT_CLKOUT = 0 */ + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_1, 0x08020080); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw, 0x08020080); + } + + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_22, 0x00000000); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw, 0x00000000); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_23, 0x00600020); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw, 0x00600020); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_24, 0x40010080); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw, 0x40010080); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_25, 0x08102040); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw, 0x08102040); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_26, 0x00200020); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw, 0x00200020); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_27, 0x00200020); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw, 0x00200020); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_28, 0x00200020); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw, 0x00200020); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_29, 0x00200020); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw, 0x00200020); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_30, 0x00200020); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw, 0x00200020); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_31, 0x00000000); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw, 0x00000000); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_32, 0x00000000); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw, 0x00000000); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_33, 0x00000000); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw, 0x00000000); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_34, 0x00000000); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw, 0x00000000); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_35, 0x00000000); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw, 0x00000000); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36, 0x00000077); + write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw, 0x00000077); + + /* + * Sequence to ensure that the PHY is again in a known state after + * hardware leveling. + */ + write32(&emif_reg[nr]->emif_iodft_tlgc, 0x2011); + write32(&emif_reg[nr]->emif_iodft_tlgc, 0x2411); + write32(&emif_reg[nr]->emif_iodft_tlgc, 0x2011); +} + + +/** + * Configure DDR PHY + */ +static void config_ddr_phy(const struct emif_regs *regs, int nr) +{ + /* + * Disable initialization and refreshes for now until we finish + * programming EMIF regs and set time between rising edge of + * DDR_RESET to rising edge of DDR_CKE to > 500us per memory spec. + * We currently hardcode a value based on a max expected frequency + * of 400MHz. + */ + write32(&emif_reg[nr]->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK | 0x3100); + + write32(&emif_reg[nr]->emif_ddr_phy_ctrl_1, regs->emif_ddr_phy_ctlr_1); + write32(&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw, regs->emif_ddr_phy_ctlr_1); + + if (get_emif_rev((uint32_t)emif_reg[nr]) == EMIF_4D5) { + if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) + ext_phy_settings_hwlvl(regs, nr); + else + ext_phy_settings_swlvl(regs, nr); + } +} + +/** + * Set SDRAM timings + */ +static void set_sdram_timings(const struct emif_regs *regs, int nr) +{ + write32(&emif_reg[nr]->emif_sdram_tim_1, regs->sdram_tim1); + write32(&emif_reg[nr]->emif_sdram_tim_1_shdw, regs->sdram_tim1); + write32(&emif_reg[nr]->emif_sdram_tim_2, regs->sdram_tim2); + write32(&emif_reg[nr]->emif_sdram_tim_2_shdw, regs->sdram_tim2); + write32(&emif_reg[nr]->emif_sdram_tim_3, regs->sdram_tim3); + write32(&emif_reg[nr]->emif_sdram_tim_3_shdw, regs->sdram_tim3); +} + +static void ddr_pll_config(uint32_t ddrpll_m) +{ + uint32_t clkmode, clksel, div_m2; + + clkmode = read32(&am335x_cm_wkup->clkmode_dpll_ddr); + clksel = read32(&am335x_cm_wkup->clksel_dpll_ddr); + div_m2 = read32(&am335x_cm_wkup->div_m2_dpll_ddr); + + /* Set the PLL to bypass Mode */ + clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE; + write32(&am335x_cm_wkup->clkmode_dpll_ddr, clkmode); + + /* Wait till bypass mode is enabled */ + while ((read32(&am335x_cm_wkup->idlest_dpll_ddr) & ST_MN_BYPASS) != ST_MN_BYPASS) + ; + + clksel = clksel & (~CLK_SEL_MASK); + clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N); + write32(&am335x_cm_wkup->clksel_dpll_ddr, clksel); + + div_m2 = div_m2 & CLK_DIV_SEL; + div_m2 = div_m2 | DDRPLL_M2; + write32(&am335x_cm_wkup->div_m2_dpll_ddr, div_m2); + + clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL; + write32(&am335x_cm_wkup->clkmode_dpll_ddr, clkmode); + + /* Wait till dpll is locked */ + while ((read32(&am335x_cm_wkup->idlest_dpll_ddr) & ST_DPLL_CLK) != ST_DPLL_CLK) + ; +} + + +static void enable_emif_clocks(void) +{ + /* Enable EMIF0 Clock */ + write32(&am335x_cm_per->emif, CM_MODULEMODE_ENABLED); + /* Poll if module is functional */ + while ((read32(&am335x_cm_per->emif)) != CM_MODULEMODE_ENABLED) + ; +} + +void config_ddr(uint32_t pll, const struct ctrl_ioregs *ioregs, const struct ddr_data *data, + const struct cmd_control *ctrl, const struct emif_regs *regs, int nr) +{ + enable_emif_clocks(); + ddr_pll_config(pll); + config_vtp(nr); + config_cmd_ctrl(ctrl, nr); + config_ddr_data(data, nr); + config_io_ctrl(ioregs); + + /* Set CKE to be controlled by EMIF/DDR PHY */ + write32(&ddrctrl->ddrckectrl, DDR_CKE_CTRL_NORMAL); + + /* Program EMIF instance */ + config_ddr_phy(regs, nr); + + set_sdram_timings(regs, nr); + config_sdram(regs, nr); +} diff --git a/src/soc/ti/am335x/sdram.h b/src/soc/ti/am335x/sdram.h new file mode 100644 index 0000000..e76073f --- /dev/null +++ b/src/soc/ti/am335x/sdram.h @@ -0,0 +1,384 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __CPU_TI_AM335X_DDR_INIT_H__ +#define __CPU_TI_AM335X_DDR_INIT_H__ + +#include <types.h> + +struct ctrl_ioregs { + uint32_t cm0ioctl; + uint32_t cm1ioctl; + uint32_t cm2ioctl; + uint32_t dt0ioctl; + uint32_t dt1ioctl; + uint32_t dt2ioctrl; + uint32_t dt3ioctrl; + uint32_t emif_sdram_config_ext; +}; + +/** + * Encapsulates DDR DATA registers. + */ +struct ddr_data { + uint32_t datardsratio0; + uint32_t datawdsratio0; + uint32_t datawiratio0; + uint32_t datagiratio0; + uint32_t datafwsratio0; + uint32_t datawrsratio0; +}; + +/** + * Encapsulates DDR CMD control registers. + */ +struct cmd_control { + uint32_t cmd0csratio; + uint32_t cmd0csforce; + uint32_t cmd0csdelay; + uint32_t cmd0iclkout; + uint32_t cmd1csratio; + uint32_t cmd1csforce; + uint32_t cmd1csdelay; + uint32_t cmd1iclkout; + uint32_t cmd2csratio; + uint32_t cmd2csforce; + uint32_t cmd2csdelay; + uint32_t cmd2iclkout; +}; + + +/* + * Structure containing shadow of important registers in EMIF + * The calculation function fills in this structure to be later used for + * initialization and DVFS + */ +struct emif_regs { + uint32_t freq; + uint32_t sdram_config_init; + uint32_t sdram_config; + uint32_t sdram_config2; + uint32_t ref_ctrl; + uint32_t ref_ctrl_final; + uint32_t sdram_tim1; + uint32_t sdram_tim2; + uint32_t sdram_tim3; + uint32_t ocp_config; + uint32_t read_idle_ctrl; + uint32_t zq_config; + uint32_t temp_alert_config; + uint32_t emif_ddr_phy_ctlr_1_init; + uint32_t emif_ddr_phy_ctlr_1; + uint32_t emif_ddr_ext_phy_ctrl_1; + uint32_t emif_ddr_ext_phy_ctrl_2; + uint32_t emif_ddr_ext_phy_ctrl_3; + uint32_t emif_ddr_ext_phy_ctrl_4; + uint32_t emif_ddr_ext_phy_ctrl_5; + uint32_t emif_rd_wr_lvl_rmp_win; + uint32_t emif_rd_wr_lvl_rmp_ctl; + uint32_t emif_rd_wr_lvl_ctl; + uint32_t emif_rd_wr_exec_thresh; + uint32_t emif_prio_class_serv_map; + uint32_t emif_connect_id_serv_1_map; + uint32_t emif_connect_id_serv_2_map; + uint32_t emif_cos_config; + uint32_t emif_ecc_ctrl_reg; + uint32_t emif_ecc_address_range_1; + uint32_t emif_ecc_address_range_2; +}; + +/* VTP Registers */ +struct vtp_reg { + uint32_t vtp0ctrlreg; +}; + + +/* Reg mapping structure */ +struct emif_reg_struct { + uint32_t emif_mod_id_rev; + uint32_t emif_status; + uint32_t emif_sdram_config; + uint32_t emif_lpddr2_nvm_config; + uint32_t emif_sdram_ref_ctrl; + uint32_t emif_sdram_ref_ctrl_shdw; + uint32_t emif_sdram_tim_1; + uint32_t emif_sdram_tim_1_shdw; + uint32_t emif_sdram_tim_2; + uint32_t emif_sdram_tim_2_shdw; + uint32_t emif_sdram_tim_3; + uint32_t emif_sdram_tim_3_shdw; + uint32_t emif_lpddr2_nvm_tim; + uint32_t emif_lpddr2_nvm_tim_shdw; + uint32_t emif_pwr_mgmt_ctrl; + uint32_t emif_pwr_mgmt_ctrl_shdw; + uint32_t emif_lpddr2_mode_reg_data; + uint32_t padding1[1]; + uint32_t emif_lpddr2_mode_reg_data_es2; + uint32_t padding11[1]; + uint32_t emif_lpddr2_mode_reg_cfg; + uint32_t emif_l3_config; + uint32_t emif_l3_cfg_val_1; + uint32_t emif_l3_cfg_val_2; + uint32_t emif_iodft_tlgc; + uint32_t padding2[7]; + uint32_t emif_perf_cnt_1; + uint32_t emif_perf_cnt_2; + uint32_t emif_perf_cnt_cfg; + uint32_t emif_perf_cnt_sel; + uint32_t emif_perf_cnt_tim; + uint32_t padding3; + uint32_t emif_read_idlectrl; + uint32_t emif_read_idlectrl_shdw; + uint32_t padding4; + uint32_t emif_irqstatus_raw_sys; + uint32_t emif_irqstatus_raw_ll; + uint32_t emif_irqstatus_sys; + uint32_t emif_irqstatus_ll; + uint32_t emif_irqenable_set_sys; + uint32_t emif_irqenable_set_ll; + uint32_t emif_irqenable_clr_sys; + uint32_t emif_irqenable_clr_ll; + uint32_t padding5; + uint32_t emif_zq_config; + uint32_t emif_temp_alert_config; + uint32_t emif_l3_err_log; + uint32_t emif_rd_wr_lvl_rmp_win; + uint32_t emif_rd_wr_lvl_rmp_ctl; + uint32_t emif_rd_wr_lvl_ctl; + uint32_t padding6[1]; + uint32_t emif_ddr_phy_ctrl_1; + uint32_t emif_ddr_phy_ctrl_1_shdw; + uint32_t emif_ddr_phy_ctrl_2; + uint32_t padding7[4]; + uint32_t emif_prio_class_serv_map; + uint32_t emif_connect_id_serv_1_map; + uint32_t emif_connect_id_serv_2_map; + uint32_t padding8; + uint32_t emif_ecc_ctrl_reg; + uint32_t emif_ecc_address_range_1; + uint32_t emif_ecc_address_range_2; + uint32_t padding8_1; + uint32_t emif_rd_wr_exec_thresh; + uint32_t emif_cos_config; + uint32_t padding9[6]; + uint32_t emif_ddr_phy_status[28]; + uint32_t padding10[20]; + uint32_t emif_ddr_ext_phy_ctrl_1; + uint32_t emif_ddr_ext_phy_ctrl_1_shdw; + uint32_t emif_ddr_ext_phy_ctrl_2; + uint32_t emif_ddr_ext_phy_ctrl_2_shdw; + uint32_t emif_ddr_ext_phy_ctrl_3; + uint32_t emif_ddr_ext_phy_ctrl_3_shdw; + uint32_t emif_ddr_ext_phy_ctrl_4; + uint32_t emif_ddr_ext_phy_ctrl_4_shdw; + uint32_t emif_ddr_ext_phy_ctrl_5; + uint32_t emif_ddr_ext_phy_ctrl_5_shdw; + uint32_t emif_ddr_ext_phy_ctrl_6; + uint32_t emif_ddr_ext_phy_ctrl_6_shdw; + uint32_t emif_ddr_ext_phy_ctrl_7; + uint32_t emif_ddr_ext_phy_ctrl_7_shdw; + uint32_t emif_ddr_ext_phy_ctrl_8; + uint32_t emif_ddr_ext_phy_ctrl_8_shdw; + uint32_t emif_ddr_ext_phy_ctrl_9; + uint32_t emif_ddr_ext_phy_ctrl_9_shdw; + uint32_t emif_ddr_ext_phy_ctrl_10; + uint32_t emif_ddr_ext_phy_ctrl_10_shdw; + uint32_t emif_ddr_ext_phy_ctrl_11; + uint32_t emif_ddr_ext_phy_ctrl_11_shdw; + uint32_t emif_ddr_ext_phy_ctrl_12; + uint32_t emif_ddr_ext_phy_ctrl_12_shdw; + uint32_t emif_ddr_ext_phy_ctrl_13; + uint32_t emif_ddr_ext_phy_ctrl_13_shdw; + uint32_t emif_ddr_ext_phy_ctrl_14; + uint32_t emif_ddr_ext_phy_ctrl_14_shdw; + uint32_t emif_ddr_ext_phy_ctrl_15; + uint32_t emif_ddr_ext_phy_ctrl_15_shdw; + uint32_t emif_ddr_ext_phy_ctrl_16; + uint32_t emif_ddr_ext_phy_ctrl_16_shdw; + uint32_t emif_ddr_ext_phy_ctrl_17; + uint32_t emif_ddr_ext_phy_ctrl_17_shdw; + uint32_t emif_ddr_ext_phy_ctrl_18; + uint32_t emif_ddr_ext_phy_ctrl_18_shdw; + uint32_t emif_ddr_ext_phy_ctrl_19; + uint32_t emif_ddr_ext_phy_ctrl_19_shdw; + uint32_t emif_ddr_ext_phy_ctrl_20; + uint32_t emif_ddr_ext_phy_ctrl_20_shdw; + uint32_t emif_ddr_ext_phy_ctrl_21; + uint32_t emif_ddr_ext_phy_ctrl_21_shdw; + uint32_t emif_ddr_ext_phy_ctrl_22; + uint32_t emif_ddr_ext_phy_ctrl_22_shdw; + uint32_t emif_ddr_ext_phy_ctrl_23; + uint32_t emif_ddr_ext_phy_ctrl_23_shdw; + uint32_t emif_ddr_ext_phy_ctrl_24; + uint32_t emif_ddr_ext_phy_ctrl_24_shdw; + uint32_t emif_ddr_ext_phy_ctrl_25; + uint32_t emif_ddr_ext_phy_ctrl_25_shdw; + uint32_t emif_ddr_ext_phy_ctrl_26; + uint32_t emif_ddr_ext_phy_ctrl_26_shdw; + uint32_t emif_ddr_ext_phy_ctrl_27; + uint32_t emif_ddr_ext_phy_ctrl_27_shdw; + uint32_t emif_ddr_ext_phy_ctrl_28; + uint32_t emif_ddr_ext_phy_ctrl_28_shdw; + uint32_t emif_ddr_ext_phy_ctrl_29; + uint32_t emif_ddr_ext_phy_ctrl_29_shdw; + uint32_t emif_ddr_ext_phy_ctrl_30; + uint32_t emif_ddr_ext_phy_ctrl_30_shdw; + uint32_t emif_ddr_ext_phy_ctrl_31; + uint32_t emif_ddr_ext_phy_ctrl_31_shdw; + uint32_t emif_ddr_ext_phy_ctrl_32; + uint32_t emif_ddr_ext_phy_ctrl_32_shdw; + uint32_t emif_ddr_ext_phy_ctrl_33; + uint32_t emif_ddr_ext_phy_ctrl_33_shdw; + uint32_t emif_ddr_ext_phy_ctrl_34; + uint32_t emif_ddr_ext_phy_ctrl_34_shdw; + uint32_t emif_ddr_ext_phy_ctrl_35; + uint32_t emif_ddr_ext_phy_ctrl_35_shdw; + union { + uint32_t emif_ddr_ext_phy_ctrl_36; + uint32_t emif_ddr_fifo_misaligned_clear_1; + }; + union { + uint32_t emif_ddr_ext_phy_ctrl_36_shdw; + uint32_t emif_ddr_fifo_misaligned_clear_2; + }; +}; + +struct ddr_cmd_regs { + uint32_t resv0[7]; + uint32_t cm0csratio; /* offset 0x01C */ + uint32_t resv1[3]; + uint32_t cm0iclkout; /* offset 0x02C */ + uint32_t resv2[8]; + uint32_t cm1csratio; /* offset 0x050 */ + uint32_t resv3[3]; + uint32_t cm1iclkout; /* offset 0x060 */ + uint32_t resv4[8]; + uint32_t cm2csratio; /* offset 0x084 */ + uint32_t resv5[3]; + uint32_t cm2iclkout; /* offset 0x094 */ + uint32_t resv6[3]; +}; + +struct ddr_data_regs { + uint32_t dt0rdsratio0; /* offset 0x0C8 */ + uint32_t resv1[4]; + uint32_t dt0wdsratio0; /* offset 0x0DC */ + uint32_t resv2[4]; + uint32_t dt0wiratio0; /* offset 0x0F0 */ + uint32_t resv3; + uint32_t dt0wimode0; /* offset 0x0F8 */ + uint32_t dt0giratio0; /* offset 0x0FC */ + uint32_t resv4; + uint32_t dt0gimode0; /* offset 0x104 */ + uint32_t dt0fwsratio0; /* offset 0x108 */ + uint32_t resv5[4]; + uint32_t dt0dqoffset; /* offset 0x11C */ + uint32_t dt0wrsratio0; /* offset 0x120 */ + uint32_t resv6[4]; + uint32_t dt0rdelays0; /* offset 0x134 */ + uint32_t dt0dldiff0; /* offset 0x138 */ + uint32_t resv7[12]; +}; + +/* Control Status Register */ +struct ctrl_stat { + uint32_t resv1[16]; + uint32_t statusreg; /* ofset 0x40 */ + uint32_t resv2[51]; + uint32_t secure_emif_sdram_config; /* offset 0x0110 */ + uint32_t resv3[319]; + uint32_t dev_attr; +}; + +/** + * This structure represents the DDR io control on AM33XX devices. + */ +struct ddr_cmdtctrl { + uint32_t cm0ioctl; + uint32_t cm1ioctl; + uint32_t cm2ioctl; + uint32_t resv2[12]; + uint32_t dt0ioctl; + uint32_t dt1ioctl; + uint32_t dt2ioctrl; + uint32_t dt3ioctrl; + uint32_t resv3[4]; + uint32_t emif_sdram_config_ext; +}; + +struct ddr_ctrl { + uint32_t ddrioctrl; + uint32_t resv1[325]; + uint32_t ddrckectrl; +}; + +/* AM335X EMIF Register values */ +#define VTP_CTRL_READY (0x1 << 5) +#define VTP_CTRL_ENABLE (0x1 << 6) +#define VTP_CTRL_START_EN (0x1) + +#define DDR_CKE_CTRL_NORMAL 0x1 + +#define PHY_EN_DYN_PWRDN (0x1 << 20) + +/* VTP Base address */ +#define VTP0_CTRL_ADDR 0x44E10E0C +#define VTP1_CTRL_ADDR 0x48140E10 + +/* EMIF Base address */ +#define EMIF4_0_CFG_BASE 0x4C000000 +#define EMIF4_1_CFG_BASE 0x4D000000 + +/* DDR Base address */ +#define DDR_PHY_CMD_ADDR 0x44E12000 +#define DDR_PHY_DATA_ADDR 0x44E120C8 +#define DDR_PHY_CMD_ADDR2 0x47C0C800 +#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 +#define DDR_DATA_REGS_NR 2 + +/* DDR Base address */ +#define DDR_CTRL_ADDR 0x44E10E04 +#define DDR_CONTROL_BASE_ADDR 0x44E11404 + +/* Control Module Base Address */ +#define CTRL_BASE 0x44E10000 + +#define EMIF_REG_MAJOR_REVISION_SHIFT 8 +#define EMIF_REG_MAJOR_REVISION_MASK (0x7 << 8) + +#define EMIF_REG_SDRAM_TYPE_SHIFT 29 +#define EMIF_REG_SDRAM_TYPE_MASK (0x7 << 29) + +#define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5 + +#define EMIF_REG_INITREF_DIS_MASK (1 << 31) +#define EMIF_4D5 0x5 + +/* SDRAM TYPE */ +#define EMIF_SDRAM_TYPE_DDR2 0x2 +#define EMIF_SDRAM_TYPE_DDR3 0x3 +#define EMIF_SDRAM_TYPE_LPDDR2 0x4 + +#define PLL_BYPASS_MODE 0x4 +#define ST_MN_BYPASS 0x00000100 +#define ST_DPLL_CLK 0x00000001 +#define CLK_SEL_MASK 0x7ffff +#define CLK_DIV_MASK 0x1f +#define CLK_DIV2_MASK 0x7f +#define CLK_SEL_SHIFT 0x8 +#define CLK_MODE_SEL 0x7 +#define CLK_MODE_MASK 0xfffffff8 +#define CLK_DIV_SEL 0xFFFFFFE0 +#define CPGMAC0_IDLE 0x30000 +#define DPLL_CLKDCOLDO_GATE_CTRL 0x300 + +#define V_OSCK 24000000 /* Clock output from T2 */ +#define OSC (V_OSCK / 1000000) + +#define DDRPLL_M 266 +#define DDRPLL_N (OSC - 1) +#define DDRPLL_M2 1 + +void config_ddr(uint32_t pll, const struct ctrl_ioregs *ioregs, const struct ddr_data *data, + const struct cmd_control *ctrl, const struct emif_regs *regs, int nr); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/44386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1bc2fa606f7010c8c789aa7a5c37cd41bc484b9 Gerrit-Change-Number: 44386 Gerrit-PatchSet: 1 Gerrit-Owner: Sam Lewis <sam.vr.lewis(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: mb/ti/beaglebone: Load romstage/ramstage from SD
by Sam Lewis (Code Review) 30 Mar '21

30 Mar '21

Sam Lewis has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44385 ) Change subject: mb/ti/beaglebone: Load romstage/ramstage from SD ...................................................................... mb/ti/beaglebone: Load romstage/ramstage from SD Adds a "sd_media" boot_device to allow booting from the SD card. This assumes that the generated "MLO" file is placed at a 128KB offset from the start of the SD card, to allow for the MBR etc. to be at the start of the SD card. Placing the MLO file here allows the AM335x boot ROM to load and execute the bootblock stage as well, as 128KB is one of the offsets the boot ROM checks when looking for the next stage to execute. As part of this, a FMD for the Beaglebone has also been defined. It's sized at 32M somewhat arbitrarily, as SD cards could allow for much bigger payloads. TEST: Beaglebone boots from bootblock into romstage. Romstage to ramstage still doesn't work as it needs RAM initialization first. Change-Id: I5f6901217fb974808e84aeb679af2f47eeae30fd Signed-off-by: Sam Lewis <sam.vr.lewis(a)gmail.com> --- M src/mainboard/ti/beaglebone-black/Kconfig M src/mainboard/ti/beaglebone-black/Makefile.inc A src/mainboard/ti/beaglebone-black/board.fmd A src/mainboard/ti/beaglebone-black/sd_media.c M src/soc/ti/am335x/Makefile.inc D src/soc/ti/am335x/bootblock_media.c M src/soc/ti/am335x/header.c M src/soc/ti/am335x/header.h M src/soc/ti/am335x/memlayout.ld D src/soc/ti/am335x/nand.c 10 files changed, 172 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/44385/1 diff --git a/src/mainboard/ti/beaglebone-black/Kconfig b/src/mainboard/ti/beaglebone-black/Kconfig index 5ff844e..a695942 100644 --- a/src/mainboard/ti/beaglebone-black/Kconfig +++ b/src/mainboard/ti/beaglebone-black/Kconfig @@ -5,8 +5,10 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_TI_AM335X - select BOARD_ROMSIZE_KB_4096 + select BOARD_ROMSIZE_KB_32768 select MISSING_BOARD_RESET + select COMMONLIB_STORAGE + select COMMONLIB_STORAGE_SD config MAINBOARD_DIR string @@ -28,4 +30,8 @@ int default 0 +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + endif # BOARD_TI_BEAGLEBONE_BLACK diff --git a/src/mainboard/ti/beaglebone-black/Makefile.inc b/src/mainboard/ti/beaglebone-black/Makefile.inc index a703939..0207a13 100644 --- a/src/mainboard/ti/beaglebone-black/Makefile.inc +++ b/src/mainboard/ti/beaglebone-black/Makefile.inc @@ -2,6 +2,9 @@ bootblock-y += bootblock.c bootblock-y += leds.c -romstage-y += romstage.c +bootblock-y += sd_media.c -#ramstage-y += ramstage.c +romstage-y += romstage.c +romstage-y += sd_media.c + +ramstage-y += sd_media.c diff --git a/src/mainboard/ti/beaglebone-black/board.fmd b/src/mainboard/ti/beaglebone-black/board.fmd new file mode 100644 index 0000000..c0e4281 --- /dev/null +++ b/src/mainboard/ti/beaglebone-black/board.fmd @@ -0,0 +1,10 @@ +SDCARD@0x000 32M { + BIOS@0x0 109K { + BOOTBLOCK@0x0 20K + } + + PAYLOAD { + FMAP 2K + COREBOOT(CBFS) 31M + } +} diff --git a/src/mainboard/ti/beaglebone-black/sd_media.c b/src/mainboard/ti/beaglebone-black/sd_media.c new file mode 100644 index 0000000..7e04f21 --- /dev/null +++ b/src/mainboard/ti/beaglebone-black/sd_media.c @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boot_device.h> +#include <symbols.h> +#include <console/console.h> +#include <assert.h> +#include <commonlib/storage/sd_mmc.h> +#include <cbmem.h> + +#include <soc/ti/am335x/mmc.h> +#include <soc/ti/am335x/header.h> + +// Where the coreboot image is expected to be located on the SD card +// Only certain locations are allowed - check the AM335x technical reference +// manual for more details. +#define COREBOOT_IMAGE_OFFSET (128 * KiB) + +#define SD_BLOCK_SIZE 512 + +static struct am335x_mmc_host sd_host; +static struct storage_media media; + +static size_t partial_block_read(uint8_t *dest, uint64_t block, uint32_t offset, uint32_t count) +{ + static uint8_t overflow_block[SD_BLOCK_SIZE]; + + uint64_t blocks_read = storage_block_read(&media, block, 1, &overflow_block); + + if (blocks_read != 1) { + printk(BIOS_ERR, "Expected to read 1 block but read: %llu\n", blocks_read); + return 0; + } + + assert((offset + count) <= SD_BLOCK_SIZE); + + int dest_index = 0; + for (int overflow_index = offset; overflow_index < (offset + count); overflow_index++) + dest[dest_index++] = overflow_block[overflow_index]; + + return count; +} + +// This supports reads from a SD card that aren't necessarily aligned to the +// sd block size +static ssize_t sd_readat(const struct region_device *rdev, void *dest, size_t offset, + size_t count) +{ + uint8_t *buffer = (uint8_t *)dest; + + uint64_t block_start = offset / SD_BLOCK_SIZE; + uint64_t block_end = (offset + count) / SD_BLOCK_SIZE; + uint64_t blocks = block_end - block_start + 1; + + // Read the last first, which might not be aligned on a SD block + uint32_t first_block_offset = offset % SD_BLOCK_SIZE; + size_t first_block_to_read = MIN(SD_BLOCK_SIZE - first_block_offset, count); + size_t bytes_read = partial_block_read(buffer, block_start, first_block_offset, + first_block_to_read); + + if (blocks == 1) + return bytes_read; + + buffer += bytes_read; + + if (blocks > 2) { + // Read all the "whole" blocks between the start and end blocks + uint64_t to_read = blocks - 2; + uint64_t blocks_read = + storage_block_read(&media, block_start + 1, to_read, (void *)buffer); + + if (blocks_read != to_read) { + printk(BIOS_ERR, "Expecting to read %llu blocks but only read %llu\n", + to_read, blocks_read); + return blocks_read * SD_BLOCK_SIZE; + } + + buffer += to_read * SD_BLOCK_SIZE; + bytes_read += to_read * SD_BLOCK_SIZE; + } + + // Read the last block, which might not be aligned on a SD block + bytes_read += partial_block_read(buffer, block_end, 0, count - bytes_read); + + return bytes_read; +} + +static const struct region_device_ops am335x_sd_ops = { + .mmap = mmap_helper_rdev_mmap, + .munmap = mmap_helper_rdev_munmap, + .readat = sd_readat, +}; + +extern struct omap_image_headers headers; + +static struct mmap_helper_region_device sd_mdev = MMAP_HELPER_REGION_INIT( + &am335x_sd_ops, COREBOOT_IMAGE_OFFSET + sizeof(headers), CONFIG_ROM_SIZE); + +static bool init_done = false; + +void boot_device_init(void) +{ + if (init_done) + return; + + sd_host.sd_clock_hz = 96000000; + sd_host.reg = (void *)MMCHS0_BASE; + am335x_mmc_init_storage(&sd_host); + storage_setup_media(&media, &sd_host.sd_mmc_ctrlr); + storage_display_setup(&media); + + if (ENV_BOOTBLOCK) { + mmap_helper_device_init(&sd_mdev, _cbfs_cache, REGION_SIZE(cbfs_cache)); + } else { + mmap_helper_device_init(&sd_mdev, _postram_cbfs_cache, + REGION_SIZE(postram_cbfs_cache)); + } + + init_done = true; +} + +const struct region_device *boot_device_ro(void) +{ + return &sd_mdev.rdev; +} diff --git a/src/soc/ti/am335x/Makefile.inc b/src/soc/ti/am335x/Makefile.inc index f5ebb7a..990a61e 100644 --- a/src/soc/ti/am335x/Makefile.inc +++ b/src/soc/ti/am335x/Makefile.inc @@ -1,16 +1,16 @@ bootblock-y += bootblock.c -bootblock-y += bootblock_media.c bootblock-y += timer.c bootblock-y += gpio.c bootblock-y += pinmux.c +bootblock-y += mmc.c -romstage-y += nand.c romstage-y += cbmem.c romstage-y += timer.c +romstage-y += mmc.c ramstage-y += timer.c -ramstage-y += nand.c -ramstage-y += soc.c +ramstage-y += soc.c +ramstage-y += mmc.c bootblock-y += uart.c romstage-y += uart.c diff --git a/src/soc/ti/am335x/bootblock_media.c b/src/soc/ti/am335x/bootblock_media.c deleted file mode 100644 index b7e49a6..0000000 --- a/src/soc/ti/am335x/bootblock_media.c +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <boot_device.h> -#include <symbols.h> - -static const struct mem_region_device boot_dev = - MEM_REGION_DEV_RO_INIT(_sram, CONFIG_ROM_SIZE); - -const struct region_device *boot_device_ro(void) -{ - return &boot_dev.rdev; -} diff --git a/src/soc/ti/am335x/header.c b/src/soc/ti/am335x/header.c index c0a7589..f49598b 100644 --- a/src/soc/ti/am335x/header.c +++ b/src/soc/ti/am335x/header.c @@ -5,23 +5,6 @@ #include "header.h" -struct config_headers { - // The table of contents. - struct configuration_header_toc_item toc_chsettings; - struct configuration_header_toc_item toc_end; - - // An inert instance of chsettings. - struct configuration_header_settings chsettings; -} __packed; - -struct omap_image_headers { - union { - struct config_headers config_headers; - uint8_t bytes[512]; - }; - struct gp_device_header image_header; -}; - // A symbol which defines how much of the image the iROM should load. extern char header_load_size; diff --git a/src/soc/ti/am335x/header.h b/src/soc/ti/am335x/header.h index a0a54ad..84e09f3 100644 --- a/src/soc/ti/am335x/header.h +++ b/src/soc/ti/am335x/header.h @@ -47,4 +47,21 @@ uint32_t destination; } __packed; +struct config_headers { + // The table of contents. + struct configuration_header_toc_item toc_chsettings; + struct configuration_header_toc_item toc_end; + + // An inert instance of chsettings. + struct configuration_header_settings chsettings; +} __packed; + +struct omap_image_headers { + union { + struct config_headers config_headers; + uint8_t bytes[512]; + }; + struct gp_device_header image_header; +}; + #endif diff --git a/src/soc/ti/am335x/memlayout.ld b/src/soc/ti/am335x/memlayout.ld index 16770a5..40c0836 100644 --- a/src/soc/ti/am335x/memlayout.ld +++ b/src/soc/ti/am335x/memlayout.ld @@ -12,11 +12,14 @@ TTB(0x402F8000, 16K) ROMSTAGE(0x402F8000+16K, 40K) + PRERAM_CBFS_CACHE(0x402F8000+16K+40K, 20K) + STACK(0x4030be00, 4K) SRAM_END(0x40310000) - DRAM_START(0x80000000) - RAMSTAGE(0x80200000, 192K) + DRAM_START(0x80000000) + RAMSTAGE(0x80000000, 2M) + POSTRAM_CBFS_CACHE(0x80200000, 32M) #ifdef OMAP_HEADER .header : { diff --git a/src/soc/ti/am335x/nand.c b/src/soc/ti/am335x/nand.c deleted file mode 100644 index a7029a0..0000000 --- a/src/soc/ti/am335x/nand.c +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <boot_device.h> - -const struct region_device *boot_device_ro(void) -{ - /* FIXME: add support for reading coreboot from NAND */ - return NULL; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/44385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f6901217fb974808e84aeb679af2f47eeae30fd Gerrit-Change-Number: 44385 Gerrit-PatchSet: 1 Gerrit-Owner: Sam Lewis <sam.vr.lewis(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: soc/ti/am335x: Add MMC/SD driver
by Sam Lewis (Code Review) 30 Mar '21

30 Mar '21

Sam Lewis has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44384 ) Change subject: soc/ti/am335x: Add MMC/SD driver ...................................................................... soc/ti/am335x: Add MMC/SD driver Adds a driver for the am335x MMC peripheral. This has only been tested with SD cards and probably needs some modification to use eMMC or MMC cards. It's also currently a little slow as it only supports reading a block at a time. Change-Id: I5c2b250782cddca17aa46cc8222b9aebef505fb2 Signed-off-by: Sam Lewis <sam.vr.lewis(a)gmail.com> --- A src/soc/ti/am335x/mmc.c A src/soc/ti/am335x/mmc.h 2 files changed, 311 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/44384/1 diff --git a/src/soc/ti/am335x/mmc.c b/src/soc/ti/am335x/mmc.c new file mode 100644 index 0000000..993fe8c --- /dev/null +++ b/src/soc/ti/am335x/mmc.c @@ -0,0 +1,261 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <inttypes.h> +#include <string.h> +#include <console/console.h> +#include <commonlib/sd_mmc_ctrlr.h> +#include <device/mmio.h> +#include "mmc.h" + +#define SYSCONFIG_SOFTRESET (0x1 << 1) + +#define SYSSTATUS_RESETDONE (0x01 << 0) + +#define CON_INIT (0x1 << 1) + +#define CMD_INDEX(x) (x << 24) +#define CMD_RSP_TYPE_NO_RESP (0x0 << 16) +#define CMD_RSP_TYPE_136B (0x1 << 16) +#define CMD_RSP_TYPE_48B (0x2 << 16) +#define CMD_RSP_TYPE_48B_BUSY (0x3 << 16) +#define CMD_DP_DATA (0x1 << 21) +#define CMD_DDIR_READ (0x1 << 4) + +#define HCTL_DTW_1BIT (0x0 << 1) +#define HCTL_SDBP (0x1 << 8) +#define HCTL_SDVS_VS30 (0x6 << 9) + +#define SYSCTL_ICE (0x1 << 0) +#define SYSCTL_ICS (0x1 << 1) +#define SYSCTL_CEN (0x1 << 2) +#define SYSCTL_DTO_15 (0xE << 16) + +#define STAT_ERRI (0x01 << 15) +#define STAT_ERROR_MASK (0xff << 15 | 0x3 << 24 | 0x03 << 28) +#define STAT_CC (0x1 << 0) + +#define IE_CC (0x1 << 0) +#define IE_TC (0x1 << 1) +#define IE_BRR (0x1 << 5) +#define IE_ERRORS (0xff << 15 | 0x3 << 24 | 0x03 << 28) + +#define CAPA_VS18 (0x01 << 26) +#define CAPA_VS30 (0x01 << 25) + +static int am335x_mmc_init(struct am335x_mmc *mmc) +{ + // Follows the initialisiation from the AM335X technical reference manual + setbits32(&mmc->sysconfig, SYSCONFIG_SOFTRESET); + + while (!(read32(&mmc->sysstatus) & SYSSTATUS_RESETDONE)) + ; + + setbits32(&mmc->capa, CAPA_VS30); + setbits32(&mmc->hctl, HCTL_SDVS_VS30 | HCTL_DTW_1BIT); + setbits32(&mmc->hctl, HCTL_SDBP); + + while (!(read32(&mmc->hctl) & HCTL_SDBP)) + ; + + // Assumes the default input clock speed of 96MHz to set a minimum SD + // speed of 400 KHz + write32(&mmc->sysctl, read32(&mmc->sysctl) | 240 << 6 | SYSCTL_DTO_15); + + setbits32(&mmc->sysctl, SYSCTL_ICE | SYSCTL_CEN); + + while (!(read32(&mmc->sysctl) & SYSCTL_ICS)) + ; + + write32(&mmc->ie, IE_ERRORS | IE_TC | IE_CC); + + // Clear interrupts + write32(&mmc->stat, 0xffffffffu); + + setbits32(&mmc->con, CON_INIT); + write32(&mmc->cmd, 0x00); + + while (!(read32(&mmc->stat) & STAT_CC)) + ; + + write32(&mmc->stat, 0xffffffffu); + clrbits32(&mmc->con, CON_INIT); + + return 0; +} + +static int am335x_send_cmd(struct sd_mmc_ctrlr *ctrlr, struct mmc_command *cmd, + struct mmc_data *data) +{ + struct am335x_mmc_host *mmc; + struct am335x_mmc *reg; + + mmc = container_of(ctrlr, struct am335x_mmc_host, sd_mmc_ctrlr); + reg = mmc->reg; + + if (read32(&reg->stat)) { + printk(BIOS_WARNING, "AM335X MMC: Interrupt already raised\n"); + return 1; + } + + uint32_t transfer_type = 0; + + if (data) { + if (data->flags & DATA_FLAG_READ) { + setbits32(&mmc->reg->ie, IE_BRR); + write32(&mmc->reg->blk, data->blocksize); + transfer_type |= CMD_DP_DATA | CMD_DDIR_READ; + } + + if (data->flags & DATA_FLAG_WRITE) { + printk(BIOS_ERR, "AM335X MMC: Writes currently not supported\n"); + return 1; + } + } + + switch (cmd->resp_type) { + case CARD_RSP_R1b: + transfer_type |= CMD_RSP_TYPE_48B_BUSY; + break; + case CARD_RSP_R1: + case CARD_RSP_R3: + transfer_type |= CMD_RSP_TYPE_48B; + break; + case CARD_RSP_R2: + transfer_type |= CMD_RSP_TYPE_136B; + break; + case CARD_RSP_NONE: + transfer_type |= CMD_RSP_TYPE_NO_RESP; + break; + default: + printk(BIOS_ERR, "AM335X MMC: Unknown response type\n"); + return 1; + } + + if (cmd->cmdidx == MMC_CMD_SET_BLOCKLEN) { + // todo: Support bigger blocks for faster transfers + return 0; + } + + write32(&reg->arg, cmd->cmdarg); + write32(&reg->cmd, CMD_INDEX(cmd->cmdidx) | transfer_type); + + // Wait for any interrupt + while (!read32(&reg->stat)) + ; + + // Check to ensure that there was not any errors + if (read32(&reg->stat) & STAT_ERRI) { + printk(BIOS_WARNING, "AM335X MMC: Error while reading %08x\n", + read32(&reg->stat)); + + // Clear the errors + write32(&reg->stat, STAT_ERROR_MASK); + return 1; + } + + if (cmd->resp_type == CARD_RSP_R1b) { + while (!(read32(&reg->stat) & IE_TC)) + ; + write32(&reg->stat, IE_TC); + } + + write32(&reg->stat, IE_CC); + + switch (cmd->resp_type) { + case CARD_RSP_R1: + case CARD_RSP_R1b: + case CARD_RSP_R3: + cmd->response[0] = read32(&reg->rsp10); + break; + case CARD_RSP_R2: + cmd->response[3] = read32(&reg->rsp10); + cmd->response[2] = read32(&reg->rsp32); + cmd->response[1] = read32(&reg->rsp54); + cmd->response[0] = read32(&reg->rsp76); + break; + case CARD_RSP_NONE: + break; + } + + if (data != NULL && data->flags & DATA_FLAG_READ) { + while (!(read32(&reg->stat) & IE_BRR)) + ; + + uint32_t *dest32 = (uint32_t *)data->dest; + + for (int count = 0; count < data->blocksize; count += 4) { + *dest32 = read32(&reg->data); + dest32++; + } + + write32(&reg->stat, IE_TC); + write32(&reg->stat, IE_BRR); + clrbits32(&reg->ie, IE_BRR); + } + + return 0; +} + +static void set_ios(struct sd_mmc_ctrlr *ctrlr) +{ + struct am335x_mmc_host *mmc; + struct am335x_mmc *reg; + + mmc = container_of(ctrlr, struct am335x_mmc_host, sd_mmc_ctrlr); + reg = mmc->reg; + + if (ctrlr->request_hz != ctrlr->bus_hz) { + uint32_t requested_hz = ctrlr->request_hz; + + requested_hz = MIN(requested_hz, ctrlr->f_min); + requested_hz = MAX(requested_hz, ctrlr->f_max); + + uint32_t divisor = mmc->sd_clock_hz / requested_hz; + uint32_t actual = mmc->sd_clock_hz * divisor; + + if (actual != ctrlr->bus_hz) { + clrbits32(&reg->sysctl, SYSCTL_CEN); + + uint32_t new_sysctl = read32(&reg->sysctl); + new_sysctl &= ~(0x3ff << 6); + new_sysctl |= ((divisor & 0x3ff) << 6); + + write32(&reg->sysctl, new_sysctl); + + // Wait for clock stability + while (!(read32(&reg->sysctl) & SYSCTL_ICS)) + ; + + setbits32(&reg->sysctl, SYSCTL_CEN); + + ctrlr->bus_hz = mmc->sd_clock_hz / divisor; + } + } +} + +int am335x_mmc_init_storage(struct am335x_mmc_host *mmc_host) +{ + int err = 0; + + struct sd_mmc_ctrlr *mmc_ctrlr = &mmc_host->sd_mmc_ctrlr; + memset(mmc_ctrlr, 0, sizeof(mmc_ctrlr)); + + + err = am335x_mmc_init(mmc_host->reg); + if (err != 0) { + printk(BIOS_ERR, "ERROR: Initialising AM335X SD failed.\n"); + return err; + } + + mmc_ctrlr->send_cmd = &am335x_send_cmd; + mmc_ctrlr->set_ios = &set_ios; + + mmc_ctrlr->voltages = MMC_VDD_30_31; + mmc_ctrlr->b_max = 1; + mmc_ctrlr->bus_width = 1; + mmc_ctrlr->f_max = 48000000; + mmc_ctrlr->f_min = 400000; + mmc_ctrlr->bus_hz = 400000; + + return 0; +} diff --git a/src/soc/ti/am335x/mmc.h b/src/soc/ti/am335x/mmc.h new file mode 100644 index 0000000..761aa4e --- /dev/null +++ b/src/soc/ti/am335x/mmc.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AM335X_MMC_H +#define AM335X_MMC_H + +#include <inttypes.h> +#include <commonlib/sd_mmc_ctrlr.h> + +#define MMCHS0_BASE 0x48060000 + +struct am335x_mmc { + uint8_t res1[0x110]; + uint32_t sysconfig; + uint32_t sysstatus; + uint8_t res2[0x14]; + uint32_t con; + uint32_t pwcnt; + uint32_t dll; + uint8_t res3[0xcc]; + uint32_t blk; + uint32_t arg; + uint32_t cmd; + uint32_t rsp10; + uint32_t rsp32; + uint32_t rsp54; + uint32_t rsp76; + uint32_t data; + uint32_t pstate; + uint32_t hctl; + uint32_t sysctl; + uint32_t stat; + uint32_t ie; + uint8_t res4[0x4]; + uint32_t ac12; + uint32_t capa; + uint32_t capa2; + uint8_t res5[0xc]; + uint32_t admaes; + uint32_t admasal; +}; + +struct am335x_mmc_host { + struct sd_mmc_ctrlr sd_mmc_ctrlr; + struct am335x_mmc *reg; + uint32_t sd_clock_hz; +}; + +int am335x_mmc_init_storage(struct am335x_mmc_host *mmc_host); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/44384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c2b250782cddca17aa46cc8222b9aebef505fb2 Gerrit-Change-Number: 44384 Gerrit-PatchSet: 1 Gerrit-Owner: Sam Lewis <sam.vr.lewis(a)gmail.com> Gerrit-MessageType: newchange

3 9

Change in ...coreboot[master]: WIP: temp for dispaly conflick
by jitao shi (Code Review) 29 Mar '21

29 Mar '21

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33106 Change subject: WIP: temp for dispaly conflick ...................................................................... WIP: temp for dispaly conflick Temp squlash patches google/krane: Add Panel TV101WUM-NL6 support. google/kukui: Elaborate panel support for Kukui family boards. google/kukui: Enable config for coreboot display mediatek/mt8183: add dsi driver for mt8183 google/kukui: Enable display on internal panel mediatek/mt8183: Add display driver Change-Id: I09d127ab491bca98f3a9c9b7d4ad4b09674c963d --- D 3rdparty/blobs M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/Makefile.inc A src/mainboard/google/kukui/display.c A src/mainboard/google/kukui/display.h M src/mainboard/google/kukui/mainboard.c A src/mainboard/google/kukui/panel_krane.c A src/mainboard/google/kukui/panel_kukui.c M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/ddp.c A src/soc/mediatek/mt8183/dsi.c M src/soc/mediatek/mt8183/include/soc/addressmap.h A src/soc/mediatek/mt8183/include/soc/ddp.h A src/soc/mediatek/mt8183/include/soc/dsi.h 14 files changed, 2,372 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/33106/1 diff --git a/3rdparty/blobs b/3rdparty/blobs deleted file mode 160000 index ca6cfcd..0000000 --- a/3rdparty/blobs +++ /dev/null @@ -1 +0,0 @@ -Subproject commit ca6cfcdbe1cdeb38c2622ee2e5236cc4657e3377 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 6831d1e..5893722 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -37,6 +37,9 @@ select EC_GOOGLE_CHROMEEC_SPI select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT select MAINBOARD_HAS_TPM2 if VBOOT + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_FORCE_NATIVE_VGA_INIT + select HAVE_LINEAR_FRAMEBUFFER config MAINBOARD_DIR string diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index a0556c1..8a023a5 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -22,6 +22,9 @@ ramstage-y += boardid.c ramstage-y += chromeos.c +ramstage-y += display.c +ramstage-$(CONFIG_BOARD_GOOGLE_KUKUI) += panel_kukui.c +ramstage-$(CONFIG_BOARD_GOOGLE_KRANE) += panel_krane.c ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += reset.c diff --git a/src/mainboard/google/kukui/display.c b/src/mainboard/google/kukui/display.c new file mode 100644 index 0000000..c7f7f91 --- /dev/null +++ b/src/mainboard/google/kukui/display.c @@ -0,0 +1,127 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Huaqin Telecom Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <edid.h> +#include <gpio.h> +#include <soc/auxadc.h> +#include <soc/ddp.h> +#include <soc/dsi.h> +#include <soc/gpio.h> +#include <boardid.h> + +#include "display.h" +#include "gpio.h" + +static void _display_startup(struct edid *edid, + struct lcm_init_table *init_table, + u32 init_table_size) +{ + int ret = 0; + u32 mipi_dsi_flags; + + if ((edid == NULL) || (init_table == NULL)) { + printk(BIOS_ERR, "%s: wrong parameters\n", __func__); + return; + } + + mipi_dsi_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_LPM; + + edid_set_framebuffer_bits_per_pixel(edid, 32, 0); + + mtk_ddp_init(); + ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, + false, edid, init_table, init_table_size); + + if (ret < 0) { + printk(BIOS_ERR, "dsi init fail\n"); + return; + } + + mtk_ddp_mode_set(edid); + + set_vbe_mode_info_valid(edid, (uintptr_t)0); +} + +static struct edid *get_edid(struct board_display_intf *intf) +{ + struct panel_info *info = intf->cur_panel_info; + + if (info) + return info->edid; + return NULL; +} + +static struct lcm_init_table *get_panel_init_table(struct board_display_intf + *intf, u32 *table_size) +{ + struct panel_info *info = intf->cur_panel_info; + + if (info) { + *table_size = info->table_size; + return info->init_table; + } + + *table_size = 0; + return NULL; +} + +static const char *get_panel_name(struct board_display_intf *intf) +{ + struct panel_info *info = intf->cur_panel_info; + + if (info) + return info->panel_name; + return NULL; +} + +/* Exported Functions */ + +struct board_display_intf *get_current_display_intf(void) +{ + return &panel_display_intf; +} + +int update_panel_info(struct board_display_intf *intf) +{ + int i; + union panel_id id = intf->get_panel_id(intf); + + if (intf->is_panel_id_valid(id)) { + for (i = 0; i < intf->all_panel_info_size; ++i) { + if (id.value == intf->all_panel_info[i].disp_id.value) { + intf->cur_panel_info = &intf->all_panel_info[i]; + return 0; + } + } + } + return -1; +} + +void display_startup(struct board_display_intf *intf) +{ + struct edid *edid; + u32 init_table_size; + struct lcm_init_table *init_table; + + edid = get_edid(intf); + init_table = get_panel_init_table(intf, &init_table_size); + printk(BIOS_INFO, "%s: name:%s init_table_size:%d\n", + __func__, get_panel_name(intf), init_table_size); + _display_startup(edid, init_table, init_table_size); +} diff --git a/src/mainboard/google/kukui/display.h b/src/mainboard/google/kukui/display.h new file mode 100644 index 0000000..d7b8bd9 --- /dev/null +++ b/src/mainboard/google/kukui/display.h @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Huaqin Telecom Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GOOGLE_DISPLAY_H__ +#define __MAINBOARD_GOOGLE_DISPLAY_H__ + +#include <soc/dsi.h> +#include <soc/gpio.h> + +#define MAKE_AS_A_STRING(arg) #arg + +enum kukui_panel_id { + PANEL_KUKUI_FIRST = 0, + PANEL_KUKUI_INNOLUX = 0, + PANEL_KUKUI_P097PFG_SSD2858, + PANEL_KUKUI_UNKNOWN, + PANEL_KUKUI_COUNT, + PANEL_KUKUI_UNINITIALIZED +}; + +enum krane_panel_id { + PANEL_KRANE_FIRST = 0, + PANEL_KRANE_BOE_TV101WUM_NL6, + PANEL_KRANE_UNKNOWN, + PANEL_KRANE_COUNT, + PANEL_KRANE_UNINITIALIZED +}; + + +union panel_id { + enum kukui_panel_id kukui_panel; + enum krane_panel_id krane_panel; + int value; +}; + +struct panel_info { + union panel_id disp_id; /* the ID for panel */ + const char *panel_name; /* display panel name */ + int voltage; /* voltage of LCM_ID */ + struct edid *edid; /* edid info of this panel */ + struct lcm_init_table *init_table; /* init command table */ + u32 table_size; /* init command table size */ +}; + +#define PANEL(_panel_id, _voltage, _edid, _init_table) \ + { \ + .disp_id = {_panel_id},\ + .panel_name = MAKE_AS_A_STRING(_panel_id),\ + .voltage = _voltage,\ + .edid = &_edid,\ + .init_table = _init_table,\ + .table_size = ARRAY_SIZE(_init_table)} \ + + +struct board_display_intf { + const char *board; /* board name */ + struct panel_info *all_panel_info; /* all supported panel info */ + u32 all_panel_info_size; /* num of supported panel */ + /* + * Runtime member + */ + struct panel_info *cur_panel_info; /* detected panel info */ + /* + * board related functions + */ + + union panel_id (*get_panel_id)(struct board_display_intf *intf); + bool (*is_panel_id_valid)(union panel_id id); + int (*backlight)(struct board_display_intf *intf); + int (*power)(struct board_display_intf *intf); +}; + +/* + * Exported functions + */ + +struct board_display_intf *get_current_display_intf(void); +int update_panel_info(struct board_display_intf *intf); +void display_startup(struct board_display_intf *intf); + + +/* + * Panel Interface for boards + */ +extern struct board_display_intf panel_display_intf; + +#endif diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 7a31909..4e7c20b 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -13,8 +13,17 @@ * GNU General Public License for more details. */ +#include <boardid.h> +#include <bootmode.h> +#include <console/console.h> +#include <delay.h> #include <device/device.h> #include <soc/bl31_plat_params.h> +#include "display.h" +#include <edid.h> +#include <gpio.h> +#include <soc/ddp.h> +#include <soc/dsi.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> #include <soc/mtcmos.h> @@ -70,6 +79,28 @@ static void mainboard_init(struct device *dev) { + struct board_display_intf *cur_disp_intf = NULL; + + if (display_init_required()) { + printk(BIOS_INFO, "Starting display init.\n"); + + cur_disp_intf = get_current_display_intf(); + if (cur_disp_intf && !update_panel_info(cur_disp_intf)) { + mtcmos_display_power_on(); + mtcmos_protect_display_bus(); + + cur_disp_intf->backlight(cur_disp_intf); + cur_disp_intf->power(cur_disp_intf); + display_startup(cur_disp_intf); + } else { + printk(BIOS_ERR, + "%s: Can't find correct display interface\n", + __func__); + } + + } else + printk(BIOS_ERR, "Skipping display init.\n"); + configure_emmc(); configure_usb(); configure_audio(); diff --git a/src/mainboard/google/kukui/panel_krane.c b/src/mainboard/google/kukui/panel_krane.c new file mode 100644 index 0000000..b6fa9a5 --- /dev/null +++ b/src/mainboard/google/kukui/panel_krane.c @@ -0,0 +1,409 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Huaqin Telecom Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <edid.h> +#include <gpio.h> +#include <soc/auxadc.h> +#include <soc/ddp.h> +#include <soc/dsi.h> +#include <soc/gpio.h> +#include <boardid.h> + +#include "display.h" +#include "gpio.h" + +static struct edid krane_boe_tv101wum_nl6_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "1200x1920@60Hz", + .pixel_clock = 159425, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 164, .hso = 100, .hspw = 24, .hborder = 0, + .va = 1920, .vbl = 28, .vso = 10, .vspw = 4, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 135, .y_mm = 216, + }, +}; + +struct lcm_init_table boe_tv101wum_nl6_init_cmd[] = { + {INIT_DCS_CMD, 1, { 0x10 } }, + {DELAY_CMD, 34, {} }, + {INIT_DCS_CMD, 2, { 0xB0, 0x05 } }, + {INIT_DCS_CMD, 2, { 0xB1, 0xE5 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x52 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x88 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x04 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xB6, 0x03 } }, + {INIT_DCS_CMD, 2, { 0xBA, 0x8B } }, + {INIT_DCS_CMD, 2, { 0xBF, 0x1A } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x0F } }, + {INIT_DCS_CMD, 2, { 0xC2, 0x0C } }, + {INIT_DCS_CMD, 2, { 0xC3, 0x02 } }, + {INIT_DCS_CMD, 2, { 0xC4, 0x0C } }, + {INIT_DCS_CMD, 2, { 0xC5, 0x02 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x01 } }, + {INIT_DCS_CMD, 2, { 0xE0, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xE1, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xDC, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xDD, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCC, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xCD, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xC8, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xD2, 0x03 } }, + {INIT_DCS_CMD, 2, { 0xD3, 0x03 } }, + {INIT_DCS_CMD, 2, { 0xE6, 0x04 } }, + {INIT_DCS_CMD, 2, { 0xE7, 0x04 } }, + {INIT_DCS_CMD, 2, { 0xC4, 0x09 } }, + {INIT_DCS_CMD, 2, { 0xC5, 0x09 } }, + {INIT_DCS_CMD, 2, { 0xD8, 0x0A } }, + {INIT_DCS_CMD, 2, { 0xD9, 0x0A } }, + {INIT_DCS_CMD, 2, { 0xC2, 0x0B } }, + {INIT_DCS_CMD, 2, { 0xC3, 0x0B } }, + {INIT_DCS_CMD, 2, { 0xD6, 0x0C } }, + {INIT_DCS_CMD, 2, { 0xD7, 0x0C } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x05 } }, + {INIT_DCS_CMD, 2, { 0xC1, 0x05 } }, + {INIT_DCS_CMD, 2, { 0xD4, 0x06 } }, + {INIT_DCS_CMD, 2, { 0xD5, 0x06 } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x07 } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x07 } }, + {INIT_DCS_CMD, 2, { 0xDE, 0x08 } }, + {INIT_DCS_CMD, 2, { 0xDF, 0x08 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x02 } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xC1, 0x0D } }, + {INIT_DCS_CMD, 2, { 0xC2, 0x17 } }, + {INIT_DCS_CMD, 2, { 0xC3, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xC4, 0x31 } }, + {INIT_DCS_CMD, 2, { 0xC5, 0x1C } }, + {INIT_DCS_CMD, 2, { 0xC6, 0x2C } }, + {INIT_DCS_CMD, 2, { 0xC7, 0x33 } }, + {INIT_DCS_CMD, 2, { 0xC8, 0x31 } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x37 } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x37 } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x37 } }, + {INIT_DCS_CMD, 2, { 0xCC, 0x39 } }, + {INIT_DCS_CMD, 2, { 0xCD, 0x2E } }, + {INIT_DCS_CMD, 2, { 0xCE, 0x2F } }, + {INIT_DCS_CMD, 2, { 0xCF, 0x2F } }, + {INIT_DCS_CMD, 2, { 0xD0, 0x07 } }, + {INIT_DCS_CMD, 2, { 0xD2, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xD3, 0x0D } }, + {INIT_DCS_CMD, 2, { 0xD4, 0x17 } }, + {INIT_DCS_CMD, 2, { 0xD5, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xD6, 0x31 } }, + {INIT_DCS_CMD, 2, { 0xD7, 0x3F } }, + {INIT_DCS_CMD, 2, { 0xD8, 0x3F } }, + {INIT_DCS_CMD, 2, { 0xD9, 0x3F } }, + {INIT_DCS_CMD, 2, { 0xDA, 0x3F } }, + {INIT_DCS_CMD, 2, { 0xDB, 0x37 } }, + {INIT_DCS_CMD, 2, { 0xDC, 0x37 } }, + {INIT_DCS_CMD, 2, { 0xDD, 0x37 } }, + {INIT_DCS_CMD, 2, { 0xDE, 0x39 } }, + {INIT_DCS_CMD, 2, { 0xDF, 0x2E } }, + {INIT_DCS_CMD, 2, { 0xE0, 0x2F } }, + {INIT_DCS_CMD, 2, { 0xE1, 0x2F } }, + {INIT_DCS_CMD, 2, { 0xE2, 0x07 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x03 } }, + {INIT_DCS_CMD, 2, { 0xC8, 0x0B } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x07 } }, + {INIT_DCS_CMD, 2, { 0xC3, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xE7, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xC5, 0x2A } }, + {INIT_DCS_CMD, 2, { 0xDE, 0x2A } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x43 } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x07 } }, + {INIT_DCS_CMD, 2, { 0xE4, 0xC0 } }, + {INIT_DCS_CMD, 2, { 0xE5, 0x0D } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x06 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0xA5 } }, + {INIT_DCS_CMD, 2, { 0xC0, 0xA5 } }, + {INIT_DCS_CMD, 2, { 0xC7, 0x0F } }, + {INIT_DCS_CMD, 2, { 0xD5, 0x32 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xBC, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x07 } }, + {INIT_DCS_CMD, 2, { 0xB1, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xB2, 0x02 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x0F } }, + {INIT_DCS_CMD, 2, { 0xB4, 0x25 } }, + {INIT_DCS_CMD, 2, { 0xB5, 0x39 } }, + {INIT_DCS_CMD, 2, { 0xB6, 0x4E } }, + {INIT_DCS_CMD, 2, { 0xB7, 0x72 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x97 } }, + {INIT_DCS_CMD, 2, { 0xB9, 0xDC } }, + {INIT_DCS_CMD, 2, { 0xBA, 0x22 } }, + {INIT_DCS_CMD, 2, { 0xBB, 0xA4 } }, + {INIT_DCS_CMD, 2, { 0xBC, 0x2B } }, + {INIT_DCS_CMD, 2, { 0xBD, 0x2F } }, + {INIT_DCS_CMD, 2, { 0xBE, 0xA9 } }, + {INIT_DCS_CMD, 2, { 0xBF, 0x25 } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x61 } }, + {INIT_DCS_CMD, 2, { 0xC1, 0x97 } }, + {INIT_DCS_CMD, 2, { 0xC2, 0xB2 } }, + {INIT_DCS_CMD, 2, { 0xC3, 0xCD } }, + {INIT_DCS_CMD, 2, { 0xC4, 0xD9 } }, + {INIT_DCS_CMD, 2, { 0xC5, 0xE7 } }, + {INIT_DCS_CMD, 2, { 0xC6, 0xF4 } }, + {INIT_DCS_CMD, 2, { 0xC7, 0xFA } }, + {INIT_DCS_CMD, 2, { 0xC8, 0xFC } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x16 } }, + {INIT_DCS_CMD, 2, { 0xCC, 0xAF } }, + {INIT_DCS_CMD, 2, { 0xCD, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xCE, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x08 } }, + {INIT_DCS_CMD, 2, { 0xB1, 0x04 } }, + {INIT_DCS_CMD, 2, { 0xB2, 0x05 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x11 } }, + {INIT_DCS_CMD, 2, { 0xB4, 0x24 } }, + {INIT_DCS_CMD, 2, { 0xB5, 0x39 } }, + {INIT_DCS_CMD, 2, { 0xB6, 0x4F } }, + {INIT_DCS_CMD, 2, { 0xB7, 0x72 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x98 } }, + {INIT_DCS_CMD, 2, { 0xB9, 0xDC } }, + {INIT_DCS_CMD, 2, { 0xBA, 0x23 } }, + {INIT_DCS_CMD, 2, { 0xBB, 0xA6 } }, + {INIT_DCS_CMD, 2, { 0xBC, 0x2C } }, + {INIT_DCS_CMD, 2, { 0xBD, 0x30 } }, + {INIT_DCS_CMD, 2, { 0xBE, 0xAA } }, + {INIT_DCS_CMD, 2, { 0xBF, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x62 } }, + {INIT_DCS_CMD, 2, { 0xC1, 0x9B } }, + {INIT_DCS_CMD, 2, { 0xC2, 0xB5 } }, + {INIT_DCS_CMD, 2, { 0xC3, 0xCF } }, + {INIT_DCS_CMD, 2, { 0xC4, 0xDB } }, + {INIT_DCS_CMD, 2, { 0xC5, 0xE8 } }, + {INIT_DCS_CMD, 2, { 0xC6, 0xF5 } }, + {INIT_DCS_CMD, 2, { 0xC7, 0xFA } }, + {INIT_DCS_CMD, 2, { 0xC8, 0xFC } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x16 } }, + {INIT_DCS_CMD, 2, { 0xCC, 0xAF } }, + {INIT_DCS_CMD, 2, { 0xCD, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xCE, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x09 } }, + {INIT_DCS_CMD, 2, { 0xB1, 0x04 } }, + {INIT_DCS_CMD, 2, { 0xB2, 0x02 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x16 } }, + {INIT_DCS_CMD, 2, { 0xB4, 0x24 } }, + {INIT_DCS_CMD, 2, { 0xB5, 0x3B } }, + {INIT_DCS_CMD, 2, { 0xB6, 0x4F } }, + {INIT_DCS_CMD, 2, { 0xB7, 0x73 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x99 } }, + {INIT_DCS_CMD, 2, { 0xB9, 0xE0 } }, + {INIT_DCS_CMD, 2, { 0xBA, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xBB, 0xAD } }, + {INIT_DCS_CMD, 2, { 0xBC, 0x36 } }, + {INIT_DCS_CMD, 2, { 0xBD, 0x3A } }, + {INIT_DCS_CMD, 2, { 0xBE, 0xAE } }, + {INIT_DCS_CMD, 2, { 0xBF, 0x2A } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x66 } }, + {INIT_DCS_CMD, 2, { 0xC1, 0x9E } }, + {INIT_DCS_CMD, 2, { 0xC2, 0xB8 } }, + {INIT_DCS_CMD, 2, { 0xC3, 0xD1 } }, + {INIT_DCS_CMD, 2, { 0xC4, 0xDD } }, + {INIT_DCS_CMD, 2, { 0xC5, 0xE9 } }, + {INIT_DCS_CMD, 2, { 0xC6, 0xF6 } }, + {INIT_DCS_CMD, 2, { 0xC7, 0xFA } }, + {INIT_DCS_CMD, 2, { 0xC8, 0xFC } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x16 } }, + {INIT_DCS_CMD, 2, { 0xCC, 0xAF } }, + {INIT_DCS_CMD, 2, { 0xCD, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xCE, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x0A } }, + {INIT_DCS_CMD, 2, { 0xB1, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xB2, 0x02 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x0F } }, + {INIT_DCS_CMD, 2, { 0xB4, 0x25 } }, + {INIT_DCS_CMD, 2, { 0xB5, 0x39 } }, + {INIT_DCS_CMD, 2, { 0xB6, 0x4E } }, + {INIT_DCS_CMD, 2, { 0xB7, 0x72 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x97 } }, + {INIT_DCS_CMD, 2, { 0xB9, 0xDC } }, + {INIT_DCS_CMD, 2, { 0xBA, 0x22 } }, + {INIT_DCS_CMD, 2, { 0xBB, 0xA4 } }, + {INIT_DCS_CMD, 2, { 0xBC, 0x2B } }, + {INIT_DCS_CMD, 2, { 0xBD, 0x2F } }, + {INIT_DCS_CMD, 2, { 0xBE, 0xA9 } }, + {INIT_DCS_CMD, 2, { 0xBF, 0x25 } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x61 } }, + {INIT_DCS_CMD, 2, { 0xC1, 0x97 } }, + {INIT_DCS_CMD, 2, { 0xC2, 0xB2 } }, + {INIT_DCS_CMD, 2, { 0xC3, 0xCD } }, + {INIT_DCS_CMD, 2, { 0xC4, 0xD9 } }, + {INIT_DCS_CMD, 2, { 0xC5, 0xE7 } }, + {INIT_DCS_CMD, 2, { 0xC6, 0xF4 } }, + {INIT_DCS_CMD, 2, { 0xC7, 0xFA } }, + {INIT_DCS_CMD, 2, { 0xC8, 0xFC } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x16 } }, + {INIT_DCS_CMD, 2, { 0xCC, 0xAF } }, + {INIT_DCS_CMD, 2, { 0xCD, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xCE, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x0B } }, + {INIT_DCS_CMD, 2, { 0xB1, 0x04 } }, + {INIT_DCS_CMD, 2, { 0xB2, 0x05 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x11 } }, + {INIT_DCS_CMD, 2, { 0xB4, 0x24 } }, + {INIT_DCS_CMD, 2, { 0xB5, 0x39 } }, + {INIT_DCS_CMD, 2, { 0xB6, 0x4F } }, + {INIT_DCS_CMD, 2, { 0xB7, 0x72 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x98 } }, + {INIT_DCS_CMD, 2, { 0xB9, 0xDC } }, + {INIT_DCS_CMD, 2, { 0xBA, 0x23 } }, + {INIT_DCS_CMD, 2, { 0xBB, 0xA6 } }, + {INIT_DCS_CMD, 2, { 0xBC, 0x2C } }, + {INIT_DCS_CMD, 2, { 0xBD, 0x30 } }, + {INIT_DCS_CMD, 2, { 0xBE, 0xAA } }, + {INIT_DCS_CMD, 2, { 0xBF, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x62 } }, + {INIT_DCS_CMD, 2, { 0xC1, 0x9B } }, + {INIT_DCS_CMD, 2, { 0xC2, 0xB5 } }, + {INIT_DCS_CMD, 2, { 0xC3, 0xCF } }, + {INIT_DCS_CMD, 2, { 0xC4, 0xDB } }, + {INIT_DCS_CMD, 2, { 0xC5, 0xE8 } }, + {INIT_DCS_CMD, 2, { 0xC6, 0xF5 } }, + {INIT_DCS_CMD, 2, { 0xC7, 0xFA } }, + {INIT_DCS_CMD, 2, { 0xC8, 0xFC } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x16 } }, + {INIT_DCS_CMD, 2, { 0xCC, 0xAF } }, + {INIT_DCS_CMD, 2, { 0xCD, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xCE, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x0C } }, + {INIT_DCS_CMD, 2, { 0xB1, 0x04 } }, + {INIT_DCS_CMD, 2, { 0xB2, 0x02 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x16 } }, + {INIT_DCS_CMD, 2, { 0xB4, 0x24 } }, + {INIT_DCS_CMD, 2, { 0xB5, 0x3B } }, + {INIT_DCS_CMD, 2, { 0xB6, 0x4F } }, + {INIT_DCS_CMD, 2, { 0xB7, 0x73 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x99 } }, + {INIT_DCS_CMD, 2, { 0xB9, 0xE0 } }, + {INIT_DCS_CMD, 2, { 0xBA, 0x26 } }, + {INIT_DCS_CMD, 2, { 0xBB, 0xAD } }, + {INIT_DCS_CMD, 2, { 0xBC, 0x36 } }, + {INIT_DCS_CMD, 2, { 0xBD, 0x3A } }, + {INIT_DCS_CMD, 2, { 0xBE, 0xAE } }, + {INIT_DCS_CMD, 2, { 0xBF, 0x2A } }, + {INIT_DCS_CMD, 2, { 0xC0, 0x66 } }, + {INIT_DCS_CMD, 2, { 0xC1, 0x9E } }, + {INIT_DCS_CMD, 2, { 0xC2, 0xB8 } }, + {INIT_DCS_CMD, 2, { 0xC3, 0xD1 } }, + {INIT_DCS_CMD, 2, { 0xC4, 0xDD } }, + {INIT_DCS_CMD, 2, { 0xC5, 0xE9 } }, + {INIT_DCS_CMD, 2, { 0xC6, 0xF6 } }, + {INIT_DCS_CMD, 2, { 0xC7, 0xFA } }, + {INIT_DCS_CMD, 2, { 0xC8, 0xFC } }, + {INIT_DCS_CMD, 2, { 0xC9, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCA, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xCB, 0x16 } }, + {INIT_DCS_CMD, 2, { 0xCC, 0xAF } }, + {INIT_DCS_CMD, 2, { 0xCD, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xCE, 0xFF } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x00 } }, + {INIT_DCS_CMD, 2, { 0xB3, 0x08 } }, + {INIT_DCS_CMD, 2, { 0xB0, 0x04 } }, + {INIT_DCS_CMD, 2, { 0xB8, 0x68 } }, + {DELAY_CMD, 10, {} }, + {INIT_DCS_CMD, 1, { 0x11 } }, + {DELAY_CMD, 120, {} }, + {INIT_DCS_CMD, 1, { 0x29 } }, + {DELAY_CMD, 20, {} }, + +}; + +struct panel_info krane_panel_info[] = { + PANEL(PANEL_KRANE_BOE_TV101WUM_NL6, + 74000, + krane_boe_tv101wum_nl6_edid, + boe_tv101wum_nl6_init_cmd), + {{PANEL_KRANE_UNKNOWN}, "PANEL_KRANE_UNKNOWN", + 0, NULL, NULL, 0}, +}; + +static union panel_id krane_get_panel_id(struct board_display_intf *intf) +{ + return (union panel_id)PANEL_KRANE_BOE_TV101WUM_NL6; +}; + +static bool krane_is_panel_id_valid(union panel_id id) +{ + if (id.value < PANEL_KRANE_UNKNOWN) + return true; + return false; +}; + +static int krane_backlight(struct board_display_intf *intf) +{ + gpio_output(GPIO(PERIPHERAL_EN13), 1); + gpio_output(GPIO(DISP_PWM), 1); /* DISP_PWM0 */ + + return 0; +}; + +static int krane_power(struct board_display_intf *intf) +{ + if (board_id() < 2) { + /* board from p1 */ + gpio_output(GPIO(LCM_RST), 0); + udelay(100); + gpio_output(GPIO(LCM_RST), 1); + mdelay(20); + } else { + /* board from p2 */ + gpio_output(GPIO(LCM_RST), 0); + udelay(1500); + gpio_output(GPIO(SIM2_SRST), 1); + mdelay(5); + gpio_output(GPIO(PERIPHERAL_EN9), 1); + gpio_output(GPIO(MISC_BSI_CK_3), 1); + mdelay(100); + gpio_output(GPIO(LCM_RST), 1); + mdelay(10); + } + + return 0; + +}; + +struct board_display_intf panel_display_intf = { + .board = "krane", + .all_panel_info = krane_panel_info, + .all_panel_info_size = ARRAY_SIZE(krane_panel_info), + .cur_panel_info = NULL, + .get_panel_id = &krane_get_panel_id, + .is_panel_id_valid = &krane_is_panel_id_valid, + .backlight = &krane_backlight, + .power = &krane_power, +}; diff --git a/src/mainboard/google/kukui/panel_kukui.c b/src/mainboard/google/kukui/panel_kukui.c new file mode 100644 index 0000000..be76aa4 --- /dev/null +++ b/src/mainboard/google/kukui/panel_kukui.c @@ -0,0 +1,194 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Huaqin Telecom Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <edid.h> +#include <gpio.h> +#include <soc/auxadc.h> +#include <soc/ddp.h> +#include <soc/dsi.h> +#include <soc/gpio.h> +#include <boardid.h> + +#include "display.h" +#include "gpio.h" + +static struct edid kukui_innolux_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "768x1024@60Hz", + .pixel_clock = 56900, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 768, .hbl = 120, .hso = 40, .hspw = 40, .hborder = 0, + .va = 1024, .vbl = 44, .vso = 20, .vspw = 4, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 120, .y_mm = 160, + }, +}; + +static struct lcm_init_table lcm_init_cmd[] = { + {INIT_DCS_CMD, 1, {MIPI_DCS_EXIT_SLEEP_MODE} }, + {DELAY_CMD, 120, {} }, + {INIT_DCS_CMD, 1, {MIPI_DCS_SET_DISPLAY_ON} }, + {DELAY_CMD, 120, {} }, +}; + +static struct edid kukui_p097pfg_ssd2858_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "1536x2048@60Hz", + .pixel_clock = 211660, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1536, .hbl = 160, .hso = 140, .hspw = 10, .hborder = 0, + .va = 2048, .vbl = 32, .vso = 20, .vspw = 2, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 147, .y_mm = 196, + }, +}; + +struct lcm_init_table lcm_p097pfg_ssd2858_init_cmd[] = { + /* SSD2858 config */ + {INIT_GENENIC_CMD, 2, {0xff, 0x00} }, + /* LOCKCNT=0x1f4, MRX=0, POSTDIV=1 (/2} }, MULT=0x49 + * 27 Mhz => 985.5 Mhz + */ + {INIT_GENENIC_CMD, 6, {0x00, 0x08, 0x01, 0xf4, 0x01, 0x49} }, + /* MTXDIV=1, SYSDIV=3 (=> 4) */ + {INIT_GENENIC_CMD, 6, {0x00, 0x0c, 0x00, 0x00, 0x00, 0x03} }, + /* MTXVPF=24bpp, MRXLS=4 lanes, MRXVB=bypass, MRXECC=1, MRXEOT=1 + * MRXEE=1 + */ + {INIT_GENENIC_CMD, 6, {0x00, 0x14, 0x0c, 0x3d, 0x80, 0x0f} }, + {INIT_GENENIC_CMD, 6, {0x00, 0x20, 0x15, 0x92, 0x56, 0x7d} }, + {INIT_GENENIC_CMD, 6, {0x00, 0x24, 0x00, 0x00, 0x30, 0x00} }, + + {INIT_GENENIC_CMD, 6, {0x10, 0x08, 0x01, 0x20, 0x08, 0x45} }, + {INIT_GENENIC_CMD, 6, {0x10, 0x1c, 0x00, 0x00, 0x00, 0x00} }, + {INIT_GENENIC_CMD, 6, {0x20, 0x0c, 0x00, 0x00, 0x00, 0x04} }, + /* Pixel clock 985.5 Mhz * 0x49/0x4b = 959 Mhz */ + {INIT_GENENIC_CMD, 6, {0x20, 0x10, 0x00, 0x4b, 0x00, 0x49} }, + {INIT_GENENIC_CMD, 6, {0x20, 0xa0, 0x00, 0x00, 0x00, 0x00} }, + /* EOT=1, LPE = 0, LSOUT=4 lanes, LPD=25 */ + {INIT_GENENIC_CMD, 6, {0x60, 0x08, 0x00, 0xd9, 0x00, 0x08} }, + {INIT_GENENIC_CMD, 6, {0x60, 0x14, 0x01, 0x00, 0x01, 0x06} }, + /* DSI0 enable (default: probably not needed) */ + {INIT_GENENIC_CMD, 6, {0x60, 0x80, 0x00, 0x00, 0x00, 0x0f} }, + /* DSI1 enable */ + {INIT_GENENIC_CMD, 6, {0x60, 0xa0, 0x00, 0x00, 0x00, 0x0f} }, + + /* HSA=0x18, VSA=0x02, HBP=0x50, VBP=0x0c */ + {INIT_GENENIC_CMD, 6, {0x60, 0x0c, 0x0c, 0x50, 0x02, 0x18} }, + /* VACT= 0x800 (2048} }, VFP= 0x14, HFP=0x50 */ + {INIT_GENENIC_CMD, 6, {0x60, 0x10, 0x08, 0x00, 0x14, 0x50} }, + /* HACT=0x300 (768) */ + {INIT_GENENIC_CMD, 6, {0x60, 0x84, 0x00, 0x00, 0x03, 0x00} }, + {INIT_GENENIC_CMD, 6, {0x60, 0xa4, 0x00, 0x00, 0x03, 0x00} }, + + /* Take panel out of sleep. */ + {INIT_GENENIC_CMD, 2, {0xff, 0x01} }, + {INIT_DCS_CMD, 1, {0x11} }, + {DELAY_CMD, 120, {} }, + {INIT_DCS_CMD, 1, {0x29} }, + {DELAY_CMD, 20, {} }, + {INIT_GENENIC_CMD, 2, {0xff, 0x00} }, + + {DELAY_CMD, 120, {} }, + {INIT_DCS_CMD, 1, {0x11} }, + {DELAY_CMD, 120, {} }, + {INIT_DCS_CMD, 1, {0x29} }, + {DELAY_CMD, 20, {} }, +}; + +struct panel_info kukui_panel_info[] = { + PANEL(PANEL_KUKUI_INNOLUX, + 74000, + kukui_innolux_edid, + lcm_init_cmd), + PANEL(PANEL_KUKUI_P097PFG_SSD2858, + 212000, + kukui_p097pfg_ssd2858_edid, + lcm_p097pfg_ssd2858_init_cmd), + {{PANEL_KUKUI_UNKNOWN}, "PANEL_KUKUI_UNKNOWN", + 0, NULL, NULL, 0}, +}; + +static union panel_id kukui_get_panel_id(struct board_display_intf *intf) +{ + if (board_id() < 2) + return (union panel_id)PANEL_KUKUI_INNOLUX; + else + return (union panel_id)PANEL_KUKUI_P097PFG_SSD2858; +}; + +static bool kukui_is_panel_id_valid(union panel_id id) +{ + if (id.value < PANEL_KUKUI_UNKNOWN) + return true; + return false; +}; + +static int kukui_backlight(struct board_display_intf *intf) +{ + gpio_output(GPIO(PERIPHERAL_EN13), 1); + gpio_output(GPIO(DISP_PWM), 1); /* DISP_PWM0 */ + + return 0; +}; + +static int kukui_power(struct board_display_intf *intf) +{ + if (board_id() < 2) { + /* board from p1 */ + gpio_output(GPIO(LCM_RST), 0); + udelay(100); + gpio_output(GPIO(LCM_RST), 1); + mdelay(20); + } else { + /* board from p2 */ + gpio_output(GPIO(LCM_RST), 0); + gpio_output(GPIO(BPI_BUS3), 0); + gpio_output(GPIO(MISC_BSI_CK_3), 1); + gpio_output(GPIO(PERIPHERAL_EN9), 1); + gpio_output(GPIO(SIM2_SRST), 1); + gpio_output(GPIO(SIM2_SIO), 1); + gpio_output(GPIO(BPI_OLAT1), 1); + gpio_output(GPIO(SIM2_SCLK), 1); + mdelay(20); + gpio_output(GPIO(LCM_RST), 1); + mdelay(20); + gpio_output(GPIO(BPI_BUS3), 1); + mdelay(20); + } + + return 0; + +}; + +struct board_display_intf panel_display_intf = { + .board = "kukui", + .all_panel_info = kukui_panel_info, + .all_panel_info_size = ARRAY_SIZE(kukui_panel_info), + .cur_panel_info = NULL, + .get_panel_id = &kukui_get_panel_id, + .is_panel_id_valid = &kukui_is_panel_id_valid, + .backlight = &kukui_backlight, + .power = &kukui_power, +}; diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index ce498c1..0afa335 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -42,6 +42,8 @@ ramstage-y += auxadc.c ramstage-y += ../common/cbmem.c emi.c +ramstage-y += ddp.c +ramstage-y += dsi.c ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c new file mode 100644 index 0000000..d845981 --- /dev/null +++ b/src/soc/mediatek/mt8183/ddp.c @@ -0,0 +1,202 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <edid.h> +#include <stdlib.h> +#include <string.h> +#include <stddef.h> +#include <soc/addressmap.h> +#include <soc/ddp.h> + +#define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) +#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) + +static void disp_config_main_path_connection(void) +{ + write32(&mmsys_cfg->disp_ovl0_mout_en, OVL0_MOUT_EN_OVL0_2L); + write32(&mmsys_cfg->disp_ovl0_2l_mout_en, OVL0_2L_MOUT_EN_DISP_PATH0); + write32(&mmsys_cfg->disp_path0_sel_in, DISP_PATH0_SEL_IN_OVL0_2L); + write32(&mmsys_cfg->disp_rdma0_sout_sel_in, RDMA0_SOUT_SEL_IN_COLOR); + write32(&mmsys_cfg->disp_dither0_mout_en, DITHER0_MOUT_EN_DISP_DSI0); + write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_DITHER0_MOUT); +} + +static void disp_config_main_path_mutex(void) +{ + write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH); + + /* Clock source from DSI0 */ + write32(&disp_mutex->mutex[0].ctl, + MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 6)); + write32(&disp_mutex->mutex[0].en, BIT(0)); +} + +static void ovl_set_roi(u32 idx, u32 width, u32 height, u32 color) +{ + write32(&disp_ovl[idx]->roi_size, height << 16 | width); + write32(&disp_ovl[idx]->roi_bgclr, color); +} + +static void ovl_layer_enable(u32 idx) +{ + write32(&disp_ovl[idx]->rdma[0].ctrl, BIT(0)); + write32(&disp_ovl[idx]->rdma[0].mem_gmc_setting, RDMA_MEM_GMC); + + setbits_le32(&disp_ovl[idx]->src_con, BIT(0)); +} + +static void ovl_bgclr_in_sel(u32 idx) +{ + setbits_le32(&disp_ovl[idx]->datapath_con, BIT(2)); +} + +static void rdma_start(u32 idx) +{ + setbits_le32(&disp_rdma[idx]->global_con, RDMA_ENGINE_EN); +} + +static void rdma_config(u32 idx, u32 width, u32 height, u32 vrefresh) +{ + u32 threshold; + u32 reg; + u32 fifo_size; + + clrsetbits_le32(&disp_rdma[idx]->size_con_0, 0x1FFF, width); + clrsetbits_le32(&disp_rdma[idx]->size_con_1, 0xFFFFF, height); + + /* + * Enable FIFO underflow since DSI and DPI can't be blocked. Keep the + * FIFO pseudo size reset default of 8 KiB. Set the output threshold to + * 6 microseconds with 7/6 overhead to account for blanking, and with a + * pixel depth of 4 bytes: + */ + fifo_size = RDMA_FIFO_SIZE_0 * KiB; + + threshold = width * height * vrefresh * 4 * 7 / 1000000; + + if (threshold > fifo_size) + threshold = fifo_size; + + reg = RDMA_FIFO_UNDERFLOW_EN | + RDMA_FIFO_PSEUDO_SIZE(fifo_size) | + RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); + + write32(&disp_rdma[idx]->fifo_con, reg); +} + +static void color_start(u32 width, u32 height) +{ + write32(&disp_color->width, width); + write32(&disp_color->height, height); + write32(&disp_color->cfg_main, COLOR_BYPASS_ALL | COLOR_SEQ_SEL); + write32(&disp_color->start, BIT(0)); +} + +static void aal_start(u32 width, u32 height) +{ + write32(&disp_aal->size, height << 16 | width); + write32(&disp_aal->en, PQ_EN); +} + +static void ccorr_start(u32 width, u32 height) +{ + write32(&disp_ccorr->size, height << 16 | width); + write32(&disp_ccorr->cfg, PQ_RELAY_MODE); + write32(&disp_ccorr->en, PQ_EN); +} + +static void dither_start(u32 width, u32 height) +{ + write32(&disp_dither->size, height << 16 | width); + write32(&disp_dither->cfg, PQ_RELAY_MODE); + write32(&disp_dither->en, PQ_EN); +} + +static void gamma_start(u32 width, u32 height) +{ + write32(&disp_gamma->size, height << 16 | width); + write32(&disp_gamma->en, PQ_EN); +} + +static void ovl_layer_config(u32 idx, u32 fmt, u32 bpp, u32 width, u32 height) +{ + write32(&disp_ovl[idx]->layer[0].con, fmt << 12); + write32(&disp_ovl[idx]->layer[0].src_size, height << 16 | width); + write32(&disp_ovl[idx]->layer[0].pitch, (width * bpp) & 0xFFFF); + + ovl_layer_enable(idx); +} + +static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh) +{ + u32 idx = 0; + + /* Setup OVL */ + for (idx = 0; idx < MAIN_PATH_OVL_NR; idx++) { + u32 color = 0; + + if (idx == 0) + color = 0xFF0000FF; + + ovl_set_roi(idx, width, height, color); + } + + idx = 0; + rdma_config(idx, width, height, vrefresh); + color_start(width, height); + ccorr_start(width, height); + aal_start(width, height); + gamma_start(width, height); + dither_start(width, height); + disp_config_main_path_connection(); + disp_config_main_path_mutex(); +} + +static void disp_clock_on(void) +{ + clrbits_le32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL); + + clrbits_le32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_DSI0 | + CG_CON1_DISP_DSI0_INTERFACE); +} + +static void disp_m4u_port_off(void) +{ + write32((void *)(SMI_LARB0 + SMI_LARB_NON_SEC_CON), 0); +} + +void mtk_ddp_init(void) +{ + disp_clock_on(); + disp_m4u_port_off(); +} + +void mtk_ddp_mode_set(const struct edid *edid) +{ + u32 fmt = OVL_INFMT_RGBA8888; + u32 bpp = edid->framebuffer_bits_per_pixel / 8; + u32 idx = 0; + u32 width = edid->mode.ha; + u32 height = edid->mode.va; + u32 vrefresh = edid->mode.refresh; + + main_disp_path_setup(width, height, vrefresh); + rdma_start(idx); + ovl_layer_config(idx, fmt, bpp, width, height); + ovl_bgclr_in_sel(idx+1); +} diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c new file mode 100644 index 0000000..3bfada7 --- /dev/null +++ b/src/soc/mediatek/mt8183/dsi.c @@ -0,0 +1,485 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/mmio.h> +#include <console/console.h> +#include <delay.h> +#include <soc/addressmap.h> +#include <soc/dsi.h> +#include <timer.h> + +static void dsi_write32(void *a, uint32_t v) +{ + write32(a, v); +} + +static void dsi_clrsetbits_le32(void *a, uint32_t m, uint32_t v) +{ + clrsetbits_le32(a, m, v); +} + +static void dsi_clrbits_le32(void *a, uint32_t m) +{ + clrbits_le32(a, m); +} + +static void dsi_setbits_le32(void *a, uint32_t m) +{ + setbits_le32(a, m); +} + +static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes, + const struct edid *edid) +{ + unsigned int txdiv, txdiv0, txdiv1; + u64 pcw; + int data_rate; + u32 bpp; + + switch (format) { + case MIPI_DSI_FMT_RGB565: + bpp = 16; + break; + case MIPI_DSI_FMT_RGB666: + case MIPI_DSI_FMT_RGB666_PACKED: + bpp = 18; + break; + case MIPI_DSI_FMT_RGB888: + default: + bpp = 24; + break; + } + + data_rate = (u64)(edid->mode.pixel_clock * 1000 * bpp) / lanes; + + printk(BIOS_INFO, "data_rate: %u bps\n", data_rate); + + if (data_rate >= 2000000000) { + txdiv = 1; + txdiv0 = 0; + txdiv1 = 0; + } else if (data_rate >= 1000000000) { + txdiv = 2; + txdiv0 = 1; + txdiv1 = 0; + } else if (data_rate >= 500000000) { + txdiv = 4; + txdiv0 = 2; + txdiv1 = 0; + } else if (data_rate > 250000000) { + txdiv = 8; + txdiv0 = 3; + txdiv1 = 0; + } else if (data_rate >= 125000000) { + txdiv = 16; + txdiv0 = 4; + txdiv1 = 0; + } else { + printk(BIOS_ERR, "data rate (%u) must be >=50. Please check " + "pixel clock (%u), bpp (%u), number of lanes (%u)\n", + data_rate, edid->mode.pixel_clock, bpp, + lanes); + return -1; + } + + dsi_clrbits_le32(mipi_tx + MIPITX_PLL_CON4, BIT(11) | BIT(10)); + + dsi_setbits_le32(mipi_tx + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON); + udelay(30); + dsi_clrbits_le32(mipi_tx + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN); + + pcw = (u64)((data_rate / 1000000) * (1 << txdiv0) * (1 << txdiv1)); + pcw <<= 24; + pcw /= 26; + + dsi_write32(mipi_tx + MIPITX_PLL_CON0, pcw); + dsi_clrsetbits_le32(mipi_tx + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, + txdiv0 << 8); + udelay(30); + dsi_setbits_le32(mipi_tx + MIPITX_PLL_CON1, RG_DSI_PLL_EN); + + /* BG_LPF_EN / BG_CORE_EN */ + dsi_write32(mipi_tx + MIPITX_LANE_CON, 0x3FFF0180); + udelay(40); + dsi_write32(mipi_tx + MIPITX_LANE_CON, 0x3FFF00c0); + + /* Switch OFF each Lane */ + dsi_clrbits_le32(mipi_tx + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN); + dsi_clrbits_le32(mipi_tx + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN); + dsi_clrbits_le32(mipi_tx + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN); + dsi_clrbits_le32(mipi_tx + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN); + dsi_clrbits_le32(mipi_tx + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN); + + dsi_setbits_le32(mipi_tx + MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN); + + return data_rate; +} + +static void mtk_dsi_phy_timconfig(u32 data_rate, + struct mtk_phy_timing *phy_timing) +{ + u32 timcon0, timcon1, timcon2, timcon3; + + timcon0 = phy_timing->lpx | phy_timing->da_hs_prepare << 8 | + phy_timing->da_hs_zero << 16 | phy_timing->da_hs_trail << 24; + timcon1 = phy_timing->ta_go | phy_timing->ta_sure << 8 | + phy_timing->ta_get << 16 | phy_timing->da_hs_exit << 24; + timcon2 = 1 << 8 | phy_timing->clk_hs_zero << 16 | + phy_timing->clk_hs_trail << 24; + timcon3 = phy_timing->clk_hs_prepare | phy_timing->clk_hs_post << 8 | + phy_timing->clk_hs_exit << 16; + + dsi_write32(&dsi->dsi_phy_timecon0, timcon0); + dsi_write32(&dsi->dsi_phy_timecon1, timcon1); + dsi_write32(&dsi->dsi_phy_timecon2, timcon2); + dsi_write32(&dsi->dsi_phy_timecon3, timcon3); +} + +static void mtk_dsi_reset(void) +{ + dsi_write32(&dsi->dsi_con_ctrl, 1); + dsi_write32(&dsi->dsi_con_ctrl, 0); +} + +static void mtk_dsi_clk_hs_mode_enable(void) +{ + dsi_setbits_le32(&dsi->dsi_phy_lccon, 1); +} + +static void mtk_dsi_set_mode(u32 mode_flags) +{ + u32 tmp_reg1 = 0; + + if (mode_flags & MIPI_DSI_MODE_VIDEO) { + tmp_reg1 = SYNC_PULSE_MODE; + + if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) + tmp_reg1 = BURST_MODE; + + if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) + tmp_reg1 = SYNC_PULSE_MODE; + } + + dsi_write32(&dsi->dsi_mode_ctrl, tmp_reg1); +} + +static void mtk_dsi_phy_timing_calc(u32 format, u32 lanes, + const struct edid *edid, + struct mtk_phy_timing *phy_timing) +{ + u32 ui, cycle_time, data_rate; + u32 bit_per_pixel; + + switch (format) { + case MIPI_DSI_FMT_RGB565: + bit_per_pixel = 16; + break; + case MIPI_DSI_FMT_RGB666: + case MIPI_DSI_FMT_RGB666_PACKED: + bit_per_pixel = 18; + break; + case MIPI_DSI_FMT_RGB888: + default: + bit_per_pixel = 24; + break; + } + + data_rate = edid->mode.pixel_clock * bit_per_pixel / lanes; + + ui = 1000 / (data_rate / 1000) + 1U; + cycle_time = 8000 / (data_rate / 1000) + 1U; + + phy_timing->lpx = DIV_ROUND_UP(60, cycle_time); + phy_timing->da_hs_prepare = DIV_ROUND_UP((40 + 5 * ui), cycle_time); + phy_timing->da_hs_zero = DIV_ROUND_UP((180 + 6 * ui), cycle_time); + phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 80), cycle_time); + + if (phy_timing->da_hs_zero > phy_timing->da_hs_prepare) + phy_timing->da_hs_zero -= phy_timing->da_hs_prepare; + + phy_timing->ta_go = 4U * phy_timing->lpx; + phy_timing->ta_sure = 3U * phy_timing->lpx / 2U; + phy_timing->ta_get = 5U * phy_timing->lpx; + phy_timing->da_hs_exit = 2U * phy_timing->lpx; + + phy_timing->clk_hs_zero = DIV_ROUND_UP(0x150U, cycle_time); + phy_timing->clk_hs_trail = DIV_ROUND_UP(0x64U, cycle_time) + 0xaU; + + phy_timing->clk_hs_prepare = DIV_ROUND_UP(0x40U, cycle_time); + phy_timing->clk_hs_post = DIV_ROUND_UP(80U + 52U * ui, cycle_time); + phy_timing->clk_hs_exit = 2U * phy_timing->lpx; +} + +static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes) +{ + u32 tmp_reg = 0; + + switch (lanes) { + case 1: + tmp_reg = 1 << 2; + break; + case 2: + tmp_reg = 3 << 2; + break; + case 3: + tmp_reg = 7 << 2; + break; + case 4: + default: + tmp_reg = 0xf << 2; + break; + } + + tmp_reg |= (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; + tmp_reg |= (mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; + + dsi_write32(&dsi->dsi_txrx_ctrl, tmp_reg); +} + +static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, + const struct edid *edid, + struct mtk_phy_timing *phy_timing, + u32 lanes) +{ + u32 hsync_active_byte; + u32 hbp_byte; + u32 hfp_byte, tmp_hfp_byte; + u32 vbp_byte; + u32 vfp_byte; + u32 bpp; + u32 packet_fmt; + u32 hactive; + u32 data_phy_cycles; + + if (format == MIPI_DSI_FMT_RGB565) + bpp = 2; + else + bpp = 3; + + vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw - + edid->mode.vborder; + vfp_byte = edid->mode.vso - edid->mode.vborder; + + dsi_write32(&dsi->dsi_vsa_nl, edid->mode.vspw); + dsi_write32(&dsi->dsi_vbp_nl, vbp_byte); + dsi_write32(&dsi->dsi_vfp_nl, vfp_byte); + dsi_write32(&dsi->dsi_vact_nl, edid->mode.va); + + if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) + hbp_byte = (edid->mode.hbl - edid->mode.hso - edid->mode.hspw - + edid->mode.hborder) * bpp - 10; + else + hbp_byte = (edid->mode.hbl - edid->mode.hso - + edid->mode.hborder) * bpp - 10; + + hsync_active_byte = edid->mode.hspw * bpp - 10; + + data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare + + phy_timing->da_hs_zero + phy_timing->da_hs_exit + 2; + + tmp_hfp_byte = (edid->mode.hso - edid->mode.hborder) * bpp; + + if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { + if (tmp_hfp_byte > data_phy_cycles * lanes + 18) { + hfp_byte = tmp_hfp_byte - data_phy_cycles * lanes - 18; + } else { + printk(BIOS_ERR, "HFP less than d-phy, FPS will under 60Hz\n"); + hfp_byte = tmp_hfp_byte; + } + } else { + if (tmp_hfp_byte > data_phy_cycles * lanes + 12) { + hfp_byte = tmp_hfp_byte - data_phy_cycles * lanes - 12; + } else { + printk(BIOS_ERR, "HFP less than d-phy, FPS will under 60Hz\n"); + hfp_byte = tmp_hfp_byte; + } + } + + dsi_write32(&dsi->dsi_hsa_wc, hsync_active_byte); + dsi_write32(&dsi->dsi_hbp_wc, hbp_byte); + dsi_write32(&dsi->dsi_hfp_wc, hfp_byte); + + switch (format) { + case MIPI_DSI_FMT_RGB888: + packet_fmt = PACKED_PS_24BIT_RGB888; + break; + case MIPI_DSI_FMT_RGB666: + packet_fmt = LOOSELY_PS_18BIT_RGB666; + break; + case MIPI_DSI_FMT_RGB666_PACKED: + packet_fmt = PACKED_PS_18BIT_RGB666; + break; + case MIPI_DSI_FMT_RGB565: + packet_fmt = PACKED_PS_16BIT_RGB565; + break; + default: + packet_fmt = PACKED_PS_24BIT_RGB888; + break; + } + + hactive = edid->mode.ha; + packet_fmt |= (hactive * bpp) & DSI_PS_WC; + + dsi_write32(&dsi->dsi_psctrl, 0x2c << 24 | packet_fmt); + dsi_write32(&dsi->dsi_size_con, edid->mode.va << 16 | hactive); +} + +static void mtk_dsi_start(void) +{ + dsi_clrbits_le32(&dsi->dsi_start, 1); + dsi_setbits_le32(&dsi->dsi_start, 1); +} + +static void mtk_dsi_cmdq(u8 *data, u8 len, u32 type) +{ + struct stopwatch sw; + u8 *tx_buf = data; + u8 cmdq_size; + u32 reg_val, cmdq_mask, i, config, cmdq_off, intsta_0; + + while (read32(&dsi->dsi_intsta) & (1 << 31)) { + printk(BIOS_ERR, "%s wait dsi no busy\n", __func__); + mdelay(20); + } + + dsi_write32(&dsi->dsi_intsta, 0); + + if (MTK_DSI_HOST_IS_READ(type)) + config = BTA; + else + config = (len > 2) ? LONG_PACKET : SHORT_PACKET; + + if (len > 2) { + cmdq_size = 1 + (len + 3) / 4; + cmdq_off = 4; + cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1; + reg_val = (len << 16) | (type << 8) | config; + } else { + cmdq_size = 1; + cmdq_off = 2; + cmdq_mask = CONFIG | DATA_ID; + reg_val = (type << 8) | config; + } + + for (i = 0; i < 0x20; i = i + 4) + dsi_write32((void *)DSI_BASE + 0x200 + i, 0); + + for (i = 0; i < len; i++) { + dsi_clrsetbits_le32((void *)DSI_BASE + 0x200 + + ((cmdq_off + i) & (0xfffffffc)), + (0xff << (((i + cmdq_off) & 3) * 8)), + tx_buf[i] << (((i + cmdq_off) & 3) * 8)); + } + + dsi_clrsetbits_le32(&dsi->dsi_cmdq0, cmdq_mask, reg_val); + dsi_clrsetbits_le32(&dsi->dsi_cmdq_size, CMDQ_SIZE, cmdq_size); + mtk_dsi_start(); + + stopwatch_init_usecs_expire(&sw, 400); + do { + intsta_0 = read32(&dsi->dsi_intsta); + if (intsta_0 & CMD_DONE_INT_FLAG) + break; + udelay(4); + } while (!stopwatch_expired(&sw)); + + if (!(intsta_0 & CMD_DONE_INT_FLAG)) + printk(BIOS_ERR, "dsi send cmd time-out(400uS)\n"); +} + +static void push_table(struct lcm_init_table *init_cmd, u32 count) +{ + u32 cmd, i; + u32 type; + + for (i = 0; i < count; i++) { + cmd = init_cmd[i].cmd; + + switch (cmd) { + case DELAY_CMD: + mdelay(init_cmd[i].len); + break; + + case END_OF_TABLE: + break; + + case INIT_DCS_CMD: + switch (init_cmd[i].len) { + case 0: + return; + + case 1: + type = MIPI_DSI_DCS_SHORT_WRITE; + break; + + case 2: + type = MIPI_DSI_DCS_SHORT_WRITE_PARAM; + break; + + default: + type = MIPI_DSI_DCS_LONG_WRITE; + break; + } + mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len, type); + break; + + case INIT_GENENIC_CMD: + default: + switch (init_cmd[i].len) { + case 0: + type = MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM; + break; + case 1: + type = MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM; + break; + case 2: + type = MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM; + break; + default: + type = MIPI_DSI_GENERIC_LONG_WRITE; + break; + } + mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len, type); + break; + } + } +} + +int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual, + const struct edid *edid, struct lcm_init_table *init_cmd, + u32 count) +{ + int data_rate; + struct mtk_phy_timing phy_timing; + + mtk_dsi_phy_timing_calc(format, lanes, edid, &phy_timing); + + data_rate = mtk_dsi_phy_clk_setting(format, lanes, edid); + + if (data_rate < 0) + return -1; + + dsi_write32(&dsi->dsi_force_commit, 3); + mtk_dsi_reset(); + mtk_dsi_phy_timconfig(data_rate, &phy_timing); + mtk_dsi_rxtx_control(mode_flags, lanes); + mtk_dsi_config_vdo_timing(mode_flags, format, edid, &phy_timing, lanes); + mtk_dsi_clk_hs_mode_enable(); + push_table(init_cmd, count); + mtk_dsi_set_mode(mode_flags); + mtk_dsi_start(); + + return 0; +} diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index d41b2b9..75202dd 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -47,12 +47,27 @@ IOCFG_RT_BASE = IO_PHYS + 0x01C50000, IOCFG_RM_BASE = IO_PHYS + 0x01D20000, IOCFG_RB_BASE = IO_PHYS + 0x01D30000, + MIPITX_BASE = IO_PHYS + 0x01E50000, IOCFG_LB_BASE = IO_PHYS + 0x01E70000, IOCFG_LM_BASE = IO_PHYS + 0x01E80000, IOCFG_BL_BASE = IO_PHYS + 0x01E90000, IOCFG_LT_BASE = IO_PHYS + 0x01F20000, IOCFG_TL_BASE = IO_PHYS + 0x01F30000, SSUSB_SIF_BASE = IO_PHYS + 0x01F40300, + MMSYS_BASE = IO_PHYS + 0x04000000, + DISP_OVL0_BASE = IO_PHYS + 0x04008000, + DISP_OVL0_2L_BASE = IO_PHYS + 0x04009000, + DISP_OVL1_2L_BASE = IO_PHYS + 0x0400A000, + DISP_RDMA0_BASE = IO_PHYS + 0x0400B000, + DISP_RDMA1_BASE = IO_PHYS + 0x0400C000, + DISP_COLOR0_BASE = IO_PHYS + 0x0400E000, + DISP_CCORR0_BASE = IO_PHYS + 0x0400F000, + DISP_AAL0_BASE = IO_PHYS + 0x04010000, + DISP_GAMMA0_BASE = IO_PHYS + 0x04011000, + DISP_DITHER0_BASE = IO_PHYS + 0x04012000, + DSI_BASE = IO_PHYS + 0x04014000, + DISP_MUTEX_BASE = IO_PHYS + 0x04016000, + SMI_LARB0 = IO_PHYS + 0x04017000, SMI_BASE = IO_PHYS + 0x04019000, }; diff --git a/src/soc/mediatek/mt8183/include/soc/ddp.h b/src/soc/mediatek/mt8183/include/soc/ddp.h new file mode 100644 index 0000000..1914868 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/ddp.h @@ -0,0 +1,315 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DDP_REG_H_ +#define _DDP_REG_H_ + +#include <soc/addressmap.h> +#include <types.h> + +#define MAIN_PATH_OVL_NR 2 + +struct mmsys_cfg_regs { + u32 reserved_0x000[64]; /* 0x000 */ + u32 mmsys_cg_con0; /* 0x100 */ + u32 mmsys_cg_set0; /* 0x104 */ + u32 mmsys_cg_clr0; /* 0x108 */ + u32 reserved_0x10C; /* 0x10C */ + u32 mmsys_cg_con1; /* 0x110 */ + u32 mmsys_cg_set1; /* 0x114 */ + u32 mmsys_cg_clr1; /* 0x118 */ + u32 reserved_0x11C[889]; /* 0x11C */ + u32 disp_ovl0_mout_en; /* 0xF00 */ + u32 disp_ovl0_2l_mout_en; /* 0xF04 */ + u32 disp_ovl1_2l_mout_en; /* 0xF08 */ + u32 disp_dither0_mout_en; /* 0xF0C */ + u32 reserved_0xF10[5]; /* 0xF10 - 0xF20 */ + u32 disp_path0_sel_in; /* 0xF24 */ + u32 reserved_0xF28; /* 0xF28 */ + u32 dsi0_sel_in; /* 0xF2C */ + u32 dpi0_sel_in; /* 0xF30 */ + u32 reserved_0xF34; /* 0xF34 */ + u32 disp_ovl0_2l_sel_in; /* 0xF38 */ + u32 reserved_0xF3C[5]; /* 0xF3C - 0xF4C */ + u32 disp_rdma0_sout_sel_in; /* 0xF50 */ + u32 disp_rdma1_sout_sel_in; /* 0xF54 */ + u32 reserved_0xF58[3]; /* 0xF58 - 0xF60 */ + u32 dpi0_sel_sout_sel_in; /* 0xF64 */ +}; + +check_member(mmsys_cfg_regs, mmsys_cg_con0, 0x100); +check_member(mmsys_cfg_regs, dpi0_sel_sout_sel_in, 0xF64); +static struct mmsys_cfg_regs *const mmsys_cfg = + (void *)MMSYS_BASE; + + +/* DISP_REG_CONFIG_MMSYS_CG_CON0 + Configures free-run clock gating 0 + 0: Enable clock + 1: Clock gating */ +enum { + CG_CON0_SMI_COMMON = BIT(0), + CG_CON0_SMI_LARB0 = BIT(1), + CG_CON0_GALS_COMMON0 = BIT(3), + CG_CON0_GALS_COMMON1 = BIT(4), + CG_CON0_DISP_OVL0 = BIT(20), + CG_CON0_DISP_OVL0_2L = BIT(21), + CG_CON0_DISP_OVL1_2L = BIT(22), + CG_CON0_DISP_RDMA0 = BIT(23), + CG_CON0_DISP_RDMA1 = BIT(24), + CG_CON0_DISP_WDMA0 = BIT(25), + CG_CON0_DISP_COLOR0 = BIT(26), + CG_CON0_DISP_CCORR0 = BIT(27), + CG_CON0_DISP_AAL0 = BIT(28), + CG_CON0_DISP_GAMMA0 = BIT(29), + CG_CON0_DISP_DITHER0 = BIT(30), + CG_CON0_DISP_ALL = CG_CON0_SMI_COMMON | + CG_CON0_SMI_LARB0 | + CG_CON0_GALS_COMMON0 | + CG_CON0_GALS_COMMON1 | + CG_CON0_DISP_OVL0 | + CG_CON0_DISP_OVL0_2L | + CG_CON0_DISP_RDMA0 | + CG_CON0_DISP_COLOR0 | + CG_CON0_DISP_CCORR0 | + CG_CON0_DISP_AAL0 | + CG_CON0_DISP_DITHER0 | + CG_CON0_DISP_GAMMA0, + CG_CON0_ALL = 0xffffffff +}; + +/* DISP_REG_CONFIG_MMSYS_CG_CON1 + Configures free-run clock gating 1 + 0: Enable clock + 1: Clock gating */ +enum { + CG_CON1_DISP_DSI0 = BIT(0), + CG_CON1_DISP_DSI0_INTERFACE = BIT(1), + CG_CON1_DISP_26M = BIT(7), + + CG_CON1_ALL = 0xffffffff +}; + +enum { + OVL0_MOUT_EN_RDMA0 = BIT(0), + OVL0_MOUT_EN_OVL0_2L = BIT(4), + OVL0_2L_MOUT_EN_DISP_PATH0 = BIT(0), + OVL1_2L_MOUT_EN_DISP_RDMA1 = BIT(4), + DITHER0_MOUT_EN_DISP_DSI0 = BIT(0), +}; + +enum { + DISP_PATH0_SEL_IN_OVL0 = 0, + DISP_PATH0_SEL_IN_OVL0_2L = 1, + DSI0_SEL_IN_DITHER0_MOUT = 0, + DSI0_SEL_IN_RDMA0 = 1, + RDMA0_SOUT_SEL_IN_DSI0 = 0, + RDMA0_SOUT_SEL_IN_COLOR = 1, +}; + +struct disp_mutex_regs { + u32 inten; + u32 intsta; + u32 reserved0[6]; + struct { + u32 en; + u32 dummy; + u32 rst; + u32 ctl; + u32 mod; + u32 reserved[3]; + } mutex[12]; +}; + +static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE; + +enum { + MUTEX_MOD_DISP_RDMA0 = BIT(0), + MUTEX_MOD_DISP_RDMA1 = BIT(1), + MUTEX_MOD_DISP_OVL0 = BIT(9), + MUTEX_MOD_DISP_OVL0_2L = BIT(10), + MUTEX_MOD_DISP_OVL1_2L = BIT(11), + MUTEX_MOD_DISP_WDMA0 = BIT(12), + MUTEX_MOD_DISP_COLOR0 = BIT(13), + MUTEX_MOD_DISP_CCORR0 = BIT(14), + MUTEX_MOD_DISP_AAL0 = BIT(15), + MUTEX_MOD_DISP_GAMMA0 = BIT(16), + MUTEX_MOD_DISP_DITHER0 = BIT(17), + MUTEX_MOD_DISP_PWM0 = BIT(28), + MUTEX_MOD_MAIN_PATH = MUTEX_MOD_DISP_OVL0 | MUTEX_MOD_DISP_OVL0_2L | + MUTEX_MOD_DISP_RDMA0 | MUTEX_MOD_DISP_COLOR0 | + MUTEX_MOD_DISP_CCORR0 | MUTEX_MOD_DISP_AAL0 | + MUTEX_MOD_DISP_GAMMA0 | + MUTEX_MOD_DISP_DITHER0, +}; + +enum { + MUTEX_SOF_SINGLE_MODE = 0, + MUTEX_SOF_DSI0 = 1, + MUTEX_SOF_DPI0 = 2, +}; + +struct disp_ovl_regs { + u32 sta; + u32 inten; + u32 intsta; + u32 en; + u32 trig; + u32 rst; + u32 reserved_0x018[2]; + u32 roi_size; + u32 datapath_con; + u32 roi_bgclr; + u32 src_con; + struct { + u32 con; + u32 srckey; + u32 src_size; + u32 offset; + u32 reserved0; + u32 pitch; + u32 reserved1[2]; + } layer[4]; + u32 reserved_0x0B0[4]; + struct { + u32 ctrl; + u32 reserved0; + u32 mem_gmc_setting; + u32 mem_slow_con; + u32 fifo_ctrl; + u32 reserved1[3]; + } rdma[4]; + u32 reserved_0x140[880]; + u32 reserved_0xF00[16]; + u32 l0_addr; + u32 reserved_0xF44[7]; + u32 l1_addr; + u32 reserved_0xF64[7]; + u32 l2_addr; + u32 reserved_0xF84[7]; + u32 l3_addr; +}; + +check_member(disp_ovl_regs, l3_addr, 0xFA0); +static struct disp_ovl_regs *const disp_ovl[2] = { + (void *)DISP_OVL0_BASE, (void *)DISP_OVL0_2L_BASE +}; + +struct disp_rdma_regs { + u32 int_enable; + u32 int_status; + u32 reserved0[2]; + u32 global_con; + u32 size_con_0; + u32 size_con_1; + u32 target_line; + u32 reserved1; + u32 mem_con; + u32 reserved2; + u32 mem_src_pitch; + u32 mem_gmc_setting_0; + u32 mem_gmc_setting_1; + u32 mem_slow_con; + u32 mem_gmc_setting_2; + u32 fifo_con; + u32 reserved3[4]; + u32 cf[3][3]; + u32 cf_pre_add[3]; + u32 cf_post_add[3]; + u32 dummy; + u32 debug_out_sel; +}; + +enum { + RDMA_ENGINE_EN = BIT(0), + RDMA_FIFO_UNDERFLOW_EN = BIT(31), + RDMA_FIFO_SIZE_0 = 5, /* 5K */ + RDMA_VREFRESH = 60, /* vrefresh 60HZ */ + RDMA_MEM_GMC = 0x40402020, +}; + +check_member(disp_rdma_regs, debug_out_sel, 0x94); +static struct disp_rdma_regs *const disp_rdma[2] = { + (void *)DISP_RDMA0_BASE, + (void *)DISP_RDMA1_BASE, +}; + +struct disp_color_regs { + u8 reserved0[1024]; + u32 cfg_main; + u8 reserved1[2044]; + u32 start; + u8 reserved2[76]; + u32 width; + u32 height; +}; + +check_member(disp_color_regs, height, 0xC54); +static struct disp_color_regs *const disp_color = (void *)DISP_COLOR0_BASE; + +enum { + COLOR_BYPASS_ALL = BIT(7), + COLOR_SEQ_SEL = BIT(13), +}; + +struct disp_pq_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; +}; + +enum { + PQ_EN = BIT(0), + PQ_RELAY_MODE = BIT(0), +}; + +static struct disp_pq_regs *const disp_ccorr = (void *)DISP_CCORR0_BASE; + +static struct disp_pq_regs *const disp_aal = (void *)DISP_AAL0_BASE; + +static struct disp_pq_regs *const disp_gamma = (void *)DISP_GAMMA0_BASE; + +static struct disp_pq_regs *const disp_dither = (void *)DISP_DITHER0_BASE; + +enum { + SMI_LARB_NON_SEC_CON = 0x380, +}; + +enum OVL_INPUT_FORMAT { + OVL_INFMT_RGB565 = 0, + OVL_INFMT_RGB888 = 1, + OVL_INFMT_RGBA8888 = 2, + OVL_INFMT_ARGB8888 = 3, + OVL_INFMT_UYVY = 4, + OVL_INFMT_YUYV = 5, + OVL_INFMT_UNKNOWN = 16, + + OVL_COLOR_BASE = 30, + OVL_INFMT_BGR565 = OVL_INFMT_RGB565 + OVL_COLOR_BASE, + OVL_INFMT_BGR888 = OVL_INFMT_RGB888 + OVL_COLOR_BASE, + OVL_INFMT_BGRA8888 = OVL_INFMT_RGBA8888 + OVL_COLOR_BASE, + OVL_INFMT_ABGR8888 = OVL_INFMT_ARGB8888 + OVL_COLOR_BASE, +}; + +void mtk_ddp_init(void); +void mtk_ddp_mode_set(const struct edid *edid); + +#endif diff --git a/src/soc/mediatek/mt8183/include/soc/dsi.h b/src/soc/mediatek/mt8183/include/soc/dsi.h new file mode 100644 index 0000000..dc89668 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/dsi.h @@ -0,0 +1,487 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DSI_REG_H_ +#define _DSI_REG_H_ + +#include <edid.h> +#include <soc/addressmap.h> +#include <types.h> + +enum mipi_dsi_pixel_format { + MIPI_DSI_FMT_RGB888, + MIPI_DSI_FMT_RGB666, + MIPI_DSI_FMT_RGB666_PACKED, + MIPI_DSI_FMT_RGB565 +}; + +/* video mode */ +enum { + MIPI_DSI_MODE_VIDEO = BIT(0), + /* video burst mode */ + MIPI_DSI_MODE_VIDEO_BURST = BIT(1), + /* video pulse mode */ + MIPI_DSI_MODE_VIDEO_SYNC_PULSE = BIT(2), + /* enable auto vertical count mode */ + MIPI_DSI_MODE_VIDEO_AUTO_VERT = BIT(3), + /* enable hsync-end packets in vsync-pulse and v-porch area */ + MIPI_DSI_MODE_VIDEO_HSE = BIT(4), + /* disable hfront-porch area */ + MIPI_DSI_MODE_VIDEO_HFP = BIT(5), + /* disable hback-porch area */ + MIPI_DSI_MODE_VIDEO_HBP = BIT(6), + /* disable hsync-active area */ + MIPI_DSI_MODE_VIDEO_HSA = BIT(7), + /* flush display FIFO on vsync pulse */ + MIPI_DSI_MODE_VSYNC_FLUSH = BIT(8), + /* disable EoT packets in HS mode */ + MIPI_DSI_MODE_EOT_PACKET = BIT(9), + /* device supports non-continuous clock behavior (DSI spec 5.6.1) */ + MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10), + /* transmit data in low power */ + MIPI_DSI_MODE_LPM = BIT(11) +}; + +struct dsi_regs { + u32 dsi_start; + u8 reserved0[4]; + u32 dsi_inten; + u32 dsi_intsta; + u32 dsi_con_ctrl; + u32 dsi_mode_ctrl; + u32 dsi_txrx_ctrl; + u32 dsi_psctrl; + u32 dsi_vsa_nl; + u32 dsi_vbp_nl; + u32 dsi_vfp_nl; + u32 dsi_vact_nl; + u32 dsi_lfr_con; + u32 dsi_lfr_sta; + u32 dsi_size_con; + u32 dsi_vfp_early_stop; + u32 reserved1[4]; + u32 dsi_hsa_wc; + u32 dsi_hbp_wc; + u32 dsi_hfp_wc; + u32 dsi_bllp_wc; + u32 dsi_cmdq_size; + u32 dsi_hstx_cklp_wc; + u8 reserved2[156]; + u32 dsi_phy_lccon; + u32 dsi_phy_ld0con; + u8 reserved3[4]; + u32 dsi_phy_timecon0; + u32 dsi_phy_timecon1; + u32 dsi_phy_timecon2; + u32 dsi_phy_timecon3; + u8 reserved4[16]; + u32 dsi_vm_cmd_con; + u8 reserved5[92]; + u32 dsi_force_commit; + u8 reserved6[108]; + u32 dsi_cmdq0; +}; + +check_member(dsi_regs, dsi_phy_lccon, 0x104); +check_member(dsi_regs, dsi_phy_timecon3, 0x11c); +check_member(dsi_regs, dsi_vm_cmd_con, 0x130); +check_member(dsi_regs, dsi_force_commit, 0x190); +check_member(dsi_regs, dsi_cmdq0, 0x200); +static struct dsi_regs *const dsi = (void *)DSI_BASE; + +#define DELAY_CMD 0 +#define END_OF_TABLE 1 +#define INIT_GENENIC_CMD 2 +#define INIT_DCS_CMD 3 + +struct lcm_init_table { + u32 cmd; + u32 len; + u8 data[64]; +}; + +struct mtk_phy_timing { + u8 lpx; + u8 da_hs_prepare; + u8 da_hs_zero; + u8 da_hs_trail; + + u8 ta_go; + u8 ta_sure; + u8 ta_get; + u8 da_hs_exit; + + u8 clk_hs_zero; + u8 clk_hs_trail; + + u8 clk_hs_prepare; + u8 clk_hs_post; + u8 clk_hs_exit; +}; + +/* DSI_INTSTA */ +enum { + LPRX_RD_RDY_INT_FLAG = BIT(0), + CMD_DONE_INT_FLAG = BIT(1), + TE_RDY_INT_FLAG = BIT(2), + VM_DONE_INT_FLAG = BIT(3), + EXT_TE_RDY_INT_FLAG = BIT(4), + DSI_BUSY = BIT(31), +}; + +/* DSI_CON_CTRL */ +enum { + DSI_RESET = BIT(0), + DSI_EN = BIT(1), + DSI_DUAL = BIT(4), +}; + +/* DSI_MODE_CTRL */ +enum { + MODE = 3, + CMD_MODE = 0, + SYNC_PULSE_MODE = 1, + SYNC_EVENT_MODE = 2, + BURST_MODE = 3, + FRM_MODE = BIT(16), + MIX_MODE = BIT(17) +}; + +/* DSI_PSCTRL */ +enum { + DSI_PS_WC = 0x3fff, + DSI_PS_SEL = (3 << 16), + PACKED_PS_16BIT_RGB565 = (0 << 16), + LOOSELY_PS_18BIT_RGB666 = (1 << 16), + PACKED_PS_18BIT_RGB666 = (2 << 16), + PACKED_PS_24BIT_RGB888 = (3 << 16) +}; + +/* DSI_CMDQ_SIZE */ +enum { + CMDQ_SIZE = 0x3f, +}; + +/* DSI_PHY_LCCON */ +enum { + LC_HS_TX_EN = BIT(0), + LC_ULPM_EN = BIT(1), + LC_WAKEUP_EN = BIT(2) +}; + +/*DSI_PHY_LD0CON */ +enum { + LD0_RM_TRIG_EN = BIT(0), + LD0_ULPM_EN = BIT(1), + LD0_WAKEUP_EN = BIT(2) +}; + +enum { + LPX = (0xff << 0), + HS_PRPR = (0xff << 8), + HS_ZERO = (0xff << 16), + HS_TRAIL = (0xff << 24) +}; + +enum { + TA_GO = (0xff << 0), + TA_SURE = (0xff << 8), + TA_GET = (0xff << 16), + DA_HS_EXIT = (0xff << 24) +}; + +enum { + CONT_DET = (0xff << 0), + CLK_ZERO = (0xf << 16), + CLK_TRAIL = (0xff << 24) +}; + +enum { + CLK_HS_PRPR = (0xff << 0), + CLK_HS_POST = (0xff << 8), + CLK_HS_EXIT = (0xf << 16) +}; + +/* DSI_VM_CMD_CON */ +enum { + VM_CMD_EN = BIT(0), + TS_VFP_EN = BIT(5), +}; + +/* DSI_CMDQ0 */ +enum { + CONFIG = (0xff << 0), + SHORT_PACKET = 0, + LONG_PACKET = 2, + BTA = BIT(2), + DATA_ID = (0xff << 8), + DATA_0 = (0xff << 16), + DATA_1 = (0xff << 24), +}; + +#define MIPITX_LANE_CON 0x000c +#define MIPITX_PLL_PWR 0x0028 +#define MIPITX_PLL_CON0 0x002c +#define MIPITX_PLL_CON1 0x0030 +#define MIPITX_PLL_CON2 0x0034 +#define MIPITX_PLL_CON3 0x0038 +#define MIPITX_PLL_CON4 0x003c +#define MIPITX_D2_SW_CTL_EN 0x0144 +#define MIPITX_D0_SW_CTL_EN 0x0244 +#define MIPITX_CK_CKMODE_EN 0x0328 +#define DSI_CK_CKMODE_EN BIT(0) +#define MIPITX_CK_SW_CTL_EN 0x0344 +#define MIPITX_D1_SW_CTL_EN 0x0444 +#define MIPITX_D3_SW_CTL_EN 0x0544 +#define DSI_SW_CTL_EN BIT(0) +#define AD_DSI_PLL_SDM_PWR_ON BIT(0) +#define AD_DSI_PLL_SDM_ISO_EN BIT(1) + +#define RG_DSI_PLL_EN BIT(4) +#define RG_DSI_PLL_POSDIV (0x7 << 8) + +/* MIPITX_REG */ +struct mipi_tx_regs { + u32 dsi_con; + u32 dsi_clock_lane; + u32 dsi_data_lane[4]; + u8 reserved0[40]; + u32 dsi_top_con; + u32 dsi_bg_con; + u8 reserved1[8]; + u32 dsi_pll_con0; + u32 dsi_pll_con1; + u32 dsi_pll_con2; + u32 dsi_pll_con3; + u32 dsi_pll_chg; + u32 dsi_pll_top; + u32 dsi_pll_pwr; + u8 reserved2[4]; + u32 dsi_rgs; + u32 dsi_gpi_en; + u32 dsi_gpi_pull; + u32 dsi_phy_sel; + u32 dsi_sw_ctrl_en; + u32 dsi_sw_ctrl_con0; + u32 dsi_sw_ctrl_con1; + u32 dsi_sw_ctrl_con2; + u32 dsi_dbg_con; + u32 dsi_dbg_out; + u32 dsi_apb_async_sta; +}; + +check_member(mipi_tx_regs, dsi_top_con, 0x40); +check_member(mipi_tx_regs, dsi_pll_pwr, 0x68); + +static void *const mipi_tx = (void *)MIPITX_BASE; + +/* MIPITX_DSI_CON */ +enum { + RG_DSI_LDOCORE_EN = BIT(0), + RG_DSI_CKG_LDOOUT_EN = BIT(1), + RG_DSI_BCLK_SEL = (3 << 2), + RG_DSI_LD_IDX_SEL = (7 << 4), + RG_DSI_PHYCLK_SEL = (2 << 8), + RG_DSI_DSICLK_FREQ_SEL = BIT(10), + RG_DSI_LPTX_CLMP_EN = BIT(11) +}; + +/* MIPITX_DSI_CLOCK_LANE */ +enum { + LDOOUT_EN = BIT(0), + CKLANE_EN = BIT(1), + IPLUS1 = BIT(2), + LPTX_IPLUS2 = BIT(3), + LPTX_IMINUS = BIT(4), + LPCD_IPLUS = BIT(5), + LPCD_IMLUS = BIT(6), + RT_CODE = (0xf << 8) +}; + +/* MIPITX_DSI_TOP_CON */ +enum { + RG_DSI_LNT_INTR_EN = BIT(0), + RG_DSI_LNT_HS_BIAS_EN = BIT(1), + RG_DSI_LNT_IMP_CAL_EN = BIT(2), + RG_DSI_LNT_TESTMODE_EN = BIT(3), + RG_DSI_LNT_IMP_CAL_CODE = (0xf << 4), + RG_DSI_LNT_AIO_SEL = (7 << 8), + RG_DSI_PAD_TIE_LOW_EN = BIT(11), + RG_DSI_DEBUG_INPUT_EN = BIT(12), + RG_DSI_PRESERVE = (7 << 13) +}; + +/* MIPITX_DSI_BG_CON */ +enum { + RG_DSI_BG_CORE_EN = BIT(0), + RG_DSI_BG_CKEN = BIT(1), + RG_DSI_BG_DIV = (0x3 << 2), + RG_DSI_BG_FAST_CHARGE = BIT(4), + RG_DSI_V12_SEL = (7 << 5), + RG_DSI_V10_SEL = (7 << 8), + RG_DSI_V072_SEL = (7 << 11), + RG_DSI_V04_SEL = (7 << 14), + RG_DSI_V032_SEL = (7 << 17), + RG_DSI_V02_SEL = (7 << 20), + rsv_23 = BIT(23), + RG_DSI_BG_R1_TRIM = (0xf << 24), + RG_DSI_BG_R2_TRIM = (0xf << 28) +}; + +/* MIPITX_DSI_PLL_CON0 */ +enum { + RG_DSI_MPPLL_PLL_EN = BIT(0), + RG_DSI_MPPLL_PREDIV = (3 << 1), + RG_DSI_MPPLL_TXDIV0 = (3 << 3), + RG_DSI_MPPLL_TXDIV1 = (3 << 5), + RG_DSI_MPPLL_POSDIV = (7 << 7), + RG_DSI_MPPLL_MONVC_EN = BIT(10), + RG_DSI_MPPLL_MONREF_EN = BIT(11), + RG_DSI_MPPLL_VOD_EN = BIT(12) +}; + +/* MIPITX_DSI_PLL_CON1 */ +enum { + RG_DSI_MPPLL_SDM_FRA_EN = BIT(0), + RG_DSI_MPPLL_SDM_SSC_PH_INIT = BIT(1), + RG_DSI_MPPLL_SDM_SSC_EN = BIT(2), + RG_DSI_MPPLL_SDM_SSC_PRD = (0xffff << 16) +}; + +/* MIPITX_DSI_PLL_PWR */ +enum { + RG_DSI_MPPLL_SDM_PWR_ON = BIT(0), + RG_DSI_MPPLL_SDM_ISO_EN = BIT(1), + RG_DSI_MPPLL_SDM_PWR_ACK = BIT(8) +}; + +/* MIPI DSI Processor-to-Peripheral transaction types */ +enum { + MIPI_DSI_V_SYNC_START = 0x01, + MIPI_DSI_V_SYNC_END = 0x11, + MIPI_DSI_H_SYNC_START = 0x21, + MIPI_DSI_H_SYNC_END = 0x31, + + MIPI_DSI_COLOR_MODE_OFF = 0x02, + MIPI_DSI_COLOR_MODE_ON = 0x12, + MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22, + MIPI_DSI_TURN_ON_PERIPHERAL = 0x32, + + MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03, + MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13, + MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23, + + MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04, + MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14, + MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24, + + MIPI_DSI_DCS_SHORT_WRITE = 0x05, + MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15, + + MIPI_DSI_DCS_READ = 0x06, + + MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, + + MIPI_DSI_END_OF_TRANSMISSION = 0x08, + + MIPI_DSI_NULL_PACKET = 0x09, + MIPI_DSI_BLANKING_PACKET = 0x19, + MIPI_DSI_GENERIC_LONG_WRITE = 0x29, + MIPI_DSI_DCS_LONG_WRITE = 0x39, + + MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c, + + MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d, + MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d, + + MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e, + MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e, + MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e, + MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e, +}; + +/* MIPI DSI Peripheral-to-Processor transaction types */ +enum { + MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02, + MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08, + MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11, + MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12, + MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a, + MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c, + MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21, + MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22, +}; + +/* MIPI DCS commands */ +enum { + MIPI_DCS_NOP = 0x00, + MIPI_DCS_SOFT_RESET = 0x01, + MIPI_DCS_GET_DISPLAY_ID = 0x04, + MIPI_DCS_GET_RED_CHANNEL = 0x06, + MIPI_DCS_GET_GREEN_CHANNEL = 0x07, + MIPI_DCS_GET_BLUE_CHANNEL = 0x08, + MIPI_DCS_GET_DISPLAY_STATUS = 0x09, + MIPI_DCS_GET_POWER_MODE = 0x0A, + MIPI_DCS_GET_ADDRESS_MODE = 0x0B, + MIPI_DCS_GET_PIXEL_FORMAT = 0x0C, + MIPI_DCS_GET_DISPLAY_MODE = 0x0D, + MIPI_DCS_GET_SIGNAL_MODE = 0x0E, + MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F, + MIPI_DCS_ENTER_SLEEP_MODE = 0x10, + MIPI_DCS_EXIT_SLEEP_MODE = 0x11, + MIPI_DCS_ENTER_PARTIAL_MODE = 0x12, + MIPI_DCS_ENTER_NORMAL_MODE = 0x13, + MIPI_DCS_EXIT_INVERT_MODE = 0x20, + MIPI_DCS_ENTER_INVERT_MODE = 0x21, + MIPI_DCS_SET_GAMMA_CURVE = 0x26, + MIPI_DCS_SET_DISPLAY_OFF = 0x28, + MIPI_DCS_SET_DISPLAY_ON = 0x29, + MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A, + MIPI_DCS_SET_PAGE_ADDRESS = 0x2B, + MIPI_DCS_WRITE_MEMORY_START = 0x2C, + MIPI_DCS_WRITE_LUT = 0x2D, + MIPI_DCS_READ_MEMORY_START = 0x2E, + MIPI_DCS_SET_PARTIAL_AREA = 0x30, + MIPI_DCS_SET_SCROLL_AREA = 0x33, + MIPI_DCS_SET_TEAR_OFF = 0x34, + MIPI_DCS_SET_TEAR_ON = 0x35, + MIPI_DCS_SET_ADDRESS_MODE = 0x36, + MIPI_DCS_SET_SCROLL_START = 0x37, + MIPI_DCS_EXIT_IDLE_MODE = 0x38, + MIPI_DCS_ENTER_IDLE_MODE = 0x39, + MIPI_DCS_SET_PIXEL_FORMAT = 0x3A, + MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C, + MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E, + MIPI_DCS_SET_TEAR_SCANLINE = 0x44, + MIPI_DCS_GET_SCANLINE = 0x45, + MIPI_DCS_READ_DDB_START = 0xA1, + MIPI_DCS_READ_DDB_CONTINUE = 0xA8, +}; + +#define MTK_DSI_HOST_IS_READ(type) \ + ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \ + (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \ + (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \ + (type == MIPI_DSI_DCS_READ)) + +extern int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual, + const struct edid *edid, + struct lcm_init_table *init_cmd, + u32 count); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09d127ab491bca98f3a9c9b7d4ad4b09674c963d Gerrit-Change-Number: 33106 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/analogix: improve the clock tolance from 0.1% to 2%
by jitao shi (Code Review) 27 Mar '21

27 Mar '21

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39025 ) Change subject: drivers/analogix: improve the clock tolance from 0.1% to 2% ...................................................................... drivers/analogix: improve the clock tolance from 0.1% to 2% Improve the input tolance to avoid panel scroll. BUG=b:149051882 BRANCH=kukui TEST=None Change-Id: I4af96f58876932175b28fc0a8543720ebd7b5deb Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> --- M src/drivers/analogix/anx7625/anx7625.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/39025/1 diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index 9387a83b..d2d09d8 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -395,7 +395,7 @@ ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_PLL_N_NUM_7_0, (n & 0xff)); /* diff */ - ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_DIGITAL_ADJ_1, 0x37); + ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_DIGITAL_ADJ_1, 0x3d); ret |= anx7625_odfc_config(bus, post_divider - 1); -- To view, visit https://review.coreboot.org/c/coreboot/+/39025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4af96f58876932175b28fc0a8543720ebd7b5deb Gerrit-Change-Number: 39025 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

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