coreboot-gerrit October 2020

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Change in coreboot[master]: [RFC] AMD APM_CNT and SMI enablement
by Kyösti Mälkki (Code Review) 15 Mar '21

15 Mar '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42563 ) Change subject: [RFC] AMD APM_CNT and SMI enablement ...................................................................... [RFC] AMD APM_CNT and SMI enablement Some suspicious callsite caught my eye. Change-Id: I8d1287566061bc5d6f05e687f2b30c6bcb66c999 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/picasso/southbridge.c M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/42563/1 diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 0ff5606..89b49f6 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -233,6 +233,7 @@ u32 reg; msr_t cst_addr; + /* We use some of these ports in SMM regardless of whether or not * ACPI tables are generated. Enable these ports indiscriminately. */ diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index e90fe1b..8a45fda 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -470,6 +470,7 @@ { u32 reg; + /* We use some of these ports in SMM regardless of whether or not * ACPI tables are generated. Enable these ports indiscriminately. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d1287566061bc5d6f05e687f2b30c6bcb66c999 Gerrit-Change-Number: 42563 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/t440p: update VBT
by DaLao (Code Review) 14 Mar '21

14 Mar '21

DaLao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40723 ) Change subject: mb/lenovo/t440p: update VBT ...................................................................... mb/lenovo/t440p: update VBT Update T440p's VBT from to version 2179. Extracted from the latest bios update file: T440p's bios image https://download.lenovo.com/pccbbs/mobiles/gluj42us.iso Test: boot t440p with both SeaBIOS and Tianocore payloads, verify dp output and backlight control all works under both Linux and Windows. Signed-off-by: dalao <dalao(a)tutanota.com> Change-Id: If8669b8de6fa0801e261138651b8b2cf50432a70 --- M src/mainboard/lenovo/t440p/data.vbt 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/40723/1 diff --git a/src/mainboard/lenovo/t440p/data.vbt b/src/mainboard/lenovo/t440p/data.vbt index 1b2cd87..79077cc 100644 --- a/src/mainboard/lenovo/t440p/data.vbt +++ b/src/mainboard/lenovo/t440p/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/40723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8669b8de6fa0801e261138651b8b2cf50432a70 Gerrit-Change-Number: 40723 Gerrit-PatchSet: 1 Gerrit-Owner: DaLao <dalao(a)tutanota.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Override uart base address via VPD variable
by Bryant Ou (Code Review) 14 Mar '21

14 Mar '21

Bryant Ou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45408 ) Change subject: mb/ocp/deltalake: Override uart base address via VPD variable ...................................................................... mb/ocp/deltalake: Override uart base address via VPD variable Use VPD of "uart_ioport" to override base address at run time, the data will be used during FSP/coreboot if UART_OVERRIDE_BASE_ADDR is selected. Tested=On OCP Delta Lake, console messages correctly output to uart port which is defined in VPD. Signed-off-by: Bryant Ou <Bryant.Ou.Q(a)gmail.com> Change-Id: I55a85d6f137ef1aba95466e7b094740b685bf9bd --- M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/ocp/deltalake/Makefile.inc M src/mainboard/ocp/deltalake/romstage.c A src/mainboard/ocp/deltalake/uart.c M src/mainboard/ocp/deltalake/vpd.h 5 files changed, 66 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/45408/1 diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index adce988..5671664 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -16,6 +16,7 @@ select IPMI_OCP select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM2 + select UART_OVERRIDE_BASE_ADDR config POWER_STATE_DEFAULT_ON_AFTER_FAILURE default n diff --git a/src/mainboard/ocp/deltalake/Makefile.inc b/src/mainboard/ocp/deltalake/Makefile.inc index be6af24..ecef891 100644 --- a/src/mainboard/ocp/deltalake/Makefile.inc +++ b/src/mainboard/ocp/deltalake/Makefile.inc @@ -8,5 +8,14 @@ ramstage-y += ramstage.c ipmi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c +ifeq ($(CONFIG_UART_OVERRIDE_BASE_ADDR),y) +bootblock-y += uart.c +verstage-y += uart.c +romstage-y += uart.c +postcar-y += uart.c +ramstage-y += uart.c +smm-$(CONFIG_DEBUG_SMI) += uart.c +endif + CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH) diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index 71a26c8..bf7491c 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -20,6 +20,8 @@ { uint8_t val; char val_str[VPD_LEN]; + uint16_t base; + char port[VPD_LEN]; /* Send FSP log message to SOL */ if (vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val)) @@ -29,7 +31,12 @@ "SerialIoUartDebugEnable to %d\n", FSP_LOG, FSP_LOG_DEFAULT); mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; } - mupd->FspmConfig.SerialIoUartDebugIoBase = 0x2f8; + + if (vpd_gets(UART_IOPORT, port, VPD_LEN, VPD_RW_THEN_RO)) + base = hex2int(port); + else + base = hex2int(UART_IOPORT_DEFAULT); + mupd->FspmConfig.SerialIoUartDebugIoBase = base; if (mupd->FspmConfig.SerialIoUartDebugEnable) { /* FSP debug log level */ diff --git a/src/mainboard/ocp/deltalake/uart.c b/src/mainboard/ocp/deltalake/uart.c new file mode 100644 index 0000000..28801c8 --- /dev/null +++ b/src/mainboard/ocp/deltalake/uart.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/uart.h> +#include <drivers/vpd/vpd.h> +#include <string.h> +#include "vpd.h" + +int hex2int(const char *hexstr) +{ + int val = 0; + + if (hexstr[0] == '0' && hexstr[1] == 'x') + hexstr = hexstr + 2; + + while (*hexstr) { + char c = *hexstr++; + if (c >= '0' && c <= '9') + c = c - '0'; + else if (c >= 'a' && c <='f') + c = c - 'a' + 10; + else if (c >= 'A' && c <='F') + c = c - 'A' + 10; + val = (val << 4) | (c & 0xF); + } + + return val; +} + +#if (CONFIG(UART_OVERRIDE_BASE_ADDR)) +uintptr_t uart_platform_base(unsigned int idx) +{ + char port[VPD_LEN]; + uintptr_t base; + + if (vpd_gets(UART_IOPORT, port, VPD_LEN, VPD_RW_THEN_RO)) + base = hex2int(port); + else + base = hex2int(UART_IOPORT_DEFAULT); + + return base; +} +#endif \ No newline at end of file diff --git a/src/mainboard/ocp/deltalake/vpd.h b/src/mainboard/ocp/deltalake/vpd.h index ae2099d..4285e68 100644 --- a/src/mainboard/ocp/deltalake/vpd.h +++ b/src/mainboard/ocp/deltalake/vpd.h @@ -32,4 +32,10 @@ #define FSP_DCI "fsp_dci_enable" /* 1 or 0: enable or disable DCI */ #define FSP_DCI_DEFAULT 0 /* Default value when the VPD variable is not found */ +/* Define uart io port for FSP/coreboot/payload */ +#define UART_IOPORT "uart_ioport" +#define UART_IOPORT_DEFAULT "0x2f8" + +int hex2int(const char *hexstr); + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55a85d6f137ef1aba95466e7b094740b685bf9bd Gerrit-Change-Number: 45408 Gerrit-PatchSet: 1 Gerrit-Owner: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cbfstool: Add support for platform "fixups" when modifying bootblock
by Julius Werner (Code Review) 12 Mar '21

12 Mar '21

Hello Patrick Georgi, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41122 to review the following change. Change subject: cbfstool: Add support for platform "fixups" when modifying bootblock ...................................................................... cbfstool: Add support for platform "fixups" when modifying bootblock To support the new CONFIG_CBFS_VERIFICATION feature, cbfstool needs to update the master hash embedded in the bootblock code every time it adds or removes a CBFS file. This can lead to problems on certain platforms where the bootblock needs to be specially wrapped in some platform-specific data structure so that the platform's masked ROM can recognize it. If that data structure contains any form of hash or signature of the bootblock code that is checked on every boot, it will no longer match if cbfstool modifies it after the fact. In general, we should always try to disable these kinds of features where possible (they're not super useful anyway). But for platforms where the hardware simply doesn't allow that, this patch introduces the concept of "platform fixups" to cbfstool. Whenever cbfstool finds a master hash anchor in a CBFS image, it will run all built-in "fixup probe" functions on that bootblock to check if it can recognize it as the wrapper format for a platform known to have such an issue. If so, it will register a corresponding fixup function that will run whenever it tries to write back modified data to that bootblock. The function can then modify any platform-specific headers as necessary. As first supported platform, this patch adds a fixup for Qualcomm platforms (specifically the header format used by sc7180), which recalculates the bootblock body hash originally added by util/qualcomm/createxbl.py. (Note that this feature is not intended to support platform-specific signature schemes like BootGuard directly in cbfstool. For anything that requires an actual secret key, it should be okay if the user needs to run a platform-specific signing tool on the final CBFS image before flashing. This feature is intended for the normal unsigned case (which on some platforms may be implemented as signing with a well-known key) so that on a board that is not "locked down" in any way the normal use case of manipulating an image with cbfstool and then directly flashing the output file stays working with CONFIG_CBFS_VERIFICATION.) Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I02a83a40f1d0009e6f9561ae5d2d9f37a510549a --- M util/cbfstool/Makefile.inc M util/cbfstool/cbfs.h M util/cbfstool/cbfstool.c M util/cbfstool/elf.h A util/cbfstool/platform_fixups.c 5 files changed, 131 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/41122/1 diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index e98b52e..1a5882f 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -22,6 +22,7 @@ cbfsobj += rmodule.o cbfsobj += xdr.o cbfsobj += partitioned_file.o +cbfsobj += platform_fixups.o # COMMONLIB cbfsobj += cbfs_private.o cbfsobj += fsp_relocate.o diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index 10b478c..0199d9c 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -78,4 +78,9 @@ void xdr_get_seg(struct cbfs_payload_segment *out, struct cbfs_payload_segment *in); +/* platform_fixups.c */ +typedef int (*platform_fixup_func)(struct buffer *buffer, size_t offset); +platform_fixup_func platform_fixups_probe(struct buffer *buffer, size_t offset, + const char *region_name); + #endif diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index bc07b6f..0b0fea7 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -108,6 +108,7 @@ const char *region; size_t offset; struct vb2_hash cbfs_hash; + platform_fixup_func fixup; }; static struct mh_cache *get_mh_cache(void) @@ -157,6 +158,8 @@ } mhc.cbfs_hash = anchor->cbfs_hash; mhc.offset = (void *)anchor - buffer_get(&buffer); + mhc.fixup = platform_fixups_probe(&buffer, mhc.offset, + mhc.region); return &mhc; } @@ -198,6 +201,8 @@ master_hash_anchor_fmap_hash(anchor), fmap_hash, vb2_digest_size(anchor->cbfs_hash.algo)); } + if (mhc->fixup && mhc->fixup(&buffer, mhc->offset) != 0) + return -1; if (!partitioned_file_write_region(param.image_file, &buffer)) return -1; return 0; diff --git a/util/cbfstool/elf.h b/util/cbfstool/elf.h index 11cee4f..9ba55a6 100644 --- a/util/cbfstool/elf.h +++ b/util/cbfstool/elf.h @@ -574,6 +574,8 @@ #define PF_W (1 << 1) /* Segment is writable */ #define PF_R (1 << 2) /* Segment is readable */ #define PF_MASKOS 0x0ff00000 /* OS-specific */ +#define PF_QC_SG_MASK 0x07000000 /* Qualcomm "segment" types */ +#define PF_QC_SG_HASH 0x02000000 /* Qualcomm hash segment */ #define PF_MASKPROC 0xf0000000 /* Processor-specific */ /* Legal values for note segment descriptor types for core files. */ diff --git a/util/cbfstool/platform_fixups.c b/util/cbfstool/platform_fixups.c new file mode 100644 index 0000000..f893a4d --- /dev/null +++ b/util/cbfstool/platform_fixups.c @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "cbfs.h" +#include "cbfs_sections.h" +#include "elfparsing.h" + +/* + * NOTE: This currently only implements support for MBN version 6 (as used by sc7180). Support + * for other MBN versions could probably be added but may require more parsing to tell them + * apart, and minor modifications (e.g. different hash algorithm). Add later as needed. + */ +static void *qualcomm_find_hash(struct buffer *in, size_t bb_offset, struct vb2_hash *real_hash) +{ + size_t search_end_size = MIN(0, buffer_size(in) - 32 * KiB); + struct buffer elf; + buffer_clone(&elf, in); + + /* To identify a Qualcomm image, first we find the GPT header... */ + while (buffer_size(&elf) > search_end_size && + !buffer_check_magic(&elf, "EFI PART", 8)) + buffer_seek(&elf, 512); + + /* ...then shortly afterwards there's an ELF header... */ + while (buffer_size(&elf) > search_end_size && + !buffer_check_magic(&elf, ELFMAG, 4)) + buffer_seek(&elf, 512); + + if (buffer_size(&elf) <= search_end_size) + return NULL; /* Doesn't seem to be a Qualcomm image. */ + + struct parsed_elf pelf; + if (parse_elf(&elf, &pelf, ELF_PARSE_PHDR)) + return NULL; /* Not an ELF -- guess not a Qualcomm MBN after all? */ + + /* Qualcomm stores an array of SHA-384 hashes in a special ELF segment. One special one + to start with, and then one for each segment in order. */ + void *bb_hash = NULL; + void *hashtable = NULL; + int i; + int bb_segment = -1; + for (i = 0; i < pelf.ehdr.e_phnum; i++) { + Elf64_Phdr *ph = &pelf.phdr[i]; + if ((ph->p_flags & PF_QC_SG_MASK) == PF_QC_SG_HASH) { + if ((int)ph->p_filesz != + (pelf.ehdr.e_phnum + 1) * VB2_SHA384_DIGEST_SIZE) { + ERROR("fixups: Qualcomm hash segment has wrong size!\n"); + goto destroy_elf; + } /* Found the table with the hashes -- store its address. */ + hashtable = buffer_get(&elf) + ph->p_offset; + } else if (bb_segment < 0 && ph->p_offset + ph->p_filesz < buffer_size(&elf) && + buffer_offset(&elf) + ph->p_offset <= bb_offset && + buffer_offset(&elf) + ph->p_offset + ph->p_filesz > bb_offset) { + bb_segment = i; /* Found the bootblock segment -- store its index. */ + } + } + if (!hashtable) /* ELF but no special QC hash segment -- guess not QC after all? */ + goto destroy_elf; + if (bb_segment < 0) { /* Can assume it's QC if we found the special segment. */ + ERROR("fixups: Cannot find bootblock code in Qualcomm MBN!\n"); + goto destroy_elf; + } + + /* Pass out the actual hash of the current bootblock segment in |real_hash|. */ + if (vb2_hash_calculate(buffer_get(&elf) + pelf.phdr[bb_segment].p_offset, + pelf.phdr[bb_segment].p_filesz, VB2_HASH_SHA384, real_hash)) { + ERROR("fixups: vboot digest error\n"); + goto destroy_elf; + } /* Return pointer to where the bootblock hash needs to go in Qualcomm's table. */ + bb_hash = hashtable + (bb_segment + 1) * VB2_SHA384_DIGEST_SIZE; + +destroy_elf: + parsed_elf_destroy(&pelf); + return bb_hash; +} + +static bool qualcomm_probe(struct buffer *buffer, size_t offset) +{ + struct vb2_hash real_hash; + void *table_hash = qualcomm_find_hash(buffer, offset, &real_hash); + if (!table_hash) + return false; + + if (memcmp(real_hash.raw, table_hash, VB2_SHA384_DIGEST_SIZE)) { + ERROR("fixups: Identified Qualcomm MBN, but existing hash doesn't match!\n"); + return false; + } + + return true; +} + +static int qualcomm_fixup(struct buffer *buffer, size_t offset) +{ + struct vb2_hash real_hash; + void *table_hash = qualcomm_find_hash(buffer, offset, &real_hash); + if (!table_hash) { + ERROR("fixups: Cannot find Qualcomm MBN headers anymore!\n"); + return -1; + } + + memcpy(table_hash, real_hash.raw, VB2_SHA384_DIGEST_SIZE); + INFO("fixups: Updated Qualcomm MBN header bootblock hash.\n"); + return 0; +} + +platform_fixup_func platform_fixups_probe(struct buffer *buffer, size_t offset, + const char *region_name) +{ + if (!strcmp(region_name, SECTION_NAME_BOOTBLOCK)) { + if (qualcomm_probe(buffer, offset)) + return qualcomm_fixup; + } else if (!strcmp(region_name, SECTION_NAME_PRIMARY_CBFS)) { + /* TODO: add fixups for primary CBFS bootblock platforms, if needed */ + } else { + ERROR("%s called for unexpected FMAP region %s!\n", __func__, region_name); + } + + return NULL; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02a83a40f1d0009e6f9561ae5d2d9f37a510549a Gerrit-Change-Number: 41122 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cbfstool: Support CONFIG_CBFS_VERIFICATION and master hash anchor
by Julius Werner (Code Review) 12 Mar '21

12 Mar '21

Hello Patrick Georgi, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41121 to review the following change. Change subject: cbfstool: Support CONFIG_CBFS_VERIFICATION and master hash anchor ...................................................................... cbfstool: Support CONFIG_CBFS_VERIFICATION and master hash anchor This patch adds support for the new CONFIG_CBFS_VERIFICATION feature to cbfstool. When CBFS verification is enabled, cbfstool must automatically add a hash attribute to every CBFS file it adds (with a handful of exceptions like bootblock and "header" pseudofiles that are never read by coreboot code itself). It must also automatically update the master hash that is embedded in the bootblock code. It will automatically find the master hash by scanning the bootblock for its magic number and use its presence to auto-detect whether CBFS verification is enabled for an image (and which hash algorithm to use). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I61a84add8654f60c683ef213b844a11b145a5cb7 --- M util/cbfstool/Makefile.inc A util/cbfstool/cbfs_glue.h M util/cbfstool/cbfs_sections.h M util/cbfstool/cbfstool.c 4 files changed, 243 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/41121/1 diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index 000ceb2..e98b52e 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -23,10 +23,8 @@ cbfsobj += xdr.o cbfsobj += partitioned_file.o # COMMONLIB -cbfsobj += cbfs.o +cbfsobj += cbfs_private.o cbfsobj += fsp_relocate.o -cbfsobj += mem_pool.o -cbfsobj += region.o # FMAP cbfsobj += fmap.o cbfsobj += kv_pair.o @@ -72,10 +70,6 @@ ifitobj += cbfs-mkstage.o ifitobj += cbfs-mkpayload.o ifitobj += rmodule.o -# COMMONLIB -ifitobj += cbfs.o -ifitobj += mem_pool.o -ifitobj += region.o # FMAP ifitobj += fmap.o ifitobj += kv_pair.o @@ -101,6 +95,7 @@ TOOLCPPFLAGS ?= -D_DEFAULT_SOURCE # memccpy() from string.h TOOLCPPFLAGS += -D_BSD_SOURCE -D_SVID_SOURCE # _DEFAULT_SOURCE for older glibc TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h +TOOLCPPFLAGS += -D_GNU_SOURCE # memmem() from string.h TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap TOOLCPPFLAGS += -I$(top)/util/cbfstool TOOLCPPFLAGS += -I$(objutil)/cbfstool @@ -207,9 +202,7 @@ # Tolerate lzma sdk warnings $(objutil)/cbfstool/LzmaEnc.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual # Tolerate commonlib warnings -$(objutil)/cbfstool/region.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual -$(objutil)/cbfstool/cbfs.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual -$(objutil)/cbfstool/mem_pool.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual +$(objutil)/cbfstool/cbfs_private.o: TOOLCFLAGS += -Wno-sign-compare # Tolerate lz4 warnings $(objutil)/cbfstool/lz4.o: TOOLCFLAGS += -Wno-missing-prototypes $(objutil)/cbfstool/lz4_wrapper.o: TOOLCFLAGS += -Wno-attributes diff --git a/util/cbfstool/cbfs_glue.h b/util/cbfstool/cbfs_glue.h new file mode 100644 index 0000000..11786be --- /dev/null +++ b/util/cbfstool/cbfs_glue.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _CBFS_GLUE_H_ +#define _CBFS_GLUE_H_ + +#include "cbfs_image.h" + +#define CBFS_ENABLE_HASHING 1 + +typedef const struct cbfs_image *cbfs_dev_t; + +static inline ssize_t cbfs_dev_read(cbfs_dev_t dev, void *buffer, size_t offset, size_t size) +{ + if (buffer_size(&dev->buffer) < offset || + buffer_size(&dev->buffer) - offset < size) + return -1; + + memcpy(buffer, buffer_get(&dev->buffer) + offset, size); + return size; +} + +static inline size_t cbfs_dev_size(cbfs_dev_t dev) +{ + return buffer_size(&dev->buffer); +} + +#endif /* _CBFS_GLUE_H_ */ diff --git a/util/cbfstool/cbfs_sections.h b/util/cbfstool/cbfs_sections.h index 3526f8d..d444cce 100644 --- a/util/cbfstool/cbfs_sections.h +++ b/util/cbfstool/cbfs_sections.h @@ -22,6 +22,7 @@ #define SECTION_NAME_FMAP "FMAP" #define SECTION_NAME_PRIMARY_CBFS "COREBOOT" +#define SECTION_NAME_BOOTBLOCK "BOOTBLOCK" #define SECTION_ANNOTATION_CBFS "CBFS" diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 6015603..bc07b6f 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -31,13 +31,13 @@ #include "cbfs_sections.h" #include "elfparsing.h" #include "partitioned_file.h" +#include <commonlib/bsd/cbfs_private.h> +#include <commonlib/bsd/master_hash.h> #include <commonlib/fsp.h> #include <commonlib/endian.h> #include <commonlib/helpers.h> #include <vboot_host.h> -#define SECTION_WITH_FIT_TABLE "BOOTBLOCK" - struct command { const char *name; const char *optstring; @@ -104,6 +104,144 @@ .u64val = -1, }; +struct mh_cache { + const char *region; + size_t offset; + struct vb2_hash cbfs_hash; +}; + +static struct mh_cache *get_mh_cache(void) +{ + static struct mh_cache mhc; + + if (mhc.region) + return &mhc; + + const struct fmap *fmap = partitioned_file_get_fmap(param.image_file); + if (!fmap) + goto no_master_hash; + + size_t offset, size; + struct buffer buffer; + if (fmap_find_area(fmap, SECTION_NAME_BOOTBLOCK)) { + if (!partitioned_file_read_region(&buffer, param.image_file, + SECTION_NAME_BOOTBLOCK)) + goto no_master_hash; + mhc.region = SECTION_NAME_BOOTBLOCK; + offset = 0; + size = buffer.size; + } else { + struct cbfs_image cbfs; + struct cbfs_file *bootblock; + if (!partitioned_file_read_region(&buffer, param.image_file, + SECTION_NAME_PRIMARY_CBFS)) + goto no_master_hash; + mhc.region = SECTION_NAME_PRIMARY_CBFS; + if (cbfs_image_from_buffer(&cbfs, &buffer, param.headeroffset)) + goto no_master_hash; + bootblock = cbfs_get_entry(&cbfs, "bootblock"); + if (!bootblock || ntohl(bootblock->type) != CBFS_TYPE_BOOTBLOCK) + goto no_master_hash; + offset = (void *)bootblock + ntohl(bootblock->offset) - + buffer_get(&cbfs.buffer); + size = ntohl(bootblock->len); + } + + struct master_hash_anchor *anchor = memmem(buffer_get(&buffer) + offset, + size, MASTER_HASH_ANCHOR_MAGIC, sizeof(anchor->magic)); + if (anchor) { + if (!vb2_digest_size(anchor->cbfs_hash.algo)) { + ERROR("Unknown CBFS master hash type: %d\n", + anchor->cbfs_hash.algo); + goto no_master_hash; + } + mhc.cbfs_hash = anchor->cbfs_hash; + mhc.offset = (void *)anchor - buffer_get(&buffer); + return &mhc; + } + +no_master_hash: + mhc.cbfs_hash.algo = VB2_HASH_INVALID; + mhc.region = (void *)-1; + return &mhc; +} + +static void update_and_info(const char *name, void *dst, void *src, size_t size) +{ + if (!memcmp(dst, src, size)) + return; + char *src_str = bintohex(src, size); + char *dst_str = bintohex(dst, size); + INFO("Updating %s from %s to %s\n", name, dst_str, src_str); + memcpy(dst, src, size); + free(src_str); + free(dst_str); +} + +static int update_anchor(struct mh_cache *mhc, uint8_t *fmap_hash) +{ + struct buffer buffer; + if (!partitioned_file_read_region(&buffer, param.image_file, + mhc->region)) + return -1; + struct master_hash_anchor *anchor = buffer_get(&buffer) + mhc->offset; + if (memcmp(anchor->magic, MASTER_HASH_ANCHOR_MAGIC, + sizeof(anchor->magic)) || + anchor->cbfs_hash.algo != mhc->cbfs_hash.algo) { + ERROR("Master hash anchor no longer where it used to be!\n"); + return -1; + } + update_and_info("CBFS master hash", anchor->cbfs_hash.raw, + mhc->cbfs_hash.raw, vb2_digest_size(anchor->cbfs_hash.algo)); + if (fmap_hash) { + update_and_info("FMAP hash", + master_hash_anchor_fmap_hash(anchor), fmap_hash, + vb2_digest_size(anchor->cbfs_hash.algo)); + } + if (!partitioned_file_write_region(param.image_file, &buffer)) + return -1; + return 0; + +} + +static int maybe_update_master_hash(struct cbfs_image *cbfs) +{ + if (strcmp(param.region_name, SECTION_NAME_PRIMARY_CBFS)) + return 0; /* Master hash only embedded in primary CBFS. */ + + struct mh_cache *mhc = get_mh_cache(); + if (mhc->cbfs_hash.algo == VB2_HASH_INVALID) + return 0; + + cb_err_t err = cbfs_walk(cbfs, NULL, NULL, &mhc->cbfs_hash, + CBFS_WALK_WRITEBACK_HASH); + if (err != CB_CBFS_NOT_FOUND) { + ERROR("Unexpected cbfs_walk() error %d\n", err); + return -1; + } + + return update_anchor(mhc, NULL); +} + +static int maybe_update_fmap_hash(void) +{ + if (strcmp(param.region_name, SECTION_NAME_BOOTBLOCK) && + strcmp(param.region_name, SECTION_NAME_FMAP) && + param.type != CBFS_TYPE_BOOTBLOCK) + return 0; /* FMAP and bootblock didn't change. */ + + struct mh_cache *mhc = get_mh_cache(); + if (mhc->cbfs_hash.algo == VB2_HASH_INVALID) + return 0; + + uint8_t fmap_hash[VB2_MAX_DIGEST_SIZE]; + const struct fmap *fmap = partitioned_file_get_fmap(param.image_file); + if (!fmap || vb2_digest_buffer((const void *)fmap, fmap_size(fmap), + mhc->cbfs_hash.algo, fmap_hash, sizeof(fmap_hash))) + return -1; + return update_anchor(mhc, fmap_hash); +} + static bool region_is_flashmap(const char *region) { return partitioned_file_region_check_magic(param.image_file, region, @@ -253,13 +391,21 @@ header = cbfs_create_file_header(CBFS_TYPE_RAW, buffer.size, name); + + enum vb2_hash_algorithm algo = get_mh_cache()->cbfs_hash.algo; + if (algo != VB2_HASH_INVALID) + if (cbfs_add_file_hash(header, &buffer, algo)) { + ERROR("couldn't add hash for '%s'\n", name); + goto done; + } + if (cbfs_add_entry(&image, &buffer, offset, header, 0) != 0) { ERROR("Failed to add %llu into ROM image as '%s'.\n", (long long unsigned)u64val, name); goto done; } - ret = 0; + ret = maybe_update_master_hash(&image); done: free(header); @@ -366,6 +512,7 @@ h->offset = htonl(offset); h->architecture = htonl(CBFS_ARCHITECTURE_UNKNOWN); + /* Never add a hash attribute to the master header. */ header = cbfs_create_file_header(CBFS_TYPE_CBFSHEADER, buffer_size(&buffer), name); if (cbfs_add_entry(&image, &buffer, 0, header, 0) != 0) { @@ -396,7 +543,7 @@ return 1; } - ret = 0; + ret = maybe_update_master_hash(&image); done: free(header); @@ -497,18 +644,32 @@ if (convert && convert(&buffer, &offset, header) != 0) { ERROR("Failed to parse file '%s'.\n", filename); - buffer_delete(&buffer); - return 1; + goto error; } - if (param.hash != VB2_HASH_INVALID) - if (cbfs_add_file_hash(header, &buffer, param.hash) == -1) { - ERROR("couldn't add hash for '%s'\n", name); - free(header); - buffer_delete(&buffer); - return 1; + /* Bootblock and CBFS header should never have file hashes. When adding + the bootblock it is important that we *don't* look up the master hash + yet (before it is added) or we'll cache an outdated result. */ + if (type != CBFS_TYPE_BOOTBLOCK && type != CBFS_TYPE_CBFSHEADER) { + enum vb2_hash_algorithm mh_algo = get_mh_cache()->cbfs_hash.algo; + if (mh_algo != VB2_HASH_INVALID && param.hash != mh_algo) { + if (param.hash == VB2_HASH_INVALID) { + param.hash = mh_algo; + } else { + ERROR("Cannot specify hash %s that's different from master hash algorithm %s\n", + vb2_get_hash_algorithm_name(param.hash), + vb2_get_hash_algorithm_name(mh_algo)); + goto error; + } } + if (param.hash != VB2_HASH_INVALID && + cbfs_add_file_hash(header, &buffer, param.hash) == -1) { + ERROR("couldn't add hash for '%s'\n", name); + goto error; + } + } + if (param.autogen_attr) { /* Add position attribute if assigned */ if (param.baseaddress_assigned || param.stage_xip) { @@ -573,14 +734,18 @@ -offset); if (cbfs_add_entry(&image, &buffer, offset, header, len_align) != 0) { ERROR("Failed to add '%s' into ROM image.\n", filename); - free(header); - buffer_delete(&buffer); - return 1; + goto error; } free(header); buffer_delete(&buffer); - return 0; + + return maybe_update_master_hash(&image) || maybe_update_fmap_hash(); + +error: + free(header); + buffer_delete(&buffer); + return 1; } static int cbfstool_convert_raw(struct buffer *buffer, @@ -925,7 +1090,7 @@ return 1; } - return 0; + return maybe_update_master_hash(&image); } static int cbfs_create(void) @@ -1096,6 +1261,33 @@ cbfs_print_directory(&image); } + if (verbose) { + struct mh_cache *mhc = get_mh_cache(); + if (mhc->cbfs_hash.algo == VB2_HASH_INVALID) + return 0; + + struct vb2_hash real_hash = { .algo = mhc->cbfs_hash.algo }; + cb_err_t err = cbfs_walk(&image, NULL, NULL, &real_hash, + CBFS_WALK_WRITEBACK_HASH); + if (err != CB_CBFS_NOT_FOUND) { + ERROR("Unexpected cbfs_walk() error %d\n", err); + return 1; + } + char *hash_str = bintohex(real_hash.raw, + vb2_digest_size(real_hash.algo)); + printf("[MASTER HASH]\t%s:%s", + vb2_get_hash_algorithm_name(real_hash.algo), hash_str); + if (!strcmp(param.region_name, SECTION_NAME_PRIMARY_CBFS)) { + if (!memcmp(mhc->cbfs_hash.raw, real_hash.raw, + vb2_digest_size(real_hash.algo))) + printf(":valid"); + else + printf(":invalid"); + } + printf("\n"); + free(hash_str); + } + return 0; } @@ -1194,7 +1386,8 @@ memcpy(param.image_region->data + offset, new_content.data, new_content.size); buffer_delete(&new_content); - return 0; + + return maybe_update_fmap_hash(); } static int cbfs_read(void) @@ -1454,7 +1647,7 @@ "Find a place for a file of that size\n" " layout [-w] " "List mutable (or, with -w, readable) image regions\n" - " print [-r image,regions] " + " print [-r image,regions] [-k] " "Show the contents of the ROM\n" " extract [-r image,regions] [-m ARCH] -n NAME -f FILE [-U] " "Extracts a file from ROM\n" -- To view, visit https://review.coreboot.org/c/coreboot/+/41121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61a84add8654f60c683ef213b844a11b145a5cb7 Gerrit-Change-Number: 41121 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 40

Change in coreboot[master]: soc/intel/broadwell/memmap.c: Use Haswell implementation
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46992 ) Change subject: soc/intel/broadwell/memmap.c: Use Haswell implementation ...................................................................... soc/intel/broadwell/memmap.c: Use Haswell implementation Change-Id: I0752418cdf0bf39241e1c798b7aeb1a8b137c6f8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/memmap.c 1 file changed, 40 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/46992/1 diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 8b1567e..7eb2d42 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -4,45 +4,66 @@ #define __SIMPLE_DEVICE__ #include <arch/romstage.h> -#include <cbmem.h> +#include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> -#include <device/pci.h> #include <device/pci_ops.h> -#include <stdint.h> +#include <cbmem.h> +#include <security/intel/txt/txt_platform.h> +#include <security/intel/txt/txt_register.h> +#include <types.h> #include "haswell.h" -static uintptr_t dpr_region_start(void) +static uintptr_t northbridge_get_tseg_base(void) +{ + return ALIGN_DOWN(pci_read_config32(HOST_BRIDGE, TSEG), 1 * MiB); +} + +static uintptr_t northbridge_get_tseg_limit(void) +{ + return ALIGN_DOWN(pci_read_config32(HOST_BRIDGE, BGSM), 1 * MiB); +} + +union dpr_register txt_get_chipset_dpr(void) +{ + return (union dpr_register) { .raw = pci_read_config32(HOST_BRIDGE, DPR) }; +} + +/* + * Return the topmost memory address below 4 GiB available for general + * use, from software's view of memory. Do not confuse this with TOLUD, + * which applies to the DRAM as viewed by the memory controller itself. + */ +static uintptr_t top_of_low_usable_memory(void) { /* - * Base of DPR is top of usable DRAM below 4GiB. The register has - * 1 MiB alignment and reports the TOP of the range, the base - * must be calculated from the size in MiB in bits 11:4. + * Base of DPR is top of usable DRAM below 4 GiB. However, DPR + * isn't always enabled. Unlike most memory map registers, the + * DPR register stores top of DPR instead of its base address. + * Top of DPR is R/O, and mirrored from TSEG base by hardware. */ - uintptr_t dpr = pci_read_config32(HOST_BRIDGE, DPR); - uintptr_t tom = ALIGN_DOWN(dpr, 1 * MiB); + uintptr_t tolum = northbridge_get_tseg_base(); + + const union dpr_register dpr = txt_get_chipset_dpr(); /* Subtract DMA Protected Range size if enabled */ - if (dpr & DPR_EPM) - tom -= (dpr & DPR_SIZE_MASK) << 16; + if (dpr.epm) + tolum -= dpr.size * MiB; - return tom; + return tolum; } void *cbmem_top_chipset(void) { - return (void *) dpr_region_start(); + return (void *)top_of_low_usable_memory(); } void smm_region(uintptr_t *start, size_t *size) { - uintptr_t tseg = pci_read_config32(HOST_BRIDGE, TSEG); - uintptr_t bgsm = pci_read_config32(HOST_BRIDGE, BGSM); + *start = northbridge_get_tseg_base(); + *size = northbridge_get_tseg_limit(); - tseg = ALIGN_DOWN(tseg, 1 * MiB); - bgsm = ALIGN_DOWN(bgsm, 1 * MiB); - *start = tseg; - *size = bgsm - tseg; + *size -= *start; } void fill_postcar_frame(struct postcar_frame *pcf) -- To view, visit https://review.coreboot.org/c/coreboot/+/46992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0752418cdf0bf39241e1c798b7aeb1a8b137c6f8 Gerrit-Change-Number: 46992 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: [WIP] move broadwell pch as lynxpoint-lp
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47047 ) Change subject: [WIP] move broadwell pch as lynxpoint-lp ...................................................................... [WIP] move broadwell pch as lynxpoint-lp Change-Id: I5b55f90e6366b83c75834d7ef57ff2ebdce972b6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/purism/librem_bdw/acpi_tables.c M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/dsdt.asl M src/mainboard/purism/librem_bdw/gpio.c M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/finalize.c M src/soc/intel/broadwell/gma.c M src/soc/intel/broadwell/ramstage.c M src/soc/intel/broadwell/refcode.c M src/soc/intel/broadwell/report_platform.c M src/soc/intel/broadwell/romstage.c A src/southbridge/intel/lynxpoint_lp/Kconfig R src/southbridge/intel/lynxpoint_lp/Makefile.inc R src/southbridge/intel/lynxpoint_lp/acpi/globalnvs.asl R src/southbridge/intel/lynxpoint_lp/adsp.c R src/southbridge/intel/lynxpoint_lp/adsp.h R src/southbridge/intel/lynxpoint_lp/bootblock.c R src/southbridge/intel/lynxpoint_lp/chip.h R src/southbridge/intel/lynxpoint_lp/early_pch.c R src/southbridge/intel/lynxpoint_lp/ehci.h R src/southbridge/intel/lynxpoint_lp/elog.c R src/southbridge/intel/lynxpoint_lp/fadt.c R src/southbridge/intel/lynxpoint_lp/finalize.c R src/southbridge/intel/lynxpoint_lp/gpio.c R src/southbridge/intel/lynxpoint_lp/gpio.h R src/southbridge/intel/lynxpoint_lp/hda.c R src/southbridge/intel/lynxpoint_lp/iobp.c R src/southbridge/intel/lynxpoint_lp/iobp.h R src/southbridge/intel/lynxpoint_lp/lpc.c R src/southbridge/intel/lynxpoint_lp/lpc.h R src/southbridge/intel/lynxpoint_lp/me.c R src/southbridge/intel/lynxpoint_lp/me.h R src/southbridge/intel/lynxpoint_lp/me_status.c R src/southbridge/intel/lynxpoint_lp/nvs.h R src/southbridge/intel/lynxpoint_lp/pch.c R src/southbridge/intel/lynxpoint_lp/pch.h R src/southbridge/intel/lynxpoint_lp/pcie.c R src/southbridge/intel/lynxpoint_lp/pm.h R src/southbridge/intel/lynxpoint_lp/pmutil.c R src/southbridge/intel/lynxpoint_lp/power_state.c R src/southbridge/intel/lynxpoint_lp/rcba.h R src/southbridge/intel/lynxpoint_lp/sata.c R src/southbridge/intel/lynxpoint_lp/sata.h R src/southbridge/intel/lynxpoint_lp/serialio.c R src/southbridge/intel/lynxpoint_lp/serialio.h R src/southbridge/intel/lynxpoint_lp/smbus.c R src/southbridge/intel/lynxpoint_lp/smbus.h R src/southbridge/intel/lynxpoint_lp/smi.c R src/southbridge/intel/lynxpoint_lp/smihandler.c R src/southbridge/intel/lynxpoint_lp/spi.h R src/southbridge/intel/lynxpoint_lp/uart.c R src/southbridge/intel/lynxpoint_lp/usb_debug.c R src/southbridge/intel/lynxpoint_lp/usb_ehci.c R src/southbridge/intel/lynxpoint_lp/usb_xhci.c R src/southbridge/intel/lynxpoint_lp/xhci.h 59 files changed, 121 insertions(+), 106 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/47047/1 diff --git a/src/mainboard/purism/librem_bdw/acpi_tables.c b/src/mainboard/purism/librem_bdw/acpi_tables.c index 19502ed..c3827e5 100644 --- a/src/mainboard/purism/librem_bdw/acpi_tables.c +++ b/src/mainboard/purism/librem_bdw/acpi_tables.c @@ -2,7 +2,7 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> -#include <soc/intel/broadwell/pch/nvs.h> +#include <southbridge/intel/lynxpoint_lp/nvs.h> void acpi_create_gnvs(struct global_nvs *gnvs) { diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index 0575a98..84131b1 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -27,7 +27,7 @@ device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - chip soc/intel/broadwell/pch + chip southbridge/intel/lynxpoint_lp # EC host command ranges are in 0x380-0x383 & 0x80-0x8f register "gen1_dec" = "0x00000381" register "gen2_dec" = "0x000c0081" diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl index f0c67bad..669fec9 100644 --- a/src/mainboard/purism/librem_bdw/dsdt.asl +++ b/src/mainboard/purism/librem_bdw/dsdt.asl @@ -13,7 +13,7 @@ #include <soc/intel/broadwell/acpi/platform.asl> /* Global NVS and variables */ - #include <soc/intel/broadwell/pch/acpi/globalnvs.asl> + #include <southbridge/intel/lynxpoint_lp/acpi/globalnvs.asl> /* CPU */ #include <cpu/intel/common/acpi/cpu.asl> diff --git a/src/mainboard/purism/librem_bdw/gpio.c b/src/mainboard/purism/librem_bdw/gpio.c index 4ef248a..d44cc20 100644 --- a/src/mainboard/purism/librem_bdw/gpio.c +++ b/src/mainboard/purism/librem_bdw/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/intel/broadwell/pch/gpio.h> +#include <southbridge/intel/lynxpoint_lp/gpio.h> const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_INPUT, /* 0 */ diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb index 256077c..b05bbef 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/broadwell device domain 0 on - chip soc/intel/broadwell/pch + chip southbridge/intel/lynxpoint_lp # Port 0 is HDD # Port 3 is M.2 NGFF register "sata_port_map" = "0x9" diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb index d88c19c..21acfe6 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/broadwell device domain 0 on - chip soc/intel/broadwell/pch + chip southbridge/intel/lynxpoint_lp # Port 0 is HDD # Port 1 is M.2 NGFF register "sata_port_map" = "0x3" diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 02cd1c2..c03b034 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -5,55 +5,16 @@ if SOC_INTEL_BROADWELL -config INTEL_LYNXPOINT_LP - bool - default y if SOC_INTEL_BROADWELL - config SOC_SPECIFIC_OPTIONS def_bool y - select ACPI_INTEL_HARDWARE_SLEEP_VALUES select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT select CPU_INTEL_HASWELL - select HAVE_SMI_HANDLER - select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_RESET - select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT - select SOUTHBRIDGE_INTEL_COMMON_RTC - select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 - select HAVE_USBDEBUG - select IOAPIC - select REG_SCRIPT - select RTC - select SPI_FLASH - select SOC_INTEL_COMMON - select INTEL_DESCRIPTOR_MODE_CAPABLE - select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT select INTEL_GMA_ACPI - select HAVE_POWER_STATE_AFTER_FAILURE - select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE - -config PCIEXP_ASPM - bool - default y - -config PCIEXP_AER - bool - default y - -config PCIEXP_COMMON_CLOCK - bool - default y - -config PCIEXP_CLK_PM - bool - default y - -config PCIEXP_L1_SUB_STATE - bool - default y + select REG_SCRIPT + select SOC_INTEL_COMMON + select SOUTHBRIDGE_INTEL_LYNXPOINT_LP config BROADWELL_VBOOT_IN_BOOTBLOCK depends on VBOOT @@ -162,17 +123,6 @@ default 0xd6000000 depends on INTEL_PCH_UART_CONSOLE -config EHCI_BAR - hex - default 0xd8000000 - -config SERIRQ_CONTINUOUS_MODE - bool - default y - help - If you set this option to y, the serial IRQ machine will be - operated in continuous mode. - config HAVE_REFCODE_BLOB depends on ARCH_X86 bool "An external reference code blob should be put into cbfs." diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 3f06913..b8c52f4 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -1,7 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) -subdirs-y += pch - bootblock-y += bootblock.c romstage-y += early_init.c diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 300b7e7..cfaf6a9 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -18,8 +18,8 @@ #include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/gnvs.h> #include <soc/intel/broadwell/memmap.h> -#include <soc/intel/broadwell/pch/pch.h> -#include <soc/intel/broadwell/pch/pm.h> +#include <southbridge/intel/lynxpoint_lp/pch.h> +#include <southbridge/intel/lynxpoint_lp/pm.h> #include <soc/intel/broadwell/chip.h> #include "haswell.h" diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 6c6dc20..e2630d1 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -6,7 +6,7 @@ #include <device/pci_ops.h> #include <soc/intel/broadwell/haswell.h> -#include "pch/pch.h" +#include <southbridge/intel/lynxpoint_lp/pch.h> /* * 16.6 System Agent Configuration Locking diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index 0c881c2..51e1ad2 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -16,7 +16,7 @@ #include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/libgfxinit.h> #include <drivers/intel/gma/opregion.h> -#include <soc/intel/broadwell/pch/pm.h> +#include <southbridge/intel/lynxpoint_lp/pm.h> #include <soc/intel/broadwell/chip.h> #include <security/vboot/vbnv.h> #include <types.h> diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index 670b0f5..28c8d60 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -5,10 +5,10 @@ #include <console/console.h> #include <device/device.h> #include <string.h> -#include <soc/intel/broadwell/pch/pm.h> #include <soc/intel/broadwell/chip.h> -#include <soc/intel/broadwell/pch/nvs.h> +#include <southbridge/intel/lynxpoint_lp/nvs.h> +#include <southbridge/intel/lynxpoint_lp/pm.h> #include "ramstage.h" /* Save bit index for PM1_STS and GPE_STS for ACPI _SWS */ diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index 4ec1fc2..d066893 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -8,7 +8,7 @@ #include <program_loading.h> #include <rmodule.h> #include <stage_cache.h> -#include <soc/intel/broadwell/pch/pm.h> +#include <southbridge/intel/lynxpoint_lp/pm.h> #include "ramstage.h" #include "pei_data.h" diff --git a/src/soc/intel/broadwell/report_platform.c b/src/soc/intel/broadwell/report_platform.c index b02b234..e336e76 100644 --- a/src/soc/intel/broadwell/report_platform.c +++ b/src/soc/intel/broadwell/report_platform.c @@ -11,7 +11,7 @@ #include <soc/intel/broadwell/romstage.h> #include <soc/intel/broadwell/haswell.h> -#include "pch/pch.h" +#include <southbridge/intel/lynxpoint_lp/pch.h> /* FIXME: Needs an update */ static struct { diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c index c47d60f..cfae2c2 100644 --- a/src/soc/intel/broadwell/romstage.c +++ b/src/soc/intel/broadwell/romstage.c @@ -8,7 +8,6 @@ #include <cpu/intel/haswell/haswell.h> #include <elog.h> #include <romstage_handoff.h> -#include <soc/intel/broadwell/pch/pm.h> #include <soc/intel/broadwell/pei_wrapper.h> #include <soc/intel/broadwell/romstage.h> #include <stdint.h> @@ -16,9 +15,10 @@ #include "haswell.h" #include "pei_data.h" -#include "pch/gpio.h" -#include "pch/me.h" -#include "pch/pch.h" +#include <southbridge/intel/lynxpoint_lp/gpio.h> +#include <southbridge/intel/lynxpoint_lp/me.h> +#include <southbridge/intel/lynxpoint_lp/pch.h> +#include <southbridge/intel/lynxpoint_lp/pm.h> #include "raminit.h" /* Entry from cpu/intel/car/romstage.c. */ diff --git a/src/southbridge/intel/lynxpoint_lp/Kconfig b/src/southbridge/intel/lynxpoint_lp/Kconfig new file mode 100644 index 0000000..fb869961 --- /dev/null +++ b/src/southbridge/intel/lynxpoint_lp/Kconfig @@ -0,0 +1,62 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config SOUTHBRIDGE_INTEL_LYNXPOINT_LP + bool + +if SOUTHBRIDGE_INTEL_LYNXPOINT_LP + +config INTEL_LYNXPOINT_LP + bool + default y if SOUTHBRIDGE_INTEL_LYNXPOINT_LP + +config SOUTH_BRIDGE_OPTIONS + def_bool y + select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select HAVE_SMI_HANDLER + select HAVE_USBDEBUG + select IOAPIC + select INTEL_DESCRIPTOR_MODE_CAPABLE + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT + select SOUTHBRIDGE_INTEL_COMMON_RTC + select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 + select RTC + select SPI_FLASH + +config EHCI_BAR + hex + default 0xd8000000 + +config SERIRQ_CONTINUOUS_MODE + bool + default n + help + If you set this option to y, the serial IRQ machine will be + operated in continuous mode. + +config PCIEXP_ASPM + bool + default y + +config PCIEXP_AER + bool + default y + +config PCIEXP_COMMON_CLOCK + bool + default y + +config PCIEXP_CLK_PM + bool + default y + +config PCIEXP_L1_SUB_STATE + bool + default y + +endif diff --git a/src/soc/intel/broadwell/pch/Makefile.inc b/src/southbridge/intel/lynxpoint_lp/Makefile.inc similarity index 93% rename from src/soc/intel/broadwell/pch/Makefile.inc rename to src/southbridge/intel/lynxpoint_lp/Makefile.inc index 1ebe324f..6d18c9f 100644 --- a/src/soc/intel/broadwell/pch/Makefile.inc +++ b/src/southbridge/intel/lynxpoint_lp/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT_LP),y) + bootblock-y += bootblock.c ramstage-y += adsp.c @@ -37,3 +39,5 @@ smm-y += usb_xhci.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c + +endif diff --git a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint_lp/acpi/globalnvs.asl similarity index 100% rename from src/soc/intel/broadwell/pch/acpi/globalnvs.asl rename to src/southbridge/intel/lynxpoint_lp/acpi/globalnvs.asl diff --git a/src/soc/intel/broadwell/pch/adsp.c b/src/southbridge/intel/lynxpoint_lp/adsp.c similarity index 96% rename from src/soc/intel/broadwell/pch/adsp.c rename to src/southbridge/intel/lynxpoint_lp/adsp.c index 03da7d2..fa7e2d9 100644 --- a/src/soc/intel/broadwell/pch/adsp.c +++ b/src/southbridge/intel/lynxpoint_lp/adsp.c @@ -7,9 +7,9 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/mmio.h> -#include <soc/intel/broadwell/pch/chip.h> #include "adsp.h" +#include "chip.h" #include "iobp.h" #include "nvs.h" #include "pch.h" @@ -17,7 +17,7 @@ static void adsp_init(struct device *dev) { - const struct soc_intel_broadwell_pch_config *config = config_of(dev); + const struct southbridge_intel_lynxpoint_lp_config *config = config_of(dev); struct resource *bar0, *bar1; u32 tmp32; diff --git a/src/soc/intel/broadwell/pch/adsp.h b/src/southbridge/intel/lynxpoint_lp/adsp.h similarity index 100% rename from src/soc/intel/broadwell/pch/adsp.h rename to src/southbridge/intel/lynxpoint_lp/adsp.h diff --git a/src/soc/intel/broadwell/pch/bootblock.c b/src/southbridge/intel/lynxpoint_lp/bootblock.c similarity index 98% rename from src/soc/intel/broadwell/pch/bootblock.c rename to src/southbridge/intel/lynxpoint_lp/bootblock.c index 3fe2568..dc7df72 100644 --- a/src/soc/intel/broadwell/pch/bootblock.c +++ b/src/southbridge/intel/lynxpoint_lp/bootblock.c @@ -3,12 +3,12 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> #include <soc/intel/broadwell/memmap.h> -#include <soc/intel/broadwell/pch/pm.h> #include <soc/intel/broadwell/romstage.h> #include <southbridge/intel/common/early_spi.h> #include "lpc.h" #include "pch.h" +#include "pm.h" #include "rcba.h" #include "spi.h" diff --git a/src/soc/intel/broadwell/pch/chip.h b/src/southbridge/intel/lynxpoint_lp/chip.h similarity index 96% rename from src/soc/intel/broadwell/pch/chip.h rename to src/southbridge/intel/lynxpoint_lp/chip.h index 2164a31..470ef23 100644 --- a/src/soc/intel/broadwell/pch/chip.h +++ b/src/southbridge/intel/lynxpoint_lp/chip.h @@ -5,7 +5,7 @@ #include <stdint.h> -struct soc_intel_broadwell_pch_config { +struct southbridge_intel_lynxpoint_lp_config { /* GPE configuration */ uint32_t gpe0_en_1; uint32_t gpe0_en_2; diff --git a/src/soc/intel/broadwell/pch/early_pch.c b/src/southbridge/intel/lynxpoint_lp/early_pch.c similarity index 93% rename from src/soc/intel/broadwell/pch/early_pch.c rename to src/southbridge/intel/lynxpoint_lp/early_pch.c index 4f59397..d9c927a 100644 --- a/src/soc/intel/broadwell/pch/early_pch.c +++ b/src/southbridge/intel/lynxpoint_lp/early_pch.c @@ -5,11 +5,11 @@ #include <device/pci_ops.h> #include <device/smbus_host.h> #include <soc/intel/broadwell/memmap.h> -#include <soc/intel/broadwell/pch/pm.h> -#include <soc/intel/broadwell/pch/chip.h> +#include "chip.h" #include "lpc.h" #include "pch.h" +#include "pm.h" #include "rcba.h" #include "smbus.h" @@ -56,7 +56,7 @@ if (!dev || !dev->chip_info) return; - const struct soc_intel_broadwell_pch_config *config = dev->chip_info; + const struct southbridge_intel_lynxpoint_lp_config *config = dev->chip_info; pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); diff --git a/src/soc/intel/broadwell/pch/ehci.h b/src/southbridge/intel/lynxpoint_lp/ehci.h similarity index 100% rename from src/soc/intel/broadwell/pch/ehci.h rename to src/southbridge/intel/lynxpoint_lp/ehci.h diff --git a/src/soc/intel/broadwell/pch/elog.c b/src/southbridge/intel/lynxpoint_lp/elog.c similarity index 100% rename from src/soc/intel/broadwell/pch/elog.c rename to src/southbridge/intel/lynxpoint_lp/elog.c diff --git a/src/soc/intel/broadwell/pch/fadt.c b/src/southbridge/intel/lynxpoint_lp/fadt.c similarity index 98% rename from src/soc/intel/broadwell/pch/fadt.c rename to src/southbridge/intel/lynxpoint_lp/fadt.c index 39e3508..83242d3 100644 --- a/src/soc/intel/broadwell/pch/fadt.c +++ b/src/southbridge/intel/lynxpoint_lp/fadt.c @@ -3,8 +3,9 @@ #include <acpi/acpi.h> #include <cpu/x86/smm.h> #include <soc/intel/broadwell/memmap.h> -#include <soc/intel/broadwell/pch/pm.h> + #include "chip.h" +#include "pm.h" void acpi_fill_fadt(acpi_fadt_t *fadt) { diff --git a/src/soc/intel/broadwell/pch/finalize.c b/src/southbridge/intel/lynxpoint_lp/finalize.c similarity index 100% rename from src/soc/intel/broadwell/pch/finalize.c rename to src/southbridge/intel/lynxpoint_lp/finalize.c diff --git a/src/soc/intel/broadwell/pch/gpio.c b/src/southbridge/intel/lynxpoint_lp/gpio.c similarity index 98% rename from src/soc/intel/broadwell/pch/gpio.c rename to src/southbridge/intel/lynxpoint_lp/gpio.c index d61670d..dd480c3 100644 --- a/src/soc/intel/broadwell/pch/gpio.c +++ b/src/southbridge/intel/lynxpoint_lp/gpio.c @@ -5,9 +5,9 @@ #include <device/device.h> #include <device/pci.h> #include <soc/intel/broadwell/memmap.h> -#include <soc/intel/broadwell/pch/pm.h> #include "gpio.h" +#include "pm.h" /* * This function will return a number that indicates which PIRQ diff --git a/src/soc/intel/broadwell/pch/gpio.h b/src/southbridge/intel/lynxpoint_lp/gpio.h similarity index 100% rename from src/soc/intel/broadwell/pch/gpio.h rename to src/southbridge/intel/lynxpoint_lp/gpio.h diff --git a/src/soc/intel/broadwell/pch/hda.c b/src/southbridge/intel/lynxpoint_lp/hda.c similarity index 100% rename from src/soc/intel/broadwell/pch/hda.c rename to src/southbridge/intel/lynxpoint_lp/hda.c diff --git a/src/soc/intel/broadwell/pch/iobp.c b/src/southbridge/intel/lynxpoint_lp/iobp.c similarity index 100% rename from src/soc/intel/broadwell/pch/iobp.c rename to src/southbridge/intel/lynxpoint_lp/iobp.c diff --git a/src/soc/intel/broadwell/pch/iobp.h b/src/southbridge/intel/lynxpoint_lp/iobp.h similarity index 100% rename from src/soc/intel/broadwell/pch/iobp.h rename to src/southbridge/intel/lynxpoint_lp/iobp.h diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/southbridge/intel/lynxpoint_lp/lpc.c similarity index 97% rename from src/soc/intel/broadwell/pch/lpc.c rename to src/southbridge/intel/lynxpoint_lp/lpc.c index d62a94c..4824e4c 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/southbridge/intel/lynxpoint_lp/lpc.c @@ -21,13 +21,13 @@ #include <soc/intel/broadwell/memmap.h> #include <soc/intel/broadwell/haswell.h> -#include <soc/intel/broadwell/pch/pm.h> -#include <soc/intel/broadwell/pch/chip.h> +#include "chip.h" #include "lpc.h" #include "iobp.h" #include "nvs.h" #include "pch.h" +#include "pm.h" #include "rcba.h" #include "gpio.h" @@ -173,7 +173,7 @@ printk(BIOS_INFO, "Set power %s after power failure.\n", state); if (dev->chip_info) { - const struct soc_intel_broadwell_pch_config *config = dev->chip_info; + const struct southbridge_intel_lynxpoint_lp_config *config = dev->chip_info; /* GPE setup based on device tree configuration */ enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, @@ -337,7 +337,7 @@ static void pch_init_deep_sx(struct device *dev) { - const struct soc_intel_broadwell_pch_config *config = dev->chip_info; + const struct southbridge_intel_lynxpoint_lp_config *config = dev->chip_info; if (!config) return; @@ -587,7 +587,7 @@ /* LPC Generic IO Decode range. */ if (dev->chip_info) { - const struct soc_intel_broadwell_pch_config *config = dev->chip_info; + const struct southbridge_intel_lynxpoint_lp_config *config = dev->chip_info; pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC); pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC); pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC); diff --git a/src/soc/intel/broadwell/pch/lpc.h b/src/southbridge/intel/lynxpoint_lp/lpc.h similarity index 100% rename from src/soc/intel/broadwell/pch/lpc.h rename to src/southbridge/intel/lynxpoint_lp/lpc.h diff --git a/src/soc/intel/broadwell/pch/me.c b/src/southbridge/intel/lynxpoint_lp/me.c similarity index 99% rename from src/soc/intel/broadwell/pch/me.c rename to src/southbridge/intel/lynxpoint_lp/me.c index 3b27b91..89ecca6 100644 --- a/src/soc/intel/broadwell/pch/me.c +++ b/src/southbridge/intel/lynxpoint_lp/me.c @@ -20,13 +20,13 @@ #include <string.h> #include <delay.h> #include <elog.h> -#include <soc/intel/broadwell/pch/chip.h> #if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif +#include "chip.h" #include "me.h" #include "pch.h" #include "rcba.h" @@ -948,7 +948,7 @@ /* Check whether ME is present and do basic init */ static void intel_me_init(struct device *dev) { - const struct soc_intel_broadwell_pch_config *config = config_of(dev); + const struct southbridge_intel_lynxpoint_lp_config *config = config_of(dev); me_bios_path path = intel_me_path(dev); me_bios_payload mbp_data; int mbp_ret; diff --git a/src/soc/intel/broadwell/pch/me.h b/src/southbridge/intel/lynxpoint_lp/me.h similarity index 100% rename from src/soc/intel/broadwell/pch/me.h rename to src/southbridge/intel/lynxpoint_lp/me.h diff --git a/src/soc/intel/broadwell/pch/me_status.c b/src/southbridge/intel/lynxpoint_lp/me_status.c similarity index 100% rename from src/soc/intel/broadwell/pch/me_status.c rename to src/southbridge/intel/lynxpoint_lp/me_status.c diff --git a/src/soc/intel/broadwell/pch/nvs.h b/src/southbridge/intel/lynxpoint_lp/nvs.h similarity index 100% rename from src/soc/intel/broadwell/pch/nvs.h rename to src/southbridge/intel/lynxpoint_lp/nvs.h diff --git a/src/soc/intel/broadwell/pch/pch.c b/src/southbridge/intel/lynxpoint_lp/pch.c similarity index 96% rename from src/soc/intel/broadwell/pch/pch.c rename to src/southbridge/intel/lynxpoint_lp/pch.c index b4315b6..882dabe 100644 --- a/src/soc/intel/broadwell/pch/pch.c +++ b/src/southbridge/intel/lynxpoint_lp/pch.c @@ -165,7 +165,7 @@ } } -static void broadwell_pch_enable_dev(struct device *dev) +static void pch_enable(struct device *dev) { if (dev->path.type != DEVICE_PATH_PCI) return; @@ -196,9 +196,9 @@ } } -struct chip_operations soc_intel_broadwell_pch_ops = { - CHIP_NAME("Intel Broadwell PCH") - .enable_dev = &broadwell_pch_enable_dev, +struct chip_operations southbridge_intel_lynxpoint_lp_ops = { + CHIP_NAME("Intel Lynx Point LP PCH") + .enable_dev = pch_enable, }; #endif diff --git a/src/soc/intel/broadwell/pch/pch.h b/src/southbridge/intel/lynxpoint_lp/pch.h similarity index 100% rename from src/soc/intel/broadwell/pch/pch.h rename to src/southbridge/intel/lynxpoint_lp/pch.h diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/southbridge/intel/lynxpoint_lp/pcie.c similarity index 98% rename from src/soc/intel/broadwell/pch/pcie.c rename to src/southbridge/intel/lynxpoint_lp/pcie.c index 8bf7d3d..1a78bab 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/southbridge/intel/lynxpoint_lp/pcie.c @@ -7,11 +7,11 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "rcba.h" -#include <soc/intel/broadwell/pch/chip.h> #include <delay.h> #include <cpu/intel/haswell/haswell.h> + +#include "chip.h" #include "gpio.h" #include "iobp.h" #include "pch.h" @@ -121,7 +121,7 @@ root_port_config_update_gbe_port(); pci_or_config8(dev, 0xe2, 3 << 4); - const struct soc_intel_broadwell_pch_config *config = config_of(dev); + const struct southbridge_intel_lynxpoint_lp_config *config = config_of(dev); rpc.coalesce = config->pcie_port_coalesce; } @@ -435,7 +435,7 @@ static void pch_pcie_early(struct device *dev) { - const struct soc_intel_broadwell_pch_config *config = config_of(dev); + const struct southbridge_intel_lynxpoint_lp_config *config = config_of(dev); int do_aspm = 0; int rp = root_port_number(dev); diff --git a/src/soc/intel/broadwell/pch/pm.h b/src/southbridge/intel/lynxpoint_lp/pm.h similarity index 100% rename from src/soc/intel/broadwell/pch/pm.h rename to src/southbridge/intel/lynxpoint_lp/pm.h diff --git a/src/soc/intel/broadwell/pch/pmutil.c b/src/southbridge/intel/lynxpoint_lp/pmutil.c similarity index 99% rename from src/soc/intel/broadwell/pch/pmutil.c rename to src/southbridge/intel/lynxpoint_lp/pmutil.c index e8af6cc..8ba8739 100644 --- a/src/soc/intel/broadwell/pch/pmutil.c +++ b/src/southbridge/intel/lynxpoint_lp/pmutil.c @@ -14,13 +14,13 @@ #include <device/pci_def.h> #include <console/console.h> #include <soc/intel/broadwell/memmap.h> -#include <soc/intel/broadwell/pch/pm.h> #include <security/vboot/vbnv.h> #include <stdint.h> #include "gpio.h" #include "lpc.h" #include "pch.h" +#include "pm.h" static inline uint16_t get_gpiobase(void) { diff --git a/src/soc/intel/broadwell/pch/power_state.c b/src/southbridge/intel/lynxpoint_lp/power_state.c similarity index 98% rename from src/soc/intel/broadwell/pch/power_state.c rename to src/southbridge/intel/lynxpoint_lp/power_state.c index a39822a..0078b04 100644 --- a/src/soc/intel/broadwell/pch/power_state.c +++ b/src/southbridge/intel/lynxpoint_lp/power_state.c @@ -9,7 +9,6 @@ #include <device/pci_def.h> #include <string.h> #include <soc/intel/broadwell/memmap.h> -#include <soc/intel/broadwell/pch/pm.h> #include <soc/intel/broadwell/romstage.h> #include "lpc.h" diff --git a/src/soc/intel/broadwell/pch/rcba.h b/src/southbridge/intel/lynxpoint_lp/rcba.h similarity index 100% rename from src/soc/intel/broadwell/pch/rcba.h rename to src/southbridge/intel/lynxpoint_lp/rcba.h diff --git a/src/soc/intel/broadwell/pch/sata.c b/src/southbridge/intel/lynxpoint_lp/sata.c similarity index 96% rename from src/soc/intel/broadwell/pch/sata.c rename to src/southbridge/intel/lynxpoint_lp/sata.c index e9d70f1..c33088b 100644 --- a/src/soc/intel/broadwell/pch/sata.c +++ b/src/southbridge/intel/lynxpoint_lp/sata.c @@ -8,8 +8,8 @@ #include <device/pci_ids.h> #include <delay.h> #include <southbridge/intel/common/abar.h> -#include <soc/intel/broadwell/pch/chip.h> +#include "chip.h" #include "iobp.h" #include "rcba.h" #include "sata.h" @@ -37,7 +37,7 @@ } static void sata_configure_devslp( - const struct soc_intel_broadwell_pch_config *config, + const struct southbridge_intel_lynxpoint_lp_config *config, const uintptr_t abar) { union abar_reg_cap_2 abar_cap_2 = { @@ -71,7 +71,7 @@ static void sata_init(struct device *dev) { - const struct soc_intel_broadwell_pch_config *config = config_of(dev); + const struct southbridge_intel_lynxpoint_lp_config *config = config_of(dev); u32 reg32; printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n"); @@ -272,7 +272,7 @@ static void sata_enable(struct device *dev) { /* Get the chip configuration */ - const struct soc_intel_broadwell_pch_config *config = config_of(dev); + const struct southbridge_intel_lynxpoint_lp_config *config = config_of(dev); /* * Set SATA controller mode early so the resource allocator can diff --git a/src/soc/intel/broadwell/pch/sata.h b/src/southbridge/intel/lynxpoint_lp/sata.h similarity index 100% rename from src/soc/intel/broadwell/pch/sata.h rename to src/southbridge/intel/lynxpoint_lp/sata.h diff --git a/src/soc/intel/broadwell/pch/serialio.c b/src/southbridge/intel/lynxpoint_lp/serialio.c similarity index 98% rename from src/soc/intel/broadwell/pch/serialio.c rename to src/southbridge/intel/lynxpoint_lp/serialio.c index 0c079be..ce95237 100644 --- a/src/soc/intel/broadwell/pch/serialio.c +++ b/src/southbridge/intel/lynxpoint_lp/serialio.c @@ -7,8 +7,8 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <soc/intel/broadwell/pch/chip.h> +#include "chip.h" #include "iobp.h" #include "nvs.h" #include "pch.h" @@ -155,7 +155,7 @@ static void serialio_init(struct device *dev) { - const struct soc_intel_broadwell_pch_config *config = config_of(dev); + const struct southbridge_intel_lynxpoint_lp_config *config = config_of(dev); struct resource *bar0, *bar1; int sio_index = -1; diff --git a/src/soc/intel/broadwell/pch/serialio.h b/src/southbridge/intel/lynxpoint_lp/serialio.h similarity index 100% rename from src/soc/intel/broadwell/pch/serialio.h rename to src/southbridge/intel/lynxpoint_lp/serialio.h diff --git a/src/soc/intel/broadwell/pch/smbus.c b/src/southbridge/intel/lynxpoint_lp/smbus.c similarity index 100% rename from src/soc/intel/broadwell/pch/smbus.c rename to src/southbridge/intel/lynxpoint_lp/smbus.c diff --git a/src/soc/intel/broadwell/pch/smbus.h b/src/southbridge/intel/lynxpoint_lp/smbus.h similarity index 100% rename from src/soc/intel/broadwell/pch/smbus.h rename to src/southbridge/intel/lynxpoint_lp/smbus.h diff --git a/src/soc/intel/broadwell/pch/smi.c b/src/southbridge/intel/lynxpoint_lp/smi.c similarity index 96% rename from src/soc/intel/broadwell/pch/smi.c rename to src/southbridge/intel/lynxpoint_lp/smi.c index a1cdfda..a157265 100644 --- a/src/soc/intel/broadwell/pch/smi.c +++ b/src/southbridge/intel/lynxpoint_lp/smi.c @@ -6,7 +6,8 @@ #include <arch/io.h> #include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> -#include <soc/intel/broadwell/pch/pm.h> + +#include "pm.h" void smm_southbridge_clear_state(void) { diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/southbridge/intel/lynxpoint_lp/smihandler.c similarity index 100% rename from src/soc/intel/broadwell/pch/smihandler.c rename to src/southbridge/intel/lynxpoint_lp/smihandler.c diff --git a/src/soc/intel/broadwell/pch/spi.h b/src/southbridge/intel/lynxpoint_lp/spi.h similarity index 100% rename from src/soc/intel/broadwell/pch/spi.h rename to src/southbridge/intel/lynxpoint_lp/spi.h diff --git a/src/soc/intel/broadwell/pch/uart.c b/src/southbridge/intel/lynxpoint_lp/uart.c similarity index 100% rename from src/soc/intel/broadwell/pch/uart.c rename to src/southbridge/intel/lynxpoint_lp/uart.c diff --git a/src/soc/intel/broadwell/pch/usb_debug.c b/src/southbridge/intel/lynxpoint_lp/usb_debug.c similarity index 100% rename from src/soc/intel/broadwell/pch/usb_debug.c rename to src/southbridge/intel/lynxpoint_lp/usb_debug.c diff --git a/src/soc/intel/broadwell/pch/usb_ehci.c b/src/southbridge/intel/lynxpoint_lp/usb_ehci.c similarity index 100% rename from src/soc/intel/broadwell/pch/usb_ehci.c rename to src/southbridge/intel/lynxpoint_lp/usb_ehci.c diff --git a/src/soc/intel/broadwell/pch/usb_xhci.c b/src/southbridge/intel/lynxpoint_lp/usb_xhci.c similarity index 100% rename from src/soc/intel/broadwell/pch/usb_xhci.c rename to src/southbridge/intel/lynxpoint_lp/usb_xhci.c diff --git a/src/soc/intel/broadwell/pch/xhci.h b/src/southbridge/intel/lynxpoint_lp/xhci.h similarity index 100% rename from src/soc/intel/broadwell/pch/xhci.h rename to src/southbridge/intel/lynxpoint_lp/xhci.h -- To view, visit https://review.coreboot.org/c/coreboot/+/47047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b55f90e6366b83c75834d7ef57ff2ebdce972b6 Gerrit-Change-Number: 47047 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: sb/intel/lynxpoint/sata.c: Update as per newer reference code
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47032 ) Change subject: sb/intel/lynxpoint/sata.c: Update as per newer reference code ...................................................................... sb/intel/lynxpoint/sata.c: Update as per newer reference code Newer Lynxpoint reference code does some more stuff, which Broadwell already does. Also drop invalid register writes, which were copy-pasted from older southbridges and do not exist anymore on Lynxpoint. Change-Id: I0907905adfa9a21732f1918f143a1df1954275f8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/sata.c 2 files changed, 69 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/47032/1 diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 66cd05e..a1d504c 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -215,51 +215,10 @@ /* PCI Configuration Space (D31:F2): SATA */ #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) -#define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ #define IDE_DECODE_ENABLE (1 << 15) -#define IDE_SITRE (1 << 14) -#define IDE_ISP_5_CLOCKS (0 << 12) -#define IDE_ISP_4_CLOCKS (1 << 12) -#define IDE_ISP_3_CLOCKS (2 << 12) -#define IDE_RCT_4_CLOCKS (0 << 8) -#define IDE_RCT_3_CLOCKS (1 << 8) -#define IDE_RCT_2_CLOCKS (2 << 8) -#define IDE_RCT_1_CLOCKS (3 << 8) -#define IDE_DTE1 (1 << 7) -#define IDE_PPE1 (1 << 6) -#define IDE_IE1 (1 << 5) -#define IDE_TIME1 (1 << 4) -#define IDE_DTE0 (1 << 3) -#define IDE_PPE0 (1 << 2) -#define IDE_IE0 (1 << 1) -#define IDE_TIME0 (1 << 0) #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ -#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ -#define IDE_SSDE1 (1 << 3) -#define IDE_SSDE0 (1 << 2) -#define IDE_PSDE1 (1 << 1) -#define IDE_PSDE0 (1 << 0) - -#define IDE_SDMA_TIM 0x4a - -#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ -#define SIG_MODE_SEC_NORMAL (0 << 18) -#define SIG_MODE_SEC_TRISTATE (1 << 18) -#define SIG_MODE_SEC_DRIVELOW (2 << 18) -#define SIG_MODE_PRI_NORMAL (0 << 16) -#define SIG_MODE_PRI_TRISTATE (1 << 16) -#define SIG_MODE_PRI_DRIVELOW (2 << 16) -#define FAST_SCB1 (1 << 15) -#define FAST_SCB0 (1 << 14) -#define FAST_PCB1 (1 << 13) -#define FAST_PCB0 (1 << 12) -#define SCB1 (1 << 3) -#define SCB0 (1 << 2) -#define PCB1 (1 << 1) -#define PCB0 (1 << 0) - #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ #define SATA_SP 0xd0 /* Scratchpad */ diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index d8eb2a8..18dbb00 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -7,6 +7,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <delay.h> +#include <southbridge/intel/common/abar.h> #include "chip.h" #include "iobp.h" #include "pch.h" @@ -37,50 +38,35 @@ { u32 reg32; - u32 *abar; - /* Get the chip configuration */ config_t *config = dev->chip_info; - printk(BIOS_DEBUG, "SATA: Initializing...\n"); + printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n"); if (config == NULL) { printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); return; } - /* SATA configuration */ - /* Enable memory space decoding for ABAR */ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); + const uintptr_t abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "ABAR: %p\n", (void *)abar); /* Set Interrupt Line */ /* Interrupt Pin is set by D31IP.PIP */ - pci_write_config8(dev, INTR_LN, 0x0a); + pci_write_config8(dev, PCI_INTERRUPT_LINE, 0x0a); - /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); /* for AHCI, Port Enable is managed in memory mapped space */ pci_update_config16(dev, 0x92, ~0x3f, 0x8000 | config->sata_port_map); udelay(2); /* Setup register 98h */ - reg32 = pci_read_config16(dev, 0x98); + reg32 = pci_read_config32(dev, 0x98); reg32 |= 1 << 19; /* BWG step 6 */ reg32 |= 1 << 22; /* BWG step 5 */ reg32 &= ~(0x3f << 7); @@ -93,7 +79,7 @@ if (pch_is_lp()) { reg32 &= ~((1 << 31) | (1 << 30)); reg32 |= 1 << 23; - reg32 |= 1 << 24; /* Disable listen mode (hotplug) */ + reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */ } pci_write_config32(dev, 0x98, reg32); @@ -107,31 +93,60 @@ pci_write_config32(dev, 0x94, reg32); /* Initialize AHCI memory-mapped space */ - abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS - reg32 &= ~0x00020060; // clear SXS+EMS+PMS + + union abar_reg_cap abar_cap = { + .raw = abar_read32(abar, ABAR_REG_CAP), + }; + + abar_cap.external_sata = 0; /* Should be configurable */ + abar_cap.enclosure_management = 0; + abar_cap.port_multiplier = 0; + abar_cap.interlock_switch = 0; + + abar_cap.partial_state = 1; + abar_cap.slumber_state = 1; + abar_cap.pio_multiple_drq = 1; + abar_cap.cmd_list_override = 1; + abar_cap.interface_speed = 3; + abar_cap.aggressive_link_pm = 1; + abar_cap.staggered_spinup = 1; + if (pch_is_lp()) - reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY - write32(abar + 0x00, reg32); - /* PI (Ports implemented) */ - write32(abar + 0x03, config->sata_port_map); - (void)read32(abar + 0x03); /* Read back 1 */ - (void)read32(abar + 0x03); /* Read back 2 */ - /* CAP2 (HBA Capabilities Extended)*/ - reg32 = read32(abar + 0x09); - /* Enable DEVSLP */ + abar_cap.ahci_mode_only = 1; + + abar_write32(abar, ABAR_REG_CAP, abar_cap.raw); + + abar_write_ports_implemented(abar, config->sata_port_map); + + union abar_reg_cap_2 abar_cap_2 = { + .raw = abar_read32(abar, ABAR_REG_CAP_2), + }; + if (pch_is_lp()) { - if (config->sata_devslp_disable) - reg32 &= ~(1 << 3); - else - reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); - } else { - reg32 &= ~0x00000002; + if (config->sata_devslp_disable) { + abar_cap_2.supports_device_sleep = 0; + + abar_write32(abar, ABAR_REG_CAP_2, abar_cap_2.raw); + } else { + abar_cap_2.auto_partial_to_slumber = 1; + abar_cap_2.supports_device_sleep = 1; + abar_cap_2.aggressive_devslp_mgmt = 1; + abar_cap_2.devslp_entry_slumber_only = 1; + + abar_write32(abar, ABAR_REG_CAP_2, abar_cap_2.raw); + + for (int port = 0; port < 4; port++) { + if (!(config->sata_port_map & (1 << port))) + continue; + + union abar_reg_px_devslp px_devslp = { + .raw = abar_read32(abar, ABAR_REG_PxDEVSLP(port)), + }; + px_devslp.device_sleep_present = 1; + abar_write32(abar, ABAR_REG_PxDEVSLP(port), px_devslp.raw); + } + } } - write32(abar + 0x09, reg32); /* Set Gen3 Transmitter settings if needed */ if (config->sata_port0_gen3_tx) @@ -167,8 +182,9 @@ << SATA_DTLE_EDGE_SHIFT); } - /* Additional Programming Requirements */ - /* Power Optimizer */ + /* + * Additional Programming Requirements for Power Optimizer + */ /* Step 1 */ if (pch_is_lp()) @@ -196,9 +212,14 @@ } reg32 = pci_read_config32(dev, 0x300); - reg32 |= (1 << 17) | (1 << 16); + reg32 |= (1 << 17) | (1 << 16) | (1 << 19); reg32 |= (1 << 31) | (1 << 30) | (1 << 29); pci_write_config32(dev, 0x300, reg32); + + pci_or_config32(dev, 0x98, 1 << 29); + + /* Register Lock */ + pci_or_config32(dev, 0x9c, 1 << 31); } static void sata_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/47032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0907905adfa9a21732f1918f143a1df1954275f8 Gerrit-Change-Number: 47032 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] common sb/intel fadt
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43470 ) Change subject: [WIP] common sb/intel fadt ...................................................................... [WIP] common sb/intel fadt Change-Id: I6b995d526d6781d1f53c017068ed83ea46a93f32 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc A src/southbridge/intel/common/fadt.c A src/southbridge/intel/common/fadt.h 4 files changed, 81 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/43470/1 diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 9356a2b..a3095bc 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -52,6 +52,9 @@ select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select SOUTHBRIDGE_INTEL_COMMON_PMBASE +config SOUTHBRIDGE_INTEL_COMMON_ACPI_FADT + bool + config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT bool diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index b3c48fa..77f0795 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -35,6 +35,7 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smi.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smihandler.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_FADT) += fadt.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT) += madt.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c diff --git a/src/southbridge/intel/common/fadt.c b/src/southbridge/intel/common/fadt.c new file mode 100644 index 0000000..31feff6 --- /dev/null +++ b/src/southbridge/intel/common/fadt.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/common/fadt.h> +#include <southbridge/intel/common/pmbase.h> + +/* FIXME: pmutil.h definitions are a mess */ +#define PM1_STS 0x00 +#define PM1_CNT 0x04 +#define PM1_TMR 0x08 +#define GPE0_STS 0x20 +#define PM2_CNT 0x50 + +#define PM1A_EVT_BYTES 4 +#define PM1A_CNT_BYTES 2 +#define PM2_CNT_BYTES 1 +#define PM_TMR_BYTES 4 +#define GPE0_BYTES 16 + +void acpi_fill_fadt(acpi_fadt_t *fadt) +{ + const u16 pmbase = lpc_get_pmbase(); + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm2_cnt_blk = pmbase + PM2_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = 128; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; +} diff --git a/src/southbridge/intel/common/fadt.h b/src/southbridge/intel/common/fadt.h new file mode 100644 index 0000000..48fe1cd --- /dev/null +++ b/src/southbridge/intel/common/fadt.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_COMMON_FADT_H +#define SOUTHBRIDGE_INTEL_COMMON_FADT_H + +#endif /* SOUTHBRIDGE_INTEL_COMMON_FADT_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/43470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b995d526d6781d1f53c017068ed83ea46a93f32 Gerrit-Change-Number: 43470 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/Makefile.inc: Enable UBSAN on SMM, too
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43976 ) Change subject: lib/Makefile.inc: Enable UBSAN on SMM, too ...................................................................... lib/Makefile.inc: Enable UBSAN on SMM, too We don't want undefined behavior on such privileged code, do we? Change-Id: I24f4c074ff90365cf96abf1f5bad3e2cde68547d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/lib/Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/43976/1 diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 72d4f24..c96aa90 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -4,7 +4,9 @@ ifeq ($(CONFIG_UBSAN),y) ramstage-y += ubsan.c +smm-y += ubsan.c CFLAGS_ramstage += -fsanitize=undefined +CFLAGS_smm += -fsanitize=undefined endif decompressor-y += decompressor.c -- To view, visit https://review.coreboot.org/c/coreboot/+/43976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24f4c074ff90365cf96abf1f5bad3e2cde68547d Gerrit-Change-Number: 43976 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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