Change in coreboot[master]: soc/intel/common/cache_as_ram.S: Add macro to clear CAR

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Arthur Heymans (Code Review)

25 Nov 2019 25 Nov '19

10:03 a.m.

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37191 )

Change subject: soc/intel/common/cache_as_ram.S: Add macro to clear CAR ......................................................................

soc/intel/common/cache_as_ram.S: Add macro to clear CAR

Add a macro to clear CAR which is replicated 3 times in this code.

Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 15 insertions(+), 20 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/37191/1

diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index d1ae6ca..6a0728d 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -48,6 +48,17 @@ 3: .endm

+ .macro clear_car + /* Clear the cache memory region. This will also fill up the cache */ + movl $CONFIG_DCACHE_RAM_BASE, %edi + movl $CONFIG_DCACHE_RAM_SIZE, %ecx + shr $0x02, %ecx + xor %eax, %eax + cld + rep stosl + .endm + + .global bootblock_pre_c_entry bootblock_pre_c_entry:

@@ -256,13 +267,7 @@

post_code(0x26)

- /* Clear the cache memory region. This will also fill up the cache */ - movl $CONFIG_DCACHE_RAM_BASE, %edi - movl $CONFIG_DCACHE_RAM_SIZE, %ecx - shr $0x02, %ecx - xor %eax, %eax - cld - rep stosl + clear_car

post_code(0x27)

@@ -353,13 +358,7 @@

post_code(0x26)

post_code(0x27)

@@ -462,12 +461,8 @@ xorl %edx, %edx wrmsr

- movl $CONFIG_DCACHE_RAM_BASE, %edi - movl $CONFIG_DCACHE_RAM_SIZE, %ecx - shr $0x02, %ecx - xor %eax, %eax - cld - rep stosl + clear_car + /* * Set IA32_PQR_ASSOC = 0x01 * At this stage we apply LLC_WAY_MASK_1 to the cache.

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Arthur Heymans (Code Review)

25 Nov 25 Nov

11:03 a.m.

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37191

to look at the new patch set (#2).

Change subject: soc/intel/common/cache_as_ram.S: Add macro to clear CAR ......................................................................

soc/intel/common/cache_as_ram.S: Add macro to clear CAR

Add a macro to clear CAR which is replicated 3 times in this code.

TEST: with BUILD_TIMELESS=1 the resulting binary is identical.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/37191/2

Arthur Heymans (Code Review)

noon

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37191

to look at the new patch set (#3).

Change subject: soc/intel/common/cache_as_ram.S: Add macro to clear CAR ......................................................................

soc/intel/common/cache_as_ram.S: Add macro to clear CAR

Add a macro to clear CAR which is replicated 3 times in this code.

TEST: with BUILD_TIMELESS=1 the resulting binary is identical.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/37191/3

Patrick Georgi (Code Review)

4 Dec 4 Dec

9:50 p.m.

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37191 )

Change subject: soc/intel/common/cache_as_ram.S: Add macro to clear CAR ......................................................................

Patch Set 3: Code-Review+2

Angel Pons (Code Review)

19 Jan 19 Jan

11:54 p.m.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37191 )

Change subject: soc/intel/common/cache_as_ram.S: Add macro to clear CAR ......................................................................

Patch Set 4: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/37191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Gerrit-Change-Number: 37191 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Sun, 19 Jan 2020 22:54:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Angel Pons (Code Review)

20 Jan 20 Jan

12:07 a.m.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37191 )

Change subject: soc/intel/common/cache_as_ram.S: Add macro to clear CAR ......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37191/4/src/soc/intel/common/block/... File src/soc/intel/common/block/cpu/car/cache_as_ram.S:

https://review.coreboot.org/c/coreboot/+/37191/4/src/soc/intel/common/block/... PS4, Line 58: .macro clear_car Maybe don't indent this? it would make things more consistent

-- To view, visit https://review.coreboot.org/c/coreboot/+/37191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Gerrit-Change-Number: 37191 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Sun, 19 Jan 2020 23:07:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Arthur Heymans (Code Review)

4:42 p.m.

Hello Patrick Rudolph, Angel Pons, build bot (Jenkins), Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37191

to look at the new patch set (#5).

Change subject: soc/intel/common/cache_as_ram.S: Add macro to clear CAR ......................................................................

soc/intel/common/cache_as_ram.S: Add macro to clear CAR

Add a macro to clear CAR which is replicated 3 times in this code.

TEST: with BUILD_TIMELESS=1 the resulting binary is identical.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/37191/5

Tim Wawrzynczak (Code Review)

15 Jul 15 Jul

10:23 p.m.

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37191 )

Change subject: soc/intel/common/cache_as_ram.S: Add macro to clear CAR ......................................................................

Patch Set 6: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/37191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Gerrit-Change-Number: 37191 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Tim Wawrzynczak twawrzynczak@chromium.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Wed, 15 Jul 2020 20:23:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Arthur Heymans (Code Review)

15 Jun 15 Jun

9:53 a.m.

Attention is currently required from: Arthur Heymans. Arthur Heymans has uploaded a new patch set (#7) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/37191 )

Change subject: soc/intel/common/cache_as_ram.S: Add macro to clear CAR ......................................................................

soc/intel/common/cache_as_ram.S: Add macro to clear CAR

Add a macro to clear CAR which is replicated 3 times in this code.

TEST: with BUILD_TIMELESS=1 the resulting binary is identical.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/37191/7

-- To view, visit https://review.coreboot.org/c/coreboot/+/37191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Gerrit-Change-Number: 37191 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Tim Wawrzynczak twawrzynczak@chromium.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@mailbox.org Gerrit-Attention: Arthur Heymans arthur.heymans@9elements.com Gerrit-MessageType: newpatchset

Angel Pons (Code Review)

10:54 a.m.

Attention is currently required from: Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37191 )

Change subject: soc/intel/common/cache_as_ram.S: Add macro to clear CAR ......................................................................

Patch Set 7:

(2 comments)

File src/soc/intel/common/block/cpu/car/cache_as_ram.S:

https://review.coreboot.org/c/coreboot/+/37191/comment/1f55f2b2_d628db98 PS4, Line 58: .macro clear_car

...

Maybe don't indent this? it would make things more consistent

Ack

File src/soc/intel/common/block/cpu/car/cache_as_ram.S:

https://review.coreboot.org/c/coreboot/+/37191/comment/8b920345_a24bf5d2 PS7, Line 44: /* nit: drop indentation for comment?

-- To view, visit https://review.coreboot.org/c/coreboot/+/37191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Gerrit-Change-Number: 37191 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Tim Wawrzynczak twawrzynczak@chromium.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@mailbox.org Gerrit-Attention: Arthur Heymans arthur.heymans@9elements.com Gerrit-Attention: Arthur Heymans arthur@aheymans.xyz Gerrit-Comment-Date: Tue, 15 Jun 2021 08:54:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons th3fanbus@gmail.com Gerrit-MessageType: comment

Arthur Heymans (Code Review)

16 Jun 16 Jun

9:35 a.m.

Attention is currently required from: Arthur Heymans, Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37191 )

Change subject: soc/intel/common/cache_as_ram.S: Add macro to clear CAR ......................................................................

Patch Set 7:

(1 comment)

File src/soc/intel/common/block/cpu/car/cache_as_ram.S:

https://review.coreboot.org/c/coreboot/+/37191/comment/ac1646ba_79393293 PS7, Line 44: /*

...

nit: drop indentation for comment?

Done

-- To view, visit https://review.coreboot.org/c/coreboot/+/37191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Gerrit-Change-Number: 37191 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Tim Wawrzynczak twawrzynczak@chromium.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@mailbox.org Gerrit-Attention: Arthur Heymans arthur.heymans@9elements.com Gerrit-Attention: Angel Pons th3fanbus@gmail.com Gerrit-Comment-Date: Wed, 16 Jun 2021 07:35:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons th3fanbus@gmail.com Gerrit-MessageType: comment

Arthur Heymans (Code Review)

9:35 a.m.

Attention is currently required from: Arthur Heymans, Angel Pons. Hello build bot (Jenkins), Patrick Georgi, Tim Wawrzynczak, Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37191

to look at the new patch set (#8).

Change subject: soc/intel/common/cache_as_ram.S: Add macro to clear CAR ......................................................................

soc/intel/common/cache_as_ram.S: Add macro to clear CAR

Add a macro to clear CAR which is replicated 3 times in this code.

TEST: with BUILD_TIMELESS=1 the resulting binary is identical.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/37191/8

-- To view, visit https://review.coreboot.org/c/coreboot/+/37191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Gerrit-Change-Number: 37191 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Tim Wawrzynczak twawrzynczak@chromium.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@mailbox.org Gerrit-Attention: Arthur Heymans arthur.heymans@9elements.com Gerrit-Attention: Angel Pons th3fanbus@gmail.com Gerrit-MessageType: newpatchset

Angel Pons (Code Review)

12:56 p.m.

Attention is currently required from: Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37191 )

Change subject: soc/intel/common/cache_as_ram.S: Add macro to clear CAR ......................................................................

Patch Set 9:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/37191/comment/30566ba1_6d26bc65 PS9, Line 11: the resulting binary For which board?

-- To view, visit https://review.coreboot.org/c/coreboot/+/37191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Gerrit-Change-Number: 37191 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Tim Wawrzynczak twawrzynczak@chromium.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@mailbox.org Gerrit-Attention: Arthur Heymans arthur@aheymans.xyz Gerrit-Comment-Date: Wed, 16 Jun 2021 10:56:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Arthur Heymans (Code Review)

1:13 p.m.

Attention is currently required from: Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37191 )

Change subject: soc/intel/common/cache_as_ram.S: Add macro to clear CAR ......................................................................

Patch Set 9:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/37191/comment/71045dc4_2376b1fe PS9, Line 11: the resulting binary

...

For which board?

I don't remember. I just copied the message from something like 2 years ago. It should be the same for all code using cache_as_ram.S

-- To view, visit https://review.coreboot.org/c/coreboot/+/37191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Gerrit-Change-Number: 37191 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Tim Wawrzynczak twawrzynczak@chromium.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@mailbox.org Gerrit-Attention: Angel Pons th3fanbus@gmail.com Gerrit-Comment-Date: Wed, 16 Jun 2021 11:13:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons th3fanbus@gmail.com Gerrit-MessageType: comment

Patrick Rudolph (Code Review)

21 Jun 21 Jun

8:47 a.m.

Attention is currently required from: Angel Pons, Arthur Heymans. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37191 )

Change subject: soc/intel/common/cache_as_ram.S: Add macro to clear CAR ......................................................................

Patch Set 9: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/37191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Gerrit-Change-Number: 37191 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Tim Wawrzynczak twawrzynczak@chromium.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@mailbox.org Gerrit-Attention: Angel Pons th3fanbus@gmail.com Gerrit-Attention: Arthur Heymans arthur@aheymans.xyz Gerrit-Comment-Date: Mon, 21 Jun 2021 06:47:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Patrick Georgi (Code Review)

22 Jun 22 Jun

3:14 p.m.

Attention is currently required from: Angel Pons, Arthur Heymans. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37191 )

Change subject: soc/intel/common/cache_as_ram.S: Add macro to clear CAR ......................................................................

Patch Set 9: Code-Review+2

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/37191/comment/c4db32f9_c0a38cb7 PS9, Line 11: the resulting binary

...

...
For which board? […]

Looking at the code, I see little room for divergence, so "all boards" seems to be both right and redundant, so let's leave it the way it is.

-- To view, visit https://review.coreboot.org/c/coreboot/+/37191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Gerrit-Change-Number: 37191 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Tim Wawrzynczak twawrzynczak@chromium.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@mailbox.org Gerrit-Attention: Angel Pons th3fanbus@gmail.com Gerrit-Attention: Arthur Heymans arthur@aheymans.xyz Gerrit-Comment-Date: Tue, 22 Jun 2021 13:14:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons th3fanbus@gmail.com Comment-In-Reply-To: Arthur Heymans arthur@aheymans.xyz Gerrit-MessageType: comment

Patrick Georgi (Code Review)

3:14 p.m.

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37191 )

Change subject: soc/intel/common/cache_as_ram.S: Add macro to clear CAR ......................................................................

soc/intel/common/cache_as_ram.S: Add macro to clear CAR

Add a macro to clear CAR which is replicated 3 times in this code.

TEST: with BUILD_TIMELESS=1 the resulting binary is identical.

Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/37191 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org Reviewed-by: Patrick Georgi pgeorgi@google.com --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 22 insertions(+), 20 deletions(-)

Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Patrick Rudolph: Looks good to me, approved

diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index db1345a..5da453b 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -41,6 +41,23 @@ decl %ecx .endm

+/* + * macro: clear_car + * Clears the region between CONFIG_DCACHE_RAM_BASE and + * CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE to populate + * cachelines. + * Clobbers %eax, %ecx, %edi. + */ +.macro clear_car + /* Clear the cache memory region. This will also fill up the cache */ + movl $CONFIG_DCACHE_RAM_BASE, %edi + movl $CONFIG_DCACHE_RAM_SIZE, %ecx + shr $0x02, %ecx + xor %eax, %eax + cld + rep stosl +.endm + .global bootblock_pre_c_entry bootblock_pre_c_entry:

@@ -256,13 +273,7 @@

post_code(0x26)

post_code(0x27)

@@ -353,13 +364,7 @@

post_code(0x26)

post_code(0x27)

@@ -518,12 +523,9 @@ movl $0x02, %eax #endif wrmsr - movl $CONFIG_DCACHE_RAM_BASE, %edi - movl $CONFIG_DCACHE_RAM_SIZE, %ecx - shr $0x02, %ecx - xor %eax, %eax - cld - rep stosl + + clear_car + /* * Set IA32_PQR_ASSOC * At this stage we apply LLC_WAY_MASK_1 to the cache.

-- To view, visit https://review.coreboot.org/c/coreboot/+/37191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Gerrit-Change-Number: 37191 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Tim Wawrzynczak twawrzynczak@chromium.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@mailbox.org Gerrit-MessageType: merged

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participants (5)

Angel Pons (Code Review)
Arthur Heymans (Code Review)
Patrick Georgi (Code Review)
Patrick Rudolph (Code Review)
Tim Wawrzynczak (Code Review)