Arthur Heymans has uploaded this change for review.
soc/intel/common/cache_as_ram.S: Add macro to clear CAR
Add a macro to clear CAR which is replicated 3 times in this code.
Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
1 file changed, 15 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/37191/1
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index d1ae6ca..6a0728d 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -48,6 +48,17 @@
3:
.endm
+ .macro clear_car
+ /* Clear the cache memory region. This will also fill up the cache */
+ movl $CONFIG_DCACHE_RAM_BASE, %edi
+ movl $CONFIG_DCACHE_RAM_SIZE, %ecx
+ shr $0x02, %ecx
+ xor %eax, %eax
+ cld
+ rep stosl
+ .endm
+
+
.global bootblock_pre_c_entry
bootblock_pre_c_entry:
@@ -256,13 +267,7 @@
post_code(0x26)
- /* Clear the cache memory region. This will also fill up the cache */
- movl $CONFIG_DCACHE_RAM_BASE, %edi
- movl $CONFIG_DCACHE_RAM_SIZE, %ecx
- shr $0x02, %ecx
- xor %eax, %eax
- cld
- rep stosl
+ clear_car
post_code(0x27)
@@ -353,13 +358,7 @@
post_code(0x26)
- /* Clear the cache memory region. This will also fill up the cache */
- movl $CONFIG_DCACHE_RAM_BASE, %edi
- movl $CONFIG_DCACHE_RAM_SIZE, %ecx
- shr $0x02, %ecx
- xor %eax, %eax
- cld
- rep stosl
+ clear_car
post_code(0x27)
@@ -462,12 +461,8 @@
xorl %edx, %edx
wrmsr
- movl $CONFIG_DCACHE_RAM_BASE, %edi
- movl $CONFIG_DCACHE_RAM_SIZE, %ecx
- shr $0x02, %ecx
- xor %eax, %eax
- cld
- rep stosl
+ clear_car
+
/*
* Set IA32_PQR_ASSOC = 0x01
* At this stage we apply LLC_WAY_MASK_1 to the cache.
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