Arthur Heymans uploaded patch set #2 to this change.

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soc/intel/common/cache_as_ram.S: Add macro to clear CAR

Add a macro to clear CAR which is replicated 3 times in this code.

TEST: with BUILD_TIMELESS=1 the resulting binary is identical.

Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
1 file changed, 14 insertions(+), 20 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/37191/2

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae
Gerrit-Change-Number: 37191
Gerrit-PatchSet: 2
Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz>
Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-MessageType: newpatchset